HORUS: is semi-formal verification the future of simulation?
During the design process of an IP, its functional verification is
considered a long and painful task. Assertion-based
verification of logic and temporal properties can be performed
with a variety of methods that can save considerable time.
The traditional design flow
The approach we developed is illustrated by the figure hereafter.
The left part of the diagram shows the usual design flow together
with the various levels of simulation-based verification, and the
right part exhibits the same verification steps with assertions.
This second approach complements, possibly replaces, the time-consuming test
vector elaboration, and helps interpret the results. At all levels of
the design flow, assertions help describe:
the results expected from the IP (assert),
the constraints on the inputs (assume).
The HORUS environment
From declarative assertions written in PSL or in SVA, synthesizable
designs are automatically produced in Verilog or in VHDL for:
Back to the VDS Home Page
The HORUS technology is now integrated inside Dolphin Integration tools
(simulator and
schematic editor):
article in French 