
Research Areas
Assertion-based verification at RT Level: modular design of checkers and test generators (Horus project)
Formal verification of Network on Chip (NoC) communication architectures using theorem proving techniques
Evaluation of error consequences using formal methods ("FME3" ANR project)


| Group Leader: | Laurence PIERRE |
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TIMA 46, avenue Félix Viallet 38031 GRENOBLE Cedex France |
| Phone: | (+33) 4 76 57 49 92 |
| Fax: | (+33) 4 76 57 49 81 |
This web site was last updated on December 5, 2009