TIMA - VDS Group

Research Areas

The design of first time correct Systems-on-Chip involves, among many other challenges, guaranteeing that the system will behave according to a specified set of functionalities. The VDS group is mainly concerned by the correctness of the hardware design, from its early specification levels to the "register transfer" level (RTL). Among the current projects:

Assertion-based verification at RT Level: modular design of checkers and test generators (Horus project), assertions checkers in synchronous and in QDI asynchronous technologies
Assertion-based verification of SystemC TLM designs
Formal verification of Network on Chip (NoC) communication architectures using theorem proving techniques
Automatic synthesis of correct by construction systems from PSL assertions
Evaluation of error consequences using formal methods

Group Leader:	Laurence PIERRE
	TIMA 46, avenue Félix Viallet 38031 GRENOBLE Cedex France
Phone:	(+33) 4 76 57 49 92
Fax:	(+33) 4 76 57 49 81

This web site was last updated on May 4, 2012