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Propositions de thèses
Design-for-test strategies for built-in static test of high-performance SAR ADCs
Équipe : RMS
Date de début : 1st October 2017
Durée : 3 years
Profil : Proposition de sujet de thèse:
The integration capabilities offered by current nanoscale CMOS technologies enable the fabrication of complete and very complex mixed-signal systems on a single die. However, manufacturing processes are prone to imperfections that may degrade the intended functionality of the fabricated circuits. Extensive production tests are needed in order to separate defective or unreliable parts from functionally correct devices. Unfortunately, the co-integration of blocks of very distinct nature (analog, mixed- signal, digital, RF ...) as well as the limited access to internal nodes in an integrated system make the test of these devices a very challenging and costly task. Nowadays, testing the analog, mixed-signal, and radio-frequency (RF) functions of ICs results in a high cost that may amount up to 50% of the overall manufacturing cost. The test cost is expected to rise in the coming years as ICs include ever more functionality and as we move to smaller technology nodes for which process variations and defect density become more prevalent. Therefore, reducing the cost of testing for analog, mixed-signal, and RF circuits is an area of focus and innovation for the semiconductor industry.
This thesis envisages the development of novel reduced-code static linearity test techniques for built-in test of high-performance Analog-to-Digital converters (ADCs). Reduced-code static linearity test takes advantage of the repetitive operation of some ADC architectures (e.g., pipeline, SARs, algorithmic, etc.) to infer the complete static linearity transfer function of the converter by measuring only a reduced set of output codes. On the other hand, built-in test consists of migrating some of the test instruments into the IC, in order to facilitate and speed- up testing.
Specifically, the goal of this thesis is the development of novel reduced code linearity test techniques for Successive-Approximation-Register (SAR) ADCs that may enable the definition of an efficient static linearity BIST for this type of converters. Enabling BIST not only speeds-up and reduces the cost of testing, but it also opens the door to enhanced reliability during the lifetime of the circuit. For example, built-in test may enable on- line test, self-healing, self-calibration and adaptive operation in safety-critical and mission-critical applications.
Project: HADES (EUREKA PENTA program)
Funding: Research contract HADES project, with a gross salary of about 2500 Euro/month (a net salary of 1450 Euro/month).
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Personne à contacter : Manuel J Barragan, Salvador Mir