Laboratoire TIMA


Le prochain Conseil Scientifique aura lieu

Lundi 27 février 2017, à 14 h 00 en T312, FRANCE

> en savoir plus

Le prochain Conseil de Laboratoire aura lieu

Jeudi 9 mars 2017, à 14 h 00 en T312, FRANCE

Ordre du jour : à venir

> en savoir plus


18th IEEE Latin American Test Symposium

Venue: Bogota, COLOMBIA
Date: 13th - 15th March 2017

Summary: The IEEE Latin-American Test Symposium (LATS, previously Latin-American Test Workshop - LATW) is a recognized forum for test and fault tolerance professionals and technologists from all over the world, in particular from Latin America, to present and discuss various aspects of system, board, and component testing and fault-tolerance with design, manufacturing and field considerations in mind. Presented papers are also published in the IEEE Xplore Digital Library. The best papers of the 18th LATS will be invited to re-submit to IEEE Design and Test of Computers, Journal of Electronic Testing: Theory and Applications - JETTA (Springer), Journal of Low Power Electronics - JOLPE (American Scientific Publishers), and IEEE Transactions on Computer-Aided Design (TCAD).

> en savoir plus

South European Test Seminar 2017

Venue: Alpe d'Huez, France, FRANCE
Date: 20 au 24 March 2017

> en savoir plus



Theme: Processeur parallélisant à beaucoup de cœurs
Date: 23/03/2017 à 15 h 00, Laboratoire TIMA - Salle T312

> en savoir plus

Thèses soutenances

« Actuellement il n’y aucune soutenance prévue »


Dominique Borrione est membre d'honneur de la société informatique de France 2017

Project: Dominique Borrione

Professeur émérite à l’Université Grenoble Alpes, Dominique Borrione a été Professeur à l’Université de Provence, Marseille (Déc. 1983 – Août 1988) avant de muter à l’Université de Grenoble en 1988. Elle a assuré la direction des laboratoires IMAG-ARTEMIS (Jan. 1992-Déc 1995) et TIMA (janv 2007 à déc 2014) à Grenoble. Ses domaines d’expertise portent sur les langages de description et de simulation des systèmes matériels numériques, les méthodes formelles et semi-formelles pour la description, la spécification, la vérification, la synthèse de systèmes intégrés numériques.


Le 28 janvier 2017


Best Paper Award at the SNUG (Synopsys User Group) Conference

Project: Titre : Conclusive Formal Verification of Clock Domain Crossings using SpyGlass-CDC

Auteurs : Mejid Kebaili (STMicroelectronics) & Guillaume Plassan (Synopsys) (deux doctorants de TIMA/AMFORS en thèse CIFRE:
Guillaume Plassan: CIFRE avec Synopsys
Mejid Kebaili:CIFRE avec STMicroelectronics
Récompense : “Best Paper Award” from the Technical Committee

Abstract :
In modern designs, the correct propagation of data through clock domains is ensured by implementing specific synchronizer protocols.
Then, to guarantee the absence of metastability, data loss or incoherence, the functional correctness of each CDC (Clock Domain Crossing) must be verified by using formal techniques.
However, flat verification of large designs often leads to an inconclusive status (neither proved nor failed) with limited debug capabilities.
In order to ease the formal analysis, an enhanced solution, called the Reactive flow, has been developed in the context of ST / Synopsys collaboration.
It consists of automatically abstracting irrelevant parts of the design in order to provide at least a local cause for a fail.
Also, our flow generates potential missing constraints to setup the design and to guide the formal analysis.
This methodology has been performed on large CPU 64 bits Sub-Systems with positive results.

le 28/06/2016 au World Trade Center de Grenoble


Best Paper Award at NANOARCH 2016 symposium

Project: Titre : Multi-contex Non-volatile Content Adressable Momory using Magnetic Tunnel Junctions

Auteurs : E. Deng (TIMA, AMfoRS), L. Anghel (TIMA, AMfoRS), G. Prenat(TIMA, RMS), W. Zhao (TIMA, AMfoRS)

Récompense: 2016 Best Paper Award at the 12th IEEE/ACM International Symposium on Nanoscale Architectures, July 18-20, 2016, Beijing, China

18-20 Juillet 2016



Embedded test instruments for high-performance Analog-to-Digital Converters in advanced nanometric technological nodes

Équipe : RMS

Date de début : April 2017

Durée : 1 year

Profil : The integration capabilities offered by current nanoscale CMOS technologies enable the fabrication of complete and very complex mixed-signal systems on a single die. However, manufacturing processes are prone to imperfections that may degrade the intended functionality of the fabricated circuits. Extensive production tests are needed in order to separate defective or unreliable parts from functionally correct devices. Unfortunately, the co-integration of blocks of very distinct nature (analog, mixed-signal, digital, RF, ...) as well as the limited access to internal nodes in an integrated system make the test of these devices a very challenging and costly task. Nowadays, testing the analog, mixed-signal, and radio-frequency (RF) functions of ICs results in a high cost that may amount up to 50% of the overall manufacturing cost. The test cost is expected to rise in the coming years as ICs include ever more functionality and as we move to smaller technology nodes for which process variations and defect density become more prevalent. Therefore, reducing the cost of testing for analog, mixed-signal, and RF circuits is an area of focus and innovation for the semiconductor industry.

This post-doc project envisages built-in test solutions for high-performance Analog-to-Digital converters (ADCs). Built-in test consists of migrating some of the test instruments into the IC, in order to facilitate and speed-up testing. For example, built-in test could consist of generating test stimuli on-chip, performing and processing measurements on-chip, etc. Built-in test can also help to diagnose the source of failure and, thereby, enhance production yield through appropriate actions. Furthermore, embedded test instruments may enable on-line test, self-healing, self-calibration and adaptive operation in safety-critical and mission-critical applications.

Specifically, this post-doc aims at the development of efficient built-in test instruments for static test of ADCs in a nanometric technology with the final goal of integrating a self-testable ADC demonstrator.

• See complete information to : Follow the link.

Personne à contacter : Manuel J?? Barragan, Salvador Mir