Laboratoire TIMA

Actualités


Le prochain Conseil de Laboratoire aura lieu le

27/06/2017 à 14 h 00, Laboratoire TIMA - Salle T312, FRANCE

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Conférences

23rd IEEE International Symposium on On-Line Testing and Robust System Design

IOLTS
Venue: Hotel Makedonia Palace, Thessaloniki, GREECE
Date: July 3-5, 2017

Summary: Issues related to On-line testing techniques, and more generally to design for robustness, are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective design for robustness techniques. These needs have increased dramatically with the introduction of nanometer technologies, which impact adversely noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of design for robustness techniques for extending, yield, reliability, and lifetime of modern SoCs. Design for reliability becomes also mandatory for reducing power dissipation, as voltage reduction, often used to reduce power, strongly affects reliability by reducing noise margins and thus the sensitivity to soft-errors and EMI, and by increasing circuit delays and thus the severity of timing faults. There is also a strong relation between Design for Reliability and Design for Security, as security attacks are often fault-based. The International Symposium on On-Line Testing and Robust System Design (IOLTS), is an established forum for presenting novel ideas and experimental data on these areas. The Symposium is sponsored by the IEEE Council on Electronic Design Automation (CEDA) and the 2017 edition is organized by the IEEE Computer Society Test Technology Technical Council, the University of Athens, and the TIMA Laboratory.

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2nd IEEE Federative Event on Design for Robustness

FEDfRo
Venue: Hotel Macedonia Palace, Thessaloniki, GREECE
Date: July 3-5, 2017

Summary: Nanometer scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of efficient techniques for improving yield and reliability, extending lifespan, and reducing power dissipation of modern SoCs. Additionally, the rapidly increasing complexity of modern SoCs further aggravates these issues, and makes it extremely difficult to guarantee that the design of these chips meet their specifications. Furthermore, the pervasiveness of electronic systems in modern societies, and their ubiquitous implication in all aspects of our everyday lives, drastically raises the requirements to protect modern electronic systems against all these threats, as well as versus those induced by intentional attacks against their security. These trends have made mandatory the development of efficient Design for Robustness approaches for mitigating these pluralities of threats. However, as DfX techniques are proliferating (Design for Test, Design for Debug, Design for Yield, Design for Reliability, Design for Low-Power, Design for Security, Design for Verification, …), it becomes mandatory to address these issues holistically, in order to moderate their impact on area, power, and/or performance, and increase their global efficiency. There is therefore a related need for an international consolidated forum bringing together specialists from all these domains to enhance interactions and cross-fertilization. The IEEE Federative Event on Design for Robustness (FEDfRo), sponsored by the IEEE Council on Electronic Design Automation (CEDA), was initiated on 2016 to meet this goal by bringing together: - IOLTS: International Symposium on On-Line Testing and Robust System Design http://tima.imag.fr/conferences/iolts/iolts17/ a well-established IEEE forum on Design for Quality, Design for Yield, Design for Reliability, and Low-Power design based on Design for Reliability approaches, mostly addressing digital systems; - IMSTW: the International Mixed-Signal Testing Workshop http://tima.imag.fr/conferences/imstw/imstw17/ a well-established IEEE forum addressing these techniques in the context of mixed-signal circuits;- - IVSW: the International Verification and Security Workshop http://tima.imag.fr/conferences/ivsw/ivsw17/ a new IEEE forum started on 2016 and addressing all Verification and Security issues associated with electronic systems. Starting from 2018, a fourth event, PATMOS, will also be part of FEDfRo. The above events are soliciting papers in their respective areas. Those events will be held in the same location and will run in parallel. To encourage interactions, anyone registered in one of the events can freely attend sessions of the other two events. All social activities will also be done jointly to increase interaction and cross fertilization among attendees.

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2nd International Verification and Security Workshop

IVSW
Venue: Makedonia Palace Hotel, Thessaloniki, GREECE
Date: July 3-5 2017

Summary: Issues related to verification and security are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in quality, reliability and security needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective verification techniques and security solutions. These needs have increased dramatically with the increased complexity of complex electronic systems and the fast adoption of these systems in all aspects of our daily lives. The goal of IVSW is to bring industry practitioners and researchers from the fields of verification, validation, test, reliability and security to exchange innovative ideas and to develop new methodologies for solving the difficult challenges facing us today in various SOC design environments. IVSW 2017 is sponsored by IEEE Council on Electronic Design Automation (CEDA).

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22nd International Mixed-Signal Testing Workshop

IMSTW
Venue: Hotel Makedonia Palace, Thessaloniki, GREECE
Date: July 3-5, 2017

Summary: As it happens with design automation, Analog and Mixed-Signal test solutions are much less generic than their siblings from the digital world. In spite of the high costs associated to specification-based test, the industry seemed reluctant to invest in alternatives. Why would we change something that worked? But with the rise of safety-critical applications, reliability requirements are increasing and quality is nowadays a strong asset in competitive markets. Specification-based test cannot be considered perfect any longer. The golden reference is shattered and this is an opportunity for the Analog and Mixed-Signal test community.

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Séminaires

Dr Joshua LEE, University of Hong Kong

Theme: Piezoelectric-on-Silicon Resonators for Frequency Control and Sensing
Date: 01/06/2017 - 14:00, Laboratoire TIMA - Salle T312

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Thèses soutenances

« Actuellement il n’y aucune soutenance prévue »

Distinctions


Dominique Borrione est membre d'honneur de la société informatique de France 2017

Project: Dominique Borrione

Professeur émérite à l’Université Grenoble Alpes, Dominique Borrione a été Professeur à l’Université de Provence, Marseille (Déc. 1983 – Août 1988) avant de muter à l’Université de Grenoble en 1988. Elle a assuré la direction des laboratoires IMAG-ARTEMIS (Jan. 1992-Déc 1995) et TIMA (janv 2007 à déc 2014) à Grenoble. Ses domaines d’expertise portent sur les langages de description et de simulation des systèmes matériels numériques, les méthodes formelles et semi-formelles pour la description, la spécification, la vérification, la synthèse de systèmes intégrés numériques.

URL : http://www.societe-informatique-de-france.fr/la-sif/membres_d_honneur/membres-honneur-2017/

Le 28 janvier 2017

 

Best Paper Award at the SNUG (Synopsys User Group) Conference

Project: Titre : Conclusive Formal Verification of Clock Domain Crossings using SpyGlass-CDC

Auteurs : Mejid Kebaili (STMicroelectronics) & Guillaume Plassan (Synopsys) (deux doctorants de TIMA/AMFORS en thèse CIFRE:
Guillaume Plassan: CIFRE avec Synopsys
Mejid Kebaili:CIFRE avec STMicroelectronics
Récompense : “Best Paper Award” from the Technical Committee

Abstract :
In modern designs, the correct propagation of data through clock domains is ensured by implementing specific synchronizer protocols.
Then, to guarantee the absence of metastability, data loss or incoherence, the functional correctness of each CDC (Clock Domain Crossing) must be verified by using formal techniques.
However, flat verification of large designs often leads to an inconclusive status (neither proved nor failed) with limited debug capabilities.
In order to ease the formal analysis, an enhanced solution, called the Reactive flow, has been developed in the context of ST / Synopsys collaboration.
It consists of automatically abstracting irrelevant parts of the design in order to provide at least a local cause for a fail.
Also, our flow generates potential missing constraints to setup the design and to guide the formal analysis.
This methodology has been performed on large CPU 64 bits Sub-Systems with positive results.

le 28/06/2016 au World Trade Center de Grenoble

 

Best Paper Award at NANOARCH 2016 symposium

Project: Titre : Multi-contex Non-volatile Content Adressable Momory using Magnetic Tunnel Junctions

Auteurs : E. Deng (TIMA, AMfoRS), L. Anghel (TIMA, AMfoRS), G. Prenat(TIMA, RMS), W. Zhao (TIMA, AMfoRS)

Récompense: 2016 Best Paper Award at the 12th IEEE/ACM International Symposium on Nanoscale Architectures, July 18-20, 2016, Beijing, China

18-20 Juillet 2016

 

Jobs

Embedded test instruments for high-performance Analog-to-Digital Converters in advanced nanometric technological nodes

Équipe : RMS

Date de début : April 2017

Durée : 1 year

Profil : The integration capabilities offered by current nanoscale CMOS technologies enable the fabrication of complete and very complex mixed-signal systems on a single die. However, manufacturing processes are prone to imperfections that may degrade the intended functionality of the fabricated circuits. Extensive production tests are needed in order to separate defective or unreliable parts from functionally correct devices. Unfortunately, the co-integration of blocks of very distinct nature (analog, mixed-signal, digital, RF, ...) as well as the limited access to internal nodes in an integrated system make the test of these devices a very challenging and costly task. Nowadays, testing the analog, mixed-signal, and radio-frequency (RF) functions of ICs results in a high cost that may amount up to 50% of the overall manufacturing cost. The test cost is expected to rise in the coming years as ICs include ever more functionality and as we move to smaller technology nodes for which process variations and defect density become more prevalent. Therefore, reducing the cost of testing for analog, mixed-signal, and RF circuits is an area of focus and innovation for the semiconductor industry.

This post-doc project envisages built-in test solutions for high-performance Analog-to-Digital converters (ADCs). Built-in test consists of migrating some of the test instruments into the IC, in order to facilitate and speed-up testing. For example, built-in test could consist of generating test stimuli on-chip, performing and processing measurements on-chip, etc. Built-in test can also help to diagnose the source of failure and, thereby, enhance production yield through appropriate actions. Furthermore, embedded test instruments may enable on-line test, self-healing, self-calibration and adaptive operation in safety-critical and mission-critical applications.

Specifically, this post-doc aims at the development of efficient built-in test instruments for static test of ADCs in a nanometric technology with the final goal of integrating a self-testable ADC demonstrator.

• See complete information to : Follow the link.

Personne à contacter : Manuel J?? Barragan, Salvador Mir