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21st International Mixed-Signal Testing Workshop

IMSTW
Venue: Sant Feliu de Guíxols, SPAIN
Date: July 4-6, 2016

Steering Committee : MIR S.
Program Committee : MIR S.
Program Co-chair : BARRAGAN M.
Publicity : MIR S.

Summary: The role of nano-electronic systems is rapidly expanding in every facet of modern life. To interact with environment and users the Integrated Circuits need analog, mixed-signal, RF or MEMS blocks. These blocks could represent a low part of the chip area but have a major impact on IC Yield and reliability. Indeed, one of the major bottlenecks nowadays for nano-electonics systems is the post-manufacturing testing of their analog, mixed-signal, RF, and MEMS functions, in order to guarantee outgoing quality while not sacrificing yield. Testing such functions is accounting for a large portion of the overall manufacturing cost. The main reasons include the pressing demand for zero defective parts-per-million, the increasing frequency of operation, the high levels of integration, the limited controllability and observability of embedded blocks, the integration of heterogeneous devices onto the same substrate, the requirement for specialized, high-cost equipment, the new defect mechanisms and excessive process variations occurring in advance technology nodes, the long test times, etc. In addition to the post-manufacturing testing problem, modern safety-critical, mission-critical, and remote-controlled systems need to be equipped with self-test, concurrent error detection, and fault-tolerance capabilities so as to detect early reliability hazards and guarantee reliable operation even in harsh environments. For such systems, diagnosing the sources of failures occurring in the field of operation is of vital importance, in order to apply corrective actions and to prevent failure reoccurrence. The International Mixed-Signal Testing Workshop (IMSTW) is one of the main forums that bring together analog, mixed-signal, RF, and MEMS the test community to discuss ideas and views on the above challenges.

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1st IEEE Federative Event on Design for Robustness (FEDfRo)

FEDfRo
Venue: Sant Feliu de Guixols, Catalunya, SPAIN
Date: July 4-6, 2016

Coordinators : NICOLAIDIS M.

Summary: Nanometer scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of efficient techniques for improving yield and reliability, extending lifespan, and reducing power dissipation of modern SoCs. Additionally, the rapidly increasing complexity of modern SoCs further aggravates these issues, and makes it extremely difficult to guarantee that the design of these chips meet their specifications. Furthermore, the pervasiveness of electronic systems in modern societies, and their ubiquitous implication in all aspects of our everyday lives, drastically raises the requirements to protect modern electronic systems against all these threats, as well as versus those induced by intentional attacks against their security. These trends have made mandatory the development of efficient Design for Robustness approaches for mitigating these pluralities of threats. However, as DfX techniques are proliferating (Design for Test, Design for Debug, Design for Yield, Design for Reliability, Design for Low-Power, Design for Security, Design for Verification, …), it becomes mandatory to address these issues holistically, in order to moderate their impact on area, power, and/or performance, and increase their global efficiency. There is therefore a related need for an international consolidated forum bringing together specialists from all these domains to enhance interactions and cross-fertilization. The IEEE Federative Event on Design for Robustness (FEDfRo) was initiated to meet this goal, and was established by bringing together: - IOLTS: the 22nd International On-Line Testing Symposium http://tima.imag.fr/conferences/iolts/iolts16/, a well-established IEEE forum on Design for Quality, Design for Yield, Design for Reliability, and Low-Power design based on Design for Reliability approaches, mostly addressing digital systems; - IMSTW: the 21st International Mixed-Signal Testing Workshop http://tima.imag.fr/conferences/imstw/imstw16/, a well-established IEEE forum addressing these techniques in the context of mixed-signal circuits; - IVSW: the 1st International Verification and Security Workshop http://tima.imag.fr/conferences/ivsw/ivsw16/, a new IEEE forum addressing all Verification and Security issues associated with electronic systems. The above events are soliciting papers in their respective areas. Those events will be held in the same location and will run in parallel. To encourage interactions, anyone registered in one of the events can freely attend sessions of the other two events. All social activities will also be done jointly to increase interaction and cross fertilization among attendees.

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1st IEEE International Verification and Security Workshop

IVSW
Venue: Sant Feliu de Guixols, SPAIN
Date: July 4-6, 2016

Steering Committee : NICOLAIDIS M.
Technical Program Committee : MAISTRI P., PIERRE L.
Local Organization : NICOLAIDIS M.

Summary: Issues related to verification and security are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in quality, reliability and security needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective verification techniques and security solutions. These needs have increased dramatically with the increased complexity of complex electronic systems and the fast adoption of these systems in all aspects of our daily lives. The purpose of this new workshop is to bring industry practitioners and researchers from the fields of verification, validation, test, reliability and security to exchange innovative ideas and to develop new methodologies for solving the difficult challenges facing us today in various SOC design environments. This new workshop will be held in Europe co-located in conjunction with two successful test related conferences (On-line Test Symposium and Mixed Signal Test Workshop) an ideal environment for cross- examination of test, verification, reliability and security experiences and innovative solutions. These three events are sponsored by the IEEE Council on Electronic Design Automation (CEDA). Registered attendees of any of the three events will be allowed to attend the technical sessions of the other two events. The plenary session and social activities of the three events will be done jointly.

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22nd IEEE International Symposium on On-Line Testing and Robust System Design

IOLTS
Venue: Sant Feliu de Guixols, Catalunya, SPAIN
Date: July 4-6, 2016

Audio / Visual : PAPAVRAMIDOU P.
Program Committee : ANGHEL L., BENABDENBI M., LEVEUGLE R., NICOLAIDIS M., PAPAVRAMIDOU P., SIMEU E., VELAZCO R., ZERGAINOH N. - E.
General Chair : NICOLAIDIS M.
Registration : SIMEU E., ZERGAINOH N. - E.
Finance Chair : ANGHEL L., VELAZCO R.
Secretary : FOURNERET-ITIÉ A.-L.

Summary: Issues related to On-line testing techniques, and more generally to design for robustness, are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective design for robustness techniques. These needs have increased dramatically with the introduction of nanometer technologies, which impact adversely noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of design for robustness techniques for extending, yield, reliability, and lifetime of modern SoCs. Design for reliability becomes also mandatory for reducing power dissipation, as voltage reduction, often used to reduce power, strongly affects reliability by reducing noise margins and thus the sensitivity to soft-errors and EMI, and by increasing circuit delays and thus the severity of timing faults. There is also a strong relation between Design for Reliability and Design for Security, as security attacks are often fault-based. The International Symposium on On-Line Testing and Robust System Design (IOLTS), is an established forum for presenting novel ideas and experimental data on these areas. The Symposium is sponsored by the IEEE Council on Electronic Design Automation (CEDA) and the 2016 edition is organized by the IEEE Computer Society Test Technology Technical Council, the University of Athens, and the TIMA Laboratory.

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Nanoelectronics, Applications, Design & Technology Conference

Venue: MINATEC, Grenoble, FRANCE
Date: 20-21 June 2016

Steering Committee : PETROT F.

Summary: The European Nanoelectronics Applications, Design & Technology Conference will focus on electronic components, electronic system design, design automation and manufacturing topics related to Micro- and Nano- Electronics, in themselves a very important success factor for European companies. Exhaustive research and development in this area has been supported by EUREKA, H2020 and local governments through the past five years. Latest results and exciting highlights from mainly CATRENE, PENTA, ECSEL/ENIAC, and H2020 projects will form the subjects of this conference.

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4th IEEE International Workshop on Test and Validation of High Speed Analog Circuits

TVHSAC
Venue: Disneyland Hotel, Anaheim, California, USA
Date: October 8-9, 2015

Program Chair : BARRAGAN M.

Summary: Today, we are in the internet-of-things (IoT) era - an era of sensors and components connected across a high speed communication infrastructure with analysis by massive data center “clouds”, the building blocks are systems-on-chip (SoC) integrated with several diverse IP modules. Analog and mixed-signal (AMS) circuits form many of the critical components of SoCs that push the boundaries of high bandwidth and low power. AMS circuits, such as phase-locked loops, sensors, amplifiers, wired and wireless interfaces are often embedded in a chip with limited controllability to access them. The demand for high performance, high bandwidth and low power has resulted in AMS designs operating at their margins. The unimaginable levels of integration has come at the cost of increased manufacturing process variations, vulnerability to defects, and accelerated device aging. In this scenario, verifying and validating AMS circuits, which are particularly sensitive to variations and electrical noise, in both pre-silicon and post-silicon phases, has become a great challenge. Effective diagnosis to improve AMS yield, and manufacturing test methods to detect catastrophic faults and unexpected process excursions that have contributed to increased AMS-related customer returns are a necessity. Further, sensitive AMS circuits such as those used in health and automotive products need to have a high degree of in-field reliability requiring fault tolerance and adaptive operation. Since most AMS circuits are often the gateways to a SoC, ensuring their secure design is of vital importance to prevent compromising the security of the chip. These quality objectives should be met under market requirements of aggressively low product cost and product cycle time.

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IFIP/IEEE International Conference on Very Large Scale Integration

VLSI-SoC
Venue: Daejeon Convention Center, Daejeon, KOREA
Date: October 5-7, 2015

Steering Committee Chair : MIR S.
Working Group Chair : BORRIONE D.

Summary: VLSI-SoC 2015 is the 23rd in a series of international conferences sponsored by IFIP TC 10 Working Group 10.5, IEEE CEDA and IEEE CASS, which explores the state-of-the-art in the areas that surround Very Large Scale Integration (VLSI) and System-on-Chip (SoC). Previous conferences have taken place in Edinburgh, Trondheim, Tokyo, Vancouver, Munich, Grenoble, Gramado, Lisbon, Montpellier, Darmstadt, Perth, Nice, Atlanta, Rhodes, Florianópolis, Madrid, Hong Kong, Santa Cruz, Istanbul, and Playa del Carmen. The purpose of VLSI-SoC is to provide a forum to exchange ideas and showcase research as well industrial results in EDA, design methodology, test, design, verification, devices, process, systems issues and application domains of VLSI and SoC.

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21st IEEE International On-Line Testing Symposium

IOLTS
Venue: Elia, Halkidiki, GREECE
Date: July 6-8, 2015

Audio / Visual : PAPAVRAMIDOU P.
Program Committee : ANGHEL L., BENABDENBI M., LEVEUGLE R., SIMEU E., STRATIGOPOULOS H., VELAZCO R., ZERGAINOH N. - E.
General Chair : NICOLAIDIS M.
Special Session Chair : STRATIGOPOULOS H.

Summary: Issues related to on-line testing are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective on-line testing techniques. These needs have increased dramatically with the introduction of very deep submicron and nanometer technologies which adversely impact noise margins, process, voltage and temperature variations, aging and wear-out and make integrating on-line testing and fault tolerance mandatory in many modern ICs. The International On-Line Testing Symposium (IOLTS) is an established forum for presenting novel ideas and experimental data on these areas. The symposium also emphasizes on-line testing in the continuous operation of large applications such as wired, cellular and satellite telecommunication, as well as in secure chips. The Symposium is sponsored by the IEEE Council on Electronic Design Automation (CEDA) and the 2015 edition is organized by the IEEE Computer Society Test Technology Technical Council, the University of Athens, and the TIMA Laboratory.

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20th International Mixed-Signal Testing Workshop

IMSTW
Venue: Université Pierre et Marie Curie, Paris, FRANCE
Date: 24-26 June 2015

Steering Committee : MIR S.
Program Committee : BARRAGAN M.
Local Committee : SIMEU E.
General Chair : STRATIGOPOULOS H.
Finance Chair : FOURNERET-ITIÉ A.-L.

Summary: The role of nano-electronic systems is expanding in every facet of modern life. One of the major bottlenecks nowadays for such systems is the high cost of post-manufacturing testing of their analog and mixed-signal functions, in order to guarantee outgoing quality while not sacrificing yield. In addition, safety-critical and mission-critical systems need to be equipped with self-test and fault-tolerance capabilities so as to guarantee reliable operation even in harsh environments. For such systems, diagnosing the sources of failures occurring in the field of operation is of vital importance, in order to apply corrective actions and to prevent failure reoccurrence. Diagnosis is also of vital importance to quickly identify failures in the first prototypes and to shed light on the manufacturing failure mechanisms. The International Mixed-Signals Testing Workshop is one of the main forums that bring together the test community to discuss ideas and views on the above challenges.

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