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23rd IEEE International Symposium on On-Line Testing and Robust System Design

IOLTS
Venue: Hotel Makedonia Palace, Thessaloniki, GREECE
Date: July 3-5, 2017

Finance Chair : ANGHEL L., VELAZCO R.
General Chair : NICOLAIDIS M.
Publication Chair : PAPAVRAMIDOU P.
Registration : SIMEU E., ZERGAINOH N. - E.
Secretary : ITIE Anne-Laure

Summary: Issues related to On-line testing techniques, and more generally to design for robustness, are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective design for robustness techniques. These needs have increased dramatically with the introduction of nanometer technologies, which impact adversely noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of design for robustness techniques for extending, yield, reliability, and lifetime of modern SoCs. Design for reliability becomes also mandatory for reducing power dissipation, as voltage reduction, often used to reduce power, strongly affects reliability by reducing noise margins and thus the sensitivity to soft-errors and EMI, and by increasing circuit delays and thus the severity of timing faults. There is also a strong relation between Design for Reliability and Design for Security, as security attacks are often fault-based.

The International Symposium on On-Line Testing and Robust System Design (IOLTS), is an established forum for presenting novel ideas and experimental data on these areas. The Symposium is sponsored by the IEEE Council on Electronic Design Automation (CEDA) and the 2017 edition is organized by the IEEE Computer Society Test Technology Technical Council, the University of Athens, and the TIMA Laboratory.

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2nd IEEE Federative Event on Design for Robustness

FEDfRo
Venue: Hotel Macedonia Palace, Thessaloniki, GREECE
Date: July 3-5, 2017

Coordinators : NICOLAIDIS M.

Summary: Nanometer scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of efficient techniques for improving yield and reliability, extending lifespan, and reducing power dissipation of modern SoCs. Additionally, the rapidly increasing complexity of modern SoCs further aggravates these issues, and makes it extremely difficult to guarantee that the design of these chips meet their specifications.

Furthermore, the pervasiveness of electronic systems in modern societies, and their ubiquitous implication in all aspects of our everyday lives, drastically raises the requirements to protect modern electronic systems against all these threats, as well as versus those induced by intentional attacks against their security.

These trends have made mandatory the development of efficient Design for Robustness approaches for mitigating these pluralities of threats. However, as DfX techniques are proliferating (Design for Test, Design for Debug, Design for Yield, Design for Reliability, Design for Low-Power, Design for Security, Design for Verification, …), it becomes mandatory to address these issues holistically, in order to moderate their impact on area, power, and/or performance, and increase their global efficiency. There is therefore a related need for an international consolidated forum bringing together specialists from all these domains to enhance interactions and cross-fertilization. The IEEE Federative Event on Design for Robustness (FEDfRo), sponsored by the IEEE Council on Electronic Design Automation (CEDA), was initiated on 2016 to meet this goal by bringing together:

- IOLTS: International Symposium on On-Line Testing and Robust System Design
http://tima.imag.fr/conferences/iolts/iolts17/
a well-established IEEE forum on Design for Quality, Design for Yield, Design for Reliability, and Low-Power design based on Design for Reliability approaches, mostly addressing digital systems;

- IMSTW: the International Mixed-Signal Testing Workshop
http://tima.imag.fr/conferences/imstw/imstw17/
a well-established IEEE forum addressing these techniques in the context of mixed-signal circuits;-
- IVSW: the International Verification and Security Workshop
http://tima.imag.fr/conferences/ivsw/ivsw17/
a new IEEE forum started on 2016 and addressing all Verification and Security issues associated with electronic systems.
Starting from 2018, a fourth event, PATMOS, will also be part of FEDfRo.

The above events are soliciting papers in their respective areas. Those events will be held in the same location and will run in parallel. To encourage interactions, anyone registered in one of the events can freely attend sessions of the other two events. All social activities will also be done jointly to increase interaction and cross fertilization among attendees.

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2nd International Verification and Security Workshop

IVSW
Venue: Makedonia Palace Hotel, Thessaloniki, GREECE
Date: July 3-5 2017

Local Organization : NICOLAIDIS M.
Steering Committee : NICOLAIDIS M.
Technical Program Committee : MAISTRI P., PIERRE L.

Summary: Issues related to verification and security are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in quality, reliability and security needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective verification techniques and security solutions. These needs have increased dramatically with the increased complexity of complex electronic systems and the fast adoption of these systems in all aspects of our daily lives. The goal of IVSW is to bring industry practitioners and researchers from the fields of verification, validation, test, reliability and security to exchange innovative ideas and to develop new methodologies for solving the difficult challenges facing us today in various SOC design environments. IVSW 2017 is sponsored by IEEE Council on Electronic Design Automation (CEDA).

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22nd International Mixed-Signal Testing Workshop

IMSTW
Venue: Hotel Makedonia Palace, Thessaloniki, GREECE
Date: July 3-5, 2017

Finance Chair : SIMEU E.
Program Co-chair : BARRAGAN M.
Program Committee : MIR S.
Steering Committee : MIR S.

Summary: As it happens with design automation, Analog and Mixed-Signal test solutions are much less generic than their siblings from the digital world. In spite of the high costs associated to specification-based test, the industry seemed reluctant to invest in alternatives. Why would we change something that worked? But with the rise of safety-critical applications, reliability requirements are increasing and quality is nowadays a strong asset in competitive markets. Specification-based test cannot be considered perfect any longer. The golden reference is shattered and this is an opportunity for the Analog and Mixed-Signal test community.

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