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(1) Darwish A., Sicard G., Fesquet L., 1-level Crossing Sampling Scheme for Low Data Rate Image Sensors, 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), 2014
 
(2) Fesquet L., Qaisar S.-M., Renaudin M., Adaptive rate filtering a computationally efficient signal processing approach, Signal Processing Journal , 94, page: 620-630 , 2014
 
(3) Faix M., Mazer E., Fesquet L., An asynchronous CMOS probabilistic computer Idea, 20th International Symposium on Asynchronous Circuits and Systems (ASYNC), Fresh Idea Session, Postdam, Germany, 2014
 
(4) Bonnaud O., Fesquet L., A Prospective on Education of New Generations of devices in the FDSOI and FinFET Technologies: from the technological process to the Circuit Design Specifications, 29th Symposium on Microeletronics Technology and Devices (SBMicro'14), 2014
 
(5) Zakaria H., Durand S., Marchand N., Fesquet L., A Robust and Energy-Efficient DVFS Control Algorithm for GALS-ANoC MPSoC in Advanced Technology under Process Variability Constraints , Advances in Computer Science : an International Journal, 3, page: 97-105, 2014
 
(6) Sicard G., Capteurs CMOS à Photosites standard, FR2014/051307, 2014
 
(7) Dutertre J.M., Possamai Bastos R., Torres F.S., Comparison of Bulk Built-In Current Sensors in terms of Transient-Fault Detection Sensitivity, European Workshop on CMOS Variability (VARI'14), 2014
 
(8) Fesquet L., Roa G., Le Pelleter T., Bonvilain A., Chagoya A., Designing ultra-low power systems with non-uniform sampling and event-driven logic, 27th Symposium on Integrated Circuits and Systems Design (SBCCI'14), 2014
 
(9) Dutertre J.M., Potin O., Flottes M.-L., Rouzeyre B., Di Natale G., Possamai Bastos R., Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts, Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'14), 2014
 
(10) Chefi A., Design of Low Power CMOS Image Sensor for Wireless Sensor Networks, These de Doctorat, 2014
 
(11) Al Khatib C., Chagoya A., Chevalier C., Sicard G., Fesquet L., Aupetit C., Distributed Asynchronous Controllers for Clock Management in Low Power Systems, 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), 2014
 
(12) Tayeb M.-B, Fesquet L., Nouet P., Bonnaud O., FINMINA: a French national project to promote Innovation in Higher Education in Microelectronics and Nanotechnologies, International Conference on Information Technology Based Higher Education and Training (ITHET'14), 2014
 
(13) Soudani A., Sicard G., Chefi A., Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs, AEU - International Journal of Electronics and Communications, 68, March, page: 193-200, 2014
 
(14) Bsiesy Ah., Fesquet L., Salaün A-C, Bonnaud O., Improvement of doctoral studies in Electrical and Information Engineering through the High level courses in Europe, 25th EAEEIE Annual Conference, 2014
 
(15) Di Natale G., Sarafianos A., Possamai Bastos R., Potin O., Dutertre J.M., Flottes M.-L., Rouzeyre B., Improving the ability of Bulk Built-In Current Sensors to detect SEEs by using triple-well CMOS, Microelectronics Reliability, 54, page: 2289–2294, 2014
 
(16) Abbas H., Local adaptive control in a sensor CMOS vision, These de Doctorat, 2014
 
(17) Sicard G., Fesquet L., Darwish A., Low data rate architecture for smart image sensor , Image Sensors and Imaging Systems, San Francisco, California, USA, 2014
 
(18) Bidegaray-Fesquet B., Darwish A., Le Pelleter T., Fesquet L., Beyrouthy T., Mitigating the data-deluge by an adequate sampling for low-power systems, 5th International Conference on Computational Harmonic Analysis, Vanderbilt University, Nashville, USA, 2014
 
(19) Cherkaoui A., Ring oscillator based true random number generators , These de Doctorat, 2014
 
(20) Fesquet L., Cherkaoui A., Elissati O., Self-timed rings as low-phase noise programmable oscillators, 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), 2014
 
(21) Chefi A., Abbas H., Amhaz H., Sicard G., Simple intra-pixel interaction for smart CMOS image sensors, 14th International Workshop on the Cellular Nanoscale Networks and their Applications (CNNA'14), 2014
 
(22) Sicard G., Chefi A., SPIHT-based image compression scheme for energy conservation over Wireless Vision Sensor Networks, 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), 2014
 
(23) Bonnaud O., Fesquet L., Trends in Nanoelectronic Education: From FDSOI and FinFET Technologies to Circuit Design Specifications, The 10th European Workshop on Microelectronics Education (EWME 2014), Tallinn, Estonia, 2014
 
(24) Di Natale G., Flottes M.-L., Dutertre J.M., Torres F.S., Possamai Bastos R., Rouzeyre B., A Bulk Built-in Sensor for Detection of Fault Attacks, International Symposium on Hardware Oriented Security and Trust (HOST'13), Austin, TX, USA, 2013
 
(25) Amhaz H., Sicard G., Abbas H., Rolland R., Zimouche H., A CMOS HDR Imager with an Analog Local Adaptation, International Image Sensor Workshop (IISW’13), Snowbird, USA, 2013
 
(26) Chefi A., Sicard G., Soudani A., A CMOS Image Sensor with Low-Complexity Video Compression for Wireless Sensor Networks, International New Circuits and Systems Conference (NEWCAS’13), Paris, France, 2013
 
(27) Beyrouthy T., Fesquet L., An asynchronous FPGA block with its tech-mapping algorithm dedicated to security applications, International Journal of Reconfigurable Computing, 2013, Article ID 517947, page: 12 pages, 2013
 
(28) Rouzeyre B., Flottes M.-L., Lu F., Possamai Bastos R., Di Natale G., A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic, JETTA : Journal of Electronic Testing - Theory and Applications, 29, page: 331-340, 2013
 
(29) Cherkaoui A., Fesquet L., Fischer V., Aubert A., A Self-timed Ring Based True Random Number Generator, 19th International Symposium on Asynchronous Circuits and Systems (ASYNC'13), Santa Monica, USA, 2013
 
(30) Torres F.S., Possamai Bastos R., Flottes M.-L., Di Natale G., Rouzeyre B., Dutertre J.M., A Single Built-in Sensor to Check Pull-up and Pull-down CMOS Networks against Transient Faults, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'13), Karlsruhe, Germany, 2013
 
(31) Cherkaoui A., Aubert A., Fischer V., Fesquet L., A Very High Speed True Random Number Generator with Entropy Assessment, Workshop on Cryptographic Hardware and Embedded Systems (CHES'2013), Santa Barbara, California, USA, 2013
 
(32) Sicard G., Soudani A., Chefi A., Contribution to the design of a CMOS Image Sensor with Low-Complexity Video Compression for Wireless Sensor Networks, Journal of Systems Architecture (JSA), 59, page: 818-825, 2013
 
(33) Torres F.S., Possamai Bastos R., Detection of Transient Faults in Nanometer Technologies by using Modular Built-In Current Sensors, Journal of Integrated Circuits and Systems, 8, page: 89-97, 2013
 
(34) Sliwinski P., Fesquet L., Sicard G., Wachel P., Berezowski K., Empirical recovery of input nonlinearity in distributed element models, International Workshop on Adaptation and Learning in Control and Signal Processing (ALCOSP'13), Caen, France, 2013
 
(35) Fesquet L., Bonnaud O., Innovating projects as a pedagogical strategy for the French network for education in microelectronics and nanotechnologies, International Conference on Microelectronic Systems Education (MSE 2013), Austin, Texas, USA, 2013
 
(36) Beyrouthy T., Fesquet L., Rolland R., Bonvilain A., Leroy Y., Le Pelleter T., Low-power signal processing platform based on non-uniform sampling and event-driven circuitry, Design, Automation and Test in Europe (DATE'13), Grenoble, France, 2013
 
(37) Bonvilain A., Beyrouthy T., Le Pelleter T., Fesquet L., Rolland B., Non-uniform sampling pattern recognition based on atomic decomposition, International Conference on Sampling Theory and Applications (SampTA'13), Bremen, Germany, 2013
 
(38) Alleysson D., Abbas H., Amhaz H., Sicard G., Novel Auto-Adaptative Integration-Time Technique for CMOS Image Sensor, International Image Sensor Workshop (IISW’13), Snowbird, USA, 2013
 
(39) Abbas H., Alleysson D., Amhaz H., Sicard G., Novel Mixed Design of Tone Mapping Technique for HDR CMOS Image Sensor, International Conference on Microelectronics (ICM’13), Beirut, Lebanon, 2013
 
(40) Flottes M.-L., Dutertre J.M., Possamai Bastos R., Potin O., Di Natale G., Rouzeyre B., Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'13), Arcachon, France, 2013
 
(41) Di Natale G., Flottes M.-L., Potin O., Dutertre J.M., Possamai Bastos R., Rouzeyre B., Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection, Microelectronics Reliability, 53, Issues 9–11, September–November , page: 1320–1324, 2013
 
(42) Souza Alexandre K. P. , Sicard G., de Lima Monteiro Davies W. , de Moraes Cruz Carlos A. , Simple Technique to Reduce FPN in a linear-logarithm APS, International Image Sensor Workshop (IISW’13), Snowbird, USA, 2013
 
(43) Sicard G., Rohr P., Dupont B., Arques M., Habib A., Verger L., Tchagaspanian M., Sphinx1: Spectrometric Photon Counting and Integration Pixel for X-Ray Imaging with a 100 Electrons LSB, Medical Imaging Conference (MIC’13), Seoul, Korea, 2013
 
(44) Fesquet L., Yahya E., Renaudin M., Ismail Y., Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation, 19th International Symposium on Asynchronous Circuits and Systems (ASYNC'13), Santa Monica, USA, 2013
 
(45) Fesquet L., Bonnaud O., The new strategy based on Innovative Projects in Microelectronics and Nanotechnologies, Symposium on Microelectronics Technology and Devices (SBMicro'13), Curitiba, Brazil, 2013
 
(46) Zecri M., Villard P., Thabuis T., Sicard G., Decaens G., Belleville M., Adaptive Gain and Analog Wavelet Transform for Low-Power Infrared Image Sensors, Active and Passive Electronic Components Journal (APEC), 2012, Article ID 610176, page: 1-6 , 2012
 
(47) Aubert A., Fesquet L., Cherkaoui A., Fischer V., A New Robust True Random Numbers Generator Using Self-Timed Rings, Workshop on Cryptographic architectures embedded in reconfigurable devices (Cryptarchi'12), Chateau de Goutelas, Marcoux, France, 2012
 
(48) Renaudin M., Fesquet L., Yahya E., Asynchronous circuit performance analysis, fundamentals and efficient tools, Tutorial in 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'12), Copenhagen, Denmark, 2012
 
(49) Porcher A., Asynchronous monitors synthesis from temporal assertions for the robust observation of synchronous circuits, These de Doctorat, 2012
 
(50) Fischer V., Cherkaoui A., Aubert A., Fesquet L., Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs, Design Automation and Test in Europe (DATE'12), Dresden, Germany, 2012
 
(51) Fesquet L., Controling variability and energy by design, CMOS Emerging Technologies, Vancouver, BC, Canada, 2012
 
(52) Fesquet L., Hamon J., Générateurs de nombres aléatoires vrais, FR 12 51079 , 2012
 
(53) Sicard G., Chefi A., Soudani A., Hardware compression scheme based on low-complexity arithmetic encoding for low power image transmission over WSNs, 1st Workshop on Architecture of Smart Camera (WASC'12), Clermont-Ferrand, France, 2012
 
(54) Sicard G., Alleysson D., Amhaz H., Abbas H., In Pixel Implementation of autoadaptative integration time, 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS’12), Seville, Spain, 2012
 
(55) Amhaz H., Low level image processing integrated in CMOS vision sensor, These de Doctorat, 2012
 
(56) Fesquet L., Bonvilain A., Le Pelleter T., Méthode à faible coût de calcul et robuste pour la détection d’un motif dans un signal, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'12), Marseille, France, 2012
 
(57) Paugnat F., Method for the Modelling and the Refinement of the Heterogeneous Systems, These de Doctorat, 2012
 
(58) Morin-Allory K., Paugnat F., Fesquet L., Model of a Simple yet effective Operational Amplifier, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), Seville, Spain, 2012
 
(59) Bonnaud O., Fesquet L., Papillon F., Excoffon E., Bsiesy Ah., New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school , International Conference on Information Technology Based Higher Education and Training (ITHET'12), Istanbul, Turkey, 2012
 
(60) Sicard G., Amhaz H., New smart readout technique performing edge detection designed to control vision sensors dataflow, 24th IS&T/SPIE Electronic Imaging Conference, Burlingame, California, USA, 2012
 
(61) Di Natale G., Flottes M.-L., Rouzeyre B., Possamai Bastos R., Torres F.S., Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode, Microelectronics Reliability, 52, page: 1781–1786, 2012
 
(62) Possamai Bastos R., Torres F.S., Di Natale G., Flottes M.-L., Rouzeyre B., Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode, 23rd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'12), Cagliari, Italy, 2012
 
(63) Torres F.S., Possamai Bastos R., Robust modular Bulk Built-in Current Sensors for detection of transient faults, 25th Symposium on Integrated Circuits and Systems Design (SBCCI'12), Brasilia, 2012
 
(64) Elissati O., Yahya E., Fesquet L., Rieubon S., Self-Timed Rings: A Promising Solution for Generating High-Speed High Resolution Low-Phase Noise Clocks, VLSI-SoC: Forward-Looking Trends in IC and Systems Design 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers, Springer , 22-42, 2012
 
(65) Cherkaoui A., Aubert A., Fischer V., Fesquet L., Self-Timed Rings as Entropy Sources, 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'12), Copenhagen, Denmark, 2012
 
(66) Fischer V., Cherkaoui A., Aubert A., Fesquet L., Self-Timed Rings as Sources of Entropy, 6ème colloque du GDR SOC-SIP du CNRS, Paris, France, 2012
 
(67) Fesquet L., Signal Processing for AsynchronouS Systems (SPASS), IDDN.FR.001.080019.000.S.P.2012.000.31235, 2012
 
(68) Sicard G., Renaudin M., Firmin F., Clerc S., Abouzeid F., 40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications, Transactions on Design Automation of Electronic Systems (TODAES), 16, page: article 35, 2011
 
(69) Fesquet L., Sicard G., Alsayeg K., Renaudin M., A modular synthesis method for low-power QDI state machines , 9th IEEE International NEWCAS Conference, Bordeaux, France, 2011
 
(70) Paugnat F., Bousquet L., Fesquet L., Analog Design Abstraction Levels and SystemC AMS Models of Computation, SystemC-AMS Day 2011: Industry Adoption of the SystemC AMS Standard, Dresden, Germany, 2011
 
(71) Robin R., Beyrouthy T., Fesquet L., Greitans M., Shavelis R., An Asynchronous FIR Filter Architecture coupled to a Level-Crossing ADC, 9th International Conference on Sampling Theory and Applications (SampTA), Singapore, 2011
 
(72) Beyrouthy T., Fesquet L., An event-driven FIR filter: Design and implementation , 22nd IEEE International Symposium on Rapid System Prototyping (RSP'11), Karlsruhe, Germany, 2011
 
(73) Zimouche H., Abbas H., Amhaz H., Sicard G., An improved smart readout technique based on temporal redundancies suppression designed for logarithmic CMOS image sensor, 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS’11), Beirut, Lebanon, 2011
 
(74) Fesquet L., Paugnat F., Bousquet L., Morin-Allory K., A Performance Comparison Between the SystemC-AMS Models of Computation, edaWorkshop 2011, Dresden, Germany, 2011
 
(75) Morin-Allory K., Paugnat F., Fesquet L., A refinement process for top-down mixed-signal designs thanks to SystemC-AMS , IEEE 9th International New Circuits and Systems Conference (NEWCAS'11), Bordeaux, France, 2011
 
(76) Zakaria H., Asynchronous Architecture for Power Efficiency and Yield Enhancement in the Decananometric Technologies: Application to a Multi-Core System-on-Chip, These de Doctorat, 2011
 
(77) Fesquet L., Ouchet F., Morin-Allory K., C-elements for hardened self-timed circuits, 21st International Workshop Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), Madrid, Spain, 2011
 
(78) Zimouche H., CMOS image sensors insensitive to temperature variations, These de Doctorat, 2011
 
(79) Fesquet L., Greitans M., Beyrouthy T., Shavelis R., Combined Peak and Level-Crossing Sampling Scheme, 9th International Conference on Sampling Theory and Applications (SampTA), Singapore, 2011
 
(80) Hamon J., Fesquet L., Configurable Self-Timed Ring Oscillators, 9th IEEE International NEWCAS Conference, Bordeaux, France, 2011
 
(81) Sicard G., Contrôle Contraste Local, 1158472, 2011
 
(82) Zakaria H., Fesquet L., Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs , IEEE Journal on Emerging and Selected Topics in Circuits and Systems , 1, page: 160 - 172 , 2011
 
(83) Morin-Allory K., Fesquet L., Porcher A., Does Asynchronous technology bring robustness in synchronous circuit monitoring?, Forum on specification & Design Languages (FDL’11), Oldenburg, Germany, 2011
 
(84) Fesquet L., Morin-Allory K., Yan C., Ouchet F., Formal Verification of C-element Circuits, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’11), Ithaca (NY), 2011
 
(85) Chefi A., Soudani A., Sicard G., Hardware compression solution based on HWT for low power image transmission in WSN, 23rd IEEE International Conference on Microelectronics (ICM'11), Hammamet, Tunisia, 2011
 
(86) Ayala J.L., García-Cámara B., Prieto M., Ruggiero M., Sicard G., Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings, Springer , 350 p., 2011
 
(87) Bidegaray-Fesquet B., Fesquet L., Non-Uniform Filter Design in the Log-Scale, 9th International Conference on Sampling Theory and Applications (SampTA), Singapore, 2011
 
(88) Bidegaray-Fesquet B., Fesquet L., Non-uniform Filter interpolation in the frequency domain, An International Journal on Sampling Theory in Signal and Image Processing (STSIP), 10, page: 17-35, 2011
 
(89) Fesquet L., Zakaria H., Process variability robust energy-efficient control for nano-scaled complex SoCs , 10th Edition of Faible Tension Faible Consommation (FTFC’11), Marrakech, Morocco, 2011
 
(90) Fesquet L., Elissati O., Rieubon S., Ring Oscillators : The Asynchronous Alternative, 10th Edition of Faible Tension Faible Consommation (FTFC’11), Marrakech, Morocco, 2011
 
(91) Ouchet F., Robustness analysis and improvement of QDI self-timed circuits, These de Doctorat, 2011
 
(92) Fesquet L., Torresani B., Sampling Theory in Signal and Image Processing, Sampling Publishing ISSN: 1530-6429, Vol. 10, N°1-2, 2011
 
(93) Zakaria H., Fesquet L., Yahya E., Self Adaption in SoCs, Autonomic Networking-on-Chip (Bio-inspired Specification, Development, and Verification), CRC Press, 287p, 2011
 
(94) Elissati O., Self-Timed Ring Oscillators : from theory to practice, These de Doctorat, 2011
 
(95) Amhaz H., Zimouche H., Sicard G., Smart Readout Technique based on Temporal Redundancies Suppression Designed for Logarithmic CMOS Image Sensor, International Image Sensor Workshop (IISW’11), Hokkaido, Japan, 2011
 
(96) Sicard G., Amhaz H., Zimouche H., Smart readout technique designed for logarithmic CMOS image sensor including a motion detection scheme, 9th IEEE International Conference on New Circuits and Systems (NEWCAS’11), Bordeaux, France, 2011
 
(97) Porcher A., Fesquet L., Morin-Allory K., Synthesis of Quasi Delay Insensitive Monitors, 7th Conference on PhD Research in Microelectronics and Electronics (PRIME’11), Madonna Di Campiglio (Trento), Italy, 2011
 
(98) Zimouche H., Sicard G., Amhaz H., Temperature compensated logarithmic CMOS image sensor using CMOS voltage reference Bandgap method , 9th IEEE International Conference on New Circuits and Systems (NEWCAS’11), Bordeaux, France, 2011
 
(99) Zimouche H., Amhaz H., Temperature Compensation Scheme for Logarithmic CMOS Image Sensor, International Image Sensor Workshop (IISW’11), Hokkaido, Japan, 2011
 
(100) Fesquet L., Thinking and Designing Differently: The Asynchronous Alternative, Dresden Microelectronic Academy, Dresden, Germany, 2011
 
(101) Fesquet L., Leblond N., Porcher A., Tiempo Asynchronous Design Flow Tutorial - Modeling and Debug, Design Automation Conference (DAC’11), San Diego, USA, 2011
 
(102) Heinrich V., Sicard G., Roche P., Crippa D., Veggetti A., Jain A., Abouzeid F., Clerc S., A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder, IEEE International Conference on Integrated Circuit Design and Technology (ICICDT’10), Grenoble, France, 2010
 
(103) Sicard G., Amhaz H., A high output voltage swing logarithmic image sensor designed with on chip FPN reduction, 6th IEEE Conference on Ph.D. Research in Microelectronics & Electronics (PRIME'10), Berlin, Germany, 2010
 
(104) Elissati O., Fesquet L., Rieubon S., Yahya E., A High-Speed High-Resolution Low-Phase Noise Oscillator Using Self-Timed Rings, 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'10), Madrid, Spain, 2010
 
(105) Rieubon S., Elissati O., Yahya E., Fesquet L., A novel High-Speed Multi-Phase Oscillator on Asynchronous Rings, IEEE International Conference on Microelectronics ICM’2010, Cairo, Egypte, 2010
 
(106) Labonne E., Rolland R., Sicard G., A Standard 3.5T CMOS Imager Including a Light Adaptive System for Integration Time Optimization , Algorithm-Architecture Matching for Signal and Image Processing , Springer , 81-93, 2010
 
(107) Sicard G., Reis R., Kastensmidt F., Possamai Bastos R., Renaudin M., Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies , 15th IEEE European Test Symposium (ETS’10), Prague, Czecoslovaquia, 2010
 
(108) Possamai Bastos R., Sicard G., Kastensmidt F., Reis R., Renaudin M., Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies , 21st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Monte Cassino Abbey and Gaeta, Italy, 2010
 
(109) Reis R., Kastensmidt F., Renaudin M., Possamai Bastos R., Sicard G., Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies , Microelectronics and Reliability, 50, page: 1241-1246, 2010
 
(110) Morin-Allory K., Fesquet L., Ouchet F., Delay Insensitivity Does Not Mean Slope Insensitivity!, IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), Grenoble, France, 2010
 
(111) Sicard G., Kastensmidt F., Renaudin M., Reis R., Possamai Bastos R., Evaluating transient-fault effects on traditional C-element's implementations, 16th IEEE International On-Line Testing Symposium, (IOLTS’10), Corfu island, Greece, 2010
 
(112) Bidegaray-Fesquet B., Fesquet L., IIR digital filtering of non-uniformly sampled signals via state representation, International Journal of Signal Processing, 90, page: 2811-2821, 2010
 
(113) Rolland R., Hamon J., Fristot V., Implementation of a real time multi-resolution edge detection video filter, 8th European Workshop on Microelectronics Education (EWME’10), Darmstadt, Germany, 2010
 
(114) Marchand N., Durand S., Zakaria H., Fesquet L., Integrated Asynchronous Regulation for Nanometric Technologies, 1st IEEE European workshop on CMOS Variability (VARI'10), Montpellier, France, 2010
 
(115) Zimouche H., Sicard G., Integrated temperature compensation scheme for a standard linear CMOS vision sensor, 6th IEEE Conference on Ph.D. Research in Microelectronics & Electronics (PRIME 2010), Berlin, Germany, 2010
 
(116) Yahya E., Rieubon S., Fesquet L., Elissati O., Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Springer , 137–149, 2010
 
(117) Rieubon S., Elissati O., Fesquet L., Yahya E., Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case , International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2010), Grenoble, France, 2010
 
(118) Zimouche H., Sicard G., Standard Linear CMOS Image Sensor Insensitive to Temperature Variations, The 8th IEEE International NEWCAS 2010 Conference, Montreal, Canada, 2010
 
(119) Barbut L., Serbutoviez C., Coppard R., Chartier I., Gwoziecki R., Sicard G., Frere P., Tallal J., Heitzman M., Bablet J., Bory C., Jacob S., Seiler A.-L., Benwadih M., Verilhac J.-M., Step toward robust and reliable amorphous polymer field-effect transistors and logic functions made by the use of roll to roll compatible printing processes , Organic Electronics, 11, page: 456-462 , 2010
 
(120) Abouzeid F., Subthreshold architecture and digital circuits study in submicronic CMOS technology , These de Doctorat, 2010
 
(121) Morin-Allory K., Fesquet L., Porcher A., Synthesis of asynchronous monitors for critical electronic systems, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’10), Vienna, Austria, 2010
 
(122) Alsayeg K., Synthesis of low power QDI sequential controllers proved correct, These de Doctorat, 2010
 
(123) Fesquet L., Sicard G., Bidegaray-Fesquet B., Targeting ultra-low power consumption with non-uniform sampling and filtering, IEEE International Symposium on Circuits and Systems (ISCAS’10), Paris, France, 2010
 
(124) Zimouche H., Sicard G., Temperature Compensation Method for Logarithmic CMOS Vision Sensor Using CMOS Voltage Reference Bandgap Technique, 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2010), Athens, Greece, 2010
 
(125) Possamai Bastos R., Transient-Fault Robust Systems Exploiting Quasi-Delay Insensitive Asynchronous Circuits, These de Doctorat, 2010
 
(126) Amhaz H., Sicard G., X-axis Spatial Redundancy Supression : Contribution to the Integration of Smart Reading Techniques in a Standard CMOS Vision Sensor , 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS'10), Athens, Greece, 2010
 
(127) Clerc S., Abouzeid F., Sicard G., Renaudin M., Firmin F., A 45nm CMOS 0.35V-Optimized Standard Cell Library for Ultra-Low Power Applications , International Symposium on Low Power Electronics and Design (ISLPED’09), San Francisco, USA, 2009
 
(128) Belleville M., Sicard G., Pistone F., Maillart P., Decaens G., Villard P., Thabuis T., A comparative study of on chip decorrelation schemes for low power, high resolution Infrared sensors, Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), Toulouse, France, 2009
 
(129) Renaudin M., Qaisar S.-M., Fesquet L., Adaptative Rate Sampling and Filtering based on level crossing sampling, Eurasip Advances in Signal Processing, 2009, Article ID 971656, page: 12 pages, 2009
 
(130) Bidegaray-Fesquet B., Fesquet L., A fully nonuniform approach to FIR filtering, Sampling Theory and Applications (SampTA’09), Marseille, France, 2009
 
(131) Reis R., Possamai Bastos R., Monnet Y., Sicard G., Kastensmidt F., Renaudin M., A Methodology to Evaluate Transient-Fault Effects on Asynchronous and Synchronous Circuits, 14th IEEE European Test Symposium (ETS'09), Sevilla, Spain, 2009
 
(132) Renaudin M., Goulier J., André E., A new analystical approach of the impact of jitter of the continuous time delta sigma converters, VLSI-SoC: Advanced Topics on Systems on a Chip, Springer , 1-16, Volume 291, 2009
 
(133) Fesquet L., Beyrouthy T., A secure asynchronous FPGA for an embedded system, PhD Forum DATE, Nice, 2009
 
(134) Fesquet L., Yahya E., Asynchronous Design: A Promising Paradigm for Electronic Circuits and Systems, IEEE International Conference on Electronics and Systems (ICECS’09), Hammamet, Tunisia, 2009
 
(135) Hamon J., Asynchronous oscillators and architectures for UWB impulse radio signal processing, These de Doctorat, 2009
 
(136) Beyrouthy T., Asynchronous programmable logic for secured embedded systems, These de Doctorat, 2009
 
(137) Sicard G., Zimouche H., Capteur de vision CMOS à réponse insensible à la température, Journées Nationales du RÉseau Doctoral en Microélectronique (JNRDM’09), Lyon, France, 2009
 
(138) Kastensmidt F., Renaudin M., Reis R., Sicard G., Monnet Y., Possamai Bastos R., Comparing Transient-Fault Effects on Synchronous and on Asynchronous Circuits, 15th IEEE International On-Line Testing Symposium (IOLTS'09), Sesimbra-Lisbon, Portugal, 2009
 
(139) Fesquet L., Miscopein B., Renaudin M., Hamon J., Constrained Asynchronous Ring Structures for Robust Digital Oscillators, IEEE Transactions on VLSI Systems, 17, page: 907-919, 2009
 
(140) Fesquet L., Zakaria H., Controlling Energy and Process Variability in System-on-Chips: needs for control theory, 3rd IEEE Multi-conference on Systems and Control (MSC’09), Saint Petersburg, Russia, 2009
 
(141) Reis R., Kastensmidt F., Possamai Bastos R., Design of a soft-error robust microprocessor, Microelectronics journal, 40, July, page: 1062-1068, 2009
 
(142) Alsayeg K., Renaudin M., Rios D., Sicard G., Fesquet L., Direct mapping of sequential QDI controllers, Design, Automation and Test In Europe (DATE'09), Nice, France, 2009
 
(143) Fesquet L., Beyrouthy T., DPA robust S-BOX implementation on a secure asynchronous FPGA, Cryptarchi Conference, Prague, Czech republic, 2009
 
(144) Fesquet L., Renaudin M., Qaisar S.-M., Effective Resolution of an Adaptive Rate ADC, 8th International Conference on Sampling Theory and Applications (SampTA’09), Marseille, France, 2009
 
(145) Lizarraga L., Mir S., Sicard G., Experimental validation of a BIST technique for CMOS active pixel sensors, 27th IEEE VLSI Test Symposium (VTS’09), Santa Cruz, USA, 2009
 
(146) Fesquet L., Logiciel , FR.001.220016.000.S.P.2009.000.31500, 2009
 
(147) Koch-Hofer C., Modeling, Validation and Presynthesis of Asynchronous Circuits in SystemC, These de Doctorat, 2009
 
(148) Renaudin M., Rios D., Sicard G., Fesquet L., Alsayeg K., Optimizing speed and consumption of QDI controllers using direct mapping synthesis, Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), Toulouse, France, 2009
 
(149) Elissati O., Yahya E., Fesquet L., Rieubon S., Oscillation Period and Power Consumption in Configurable Self-Timed Rings Oscillators, Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), Toulouse, France, 2009
 
(150) Yahya E., Performance Modeling, Analysis and Optimization of Multi-Protocol Asynchronous Circuits, These de Doctorat, 2009
 
(151) Renaudin M., Yahya E., Elissati O., Zakaria H., Fesquet L., Programmable/Stoppable Oscillator Based on Self-Timed Rings, Asynchronous Circuits and Systems, 2009. ASYNC '09. 15th IEEE Symposium on, 2009
 
(152) Fesquet L., Alsayeg K., Morin-Allory K., RAT-based formal verification of QDI asynchronous controllers, Forum on specifications and Design Languages (FDL’09), Sophia Antipolis, France, 2009
 
(153) Renaudin M., Fesquet L., Qaisar S.-M., Signal Driven Sampling and Filtering : A Promising Approach for Time Varying Signals Processing, International Journal of Signal Processing, 5, page: 189-197, 2009
 
(154) Qaisar S.-M., Signal Driven Sampling and Processing : A Promising Approach for Adaptive Rate Computationally Efficient Solutions, These de Doctorat, 2009
 
(155) Sicard G., Amhaz H., Rolland R., Labonne E., Traitement de bas niveau intégré : Mise en oeuvre d’une adaptation aux conditions lumineuses dans un capteur d’images CMOS, 22ème colloque GRETSI, Dijon, France, 2009
 
(156) Sicard G., Clerc S., Abouzeid F., Renaudin M., Ultra-Low Voltage from 65nm to 32nm, 8èmes Journées Faible Tension Faible Consommation (FTFC’09), Neuchatel, Switzerland, 2009
 
(157) Sauvage L., Danger J.-L., Beyrouthy T., Fesquet L., Chaudhuri S., Guilley S., Updates on the Potential of Clock-Less Logics to Strengthen Cryptographic Circuits against Side-Channel Attacks, IEEE International Conference on Electronics and Systems (ICECS’09), Hammamet, Tunisia, 2009
 
(158) Yahya E., Renaudin M., AHMOSE: Towards a Circuit Level Solution for Process Variability, Design, Automation and Test in Europe Conference (DATE’08), Munich, Germany, March 10-14, 2008
 
(159) Qaisar S.-M., Renaudin M., Fesquet L., An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform, Research Letters in Signal Processing, Vol. 2008, Article ID 932068, , page: 5 pp., 2008
 
(160) Renaudin M., Fesquet L., Qaisar S.-M., An Improved Quality Adaptative Rate Filtering Technique Based on the Level Crossing Sampling, Computer Vision, Image and Signal Processing (CVISP’08), Prague, Czech Republic, July 25-27, 2008
 
(161) Qaisar S.-M., Fesquet L., Renaudin M., An improved quality filtering technique for time varying signals based on the level crossing sampling, International Conference of Signals and Electronic Systems 2008 (ICSES’08), Krakow, Poland, September 14-17, 2008
 
(162) Fesquet L., Beyrouthy T., A secure asynchronous configurable cell: an embedded programmable logic for smartcards, Workshop on Cryptographic Architectures embedded in reconfigurable devices (CryptArchi’08), Tregastel, France, June 1-4 (Comm. sans actes), 2008
 
(163) Renaudin M., Beyrouthy T., Fesquet L., Razafindraibe A., Chaudhuri S., Guilley S., Hoogvorst P., Danger J.-L., A Secure Programmable Architecture with a Dedicated Tech-mapping Algorithm: Application to a Crypto-Processor, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, November 12-14, 2008
 
(164) Rolland R., Sicard G., Labonne E., A Standard 3.5T CMOS Imager including a Light Adaptive System for Integration Time Optimisation, Conference on Design and Architectures for Signal and Image Processing (DASIP’08), Bruxelles, Belgium November 24 -26, 2008
 
(165) Fesquet L., Asynchronous integrated systems and non-uniformly sampled signal processing, HDR, 2008
 
(166) Renaudin M., Yahya E., Asynchronous Linear Pipelines: An Efficient-Optimal Pipelining Algorithm, 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS’08), Malta, August 31- September 03, 2008
 
(167) Renaudin M., Yahya E., Asynchronous Linear-Pipeline with Time Variable Delays: PerformanceModeling, Analysis and Slack Optimization, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, November 12-14, 2008
 
(168) Fesquet L., Morin-Allory K., Roustan B., Borrione D., Asynchronous online monitoring of logical and temporal assertions, Embedded Systems Specification and Design Languages, Springer , 278 p, 2008
 
(169) Renaudin M., Qaisar S.-M., Fesquet L., Computationally Efficient Adaptive Rate Sampling and Adaptive Resolution Analysis, Computer Vision, Image and Signal Processing (CVISP’08), Prague, Czech Republic, July 25-27, 2008
 
(170) Sicard G., Design of Concurent Integrated Systems : Cmos Image Sensors & Clockless Integrated Systems , HDR, 2008
 
(171) Fesquet L., Hamon J., Renaudin M., Miscopein B., High-level time-accurate model for the design of self-timed ring oscillators, Proceedings of 14th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’08), Newcastle upon Tyne, UK, 7th – 11th April , 2008
 
(172) Fesquet L., Schwoerer J., Miscopein B., Hamon J., Renaudin M., Implémentation en logique asynchrone d’un algorithme de synchronisation de signaux radio impulsionnelle, 7ème journées d'études Faible Tension Faible Consommation, (FTFC’08),Université Catholique de Louvain, Belgique, May 26-28, 2008
 
(173) Anghel L., Morin-Allory K., Fesquet L., Initiation à la conception de VLSI numériques, 10èmes journées pédagogiques CNFM, Saint-Malo, France, November 26-28, 2008
 
(174) Marchand N., Canudas de Wit C., Thonnard Y., Albea-Sanchez C., Durand S., Fesquet L., Zakaria H., Integrated Asynchronous Regulation for Nanometric Technologies: Application to an Embedded Parallel System, MINATEC CROSSROADS'08, June 23-27, 2008, Grenoble, 2008
 
(175) Rios D., Low power asynchronous systems, These de Doctorat, 2008
 
(176) Renaudin M., Yahya E., Optimal Asynchronous Linear-Pipelines, The fourth conference on Ph.D. Research in Microelectronics and Electronics (PRIME’08), Istanbul, Turkey, 2008
 
(177) Buhrig A., Optimization of the energy consumption in wireless sensor network nodes, These de Doctorat, 2008
 
(178) Renaudin M., Danger J.-L., Hoogvorst P., Guilley S., Chaudhuri S., Razafindraibe A., Fesquet L., Beyrouthy T., Physical Design of FPGA Interconnect to Prevent Information Leakage, Reconfigurable Computing: Architecture, Tools, and Applications, Springer , 87-98, 2008
 
(179) Miscopein B., Fesquet L., Renaudin M., Hamon J., Schwoerer J., Self-Timed Implementation of an Impulse Radio Synchronisation Acquisition Algorithm, Conference on Design and Architectures for Signal and Image Processing (DASIP’08), Bruxelles, Belgium November 24 -26, 2008
 
(180) Renaudin M., Yahya E., Lopin G., Standard-Logic Quasi Delay Insensitive Registers, Proc. of 16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC’08), Rhodes Island, Greece, 2008
 
(181) Rios D., Fesquet L., Alsayeg K., Renaudin M., Sicard G., Synthesis of asynchronous QDI FSM based on optimized sequencers, 34th European Conference on Solid-States Circuits (ESSCIRC’08), ESS Fringe Poster Session, Edinburgh, Scotland, 2008
 
(182) Qaisar S.-M., Renaudin M., Fesquet L., Adaptive Rate Filtering for a Signal Driven Sampling Scheme, 32nd IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’07), Honolulu, Hawaï, USA, 15-20 April , 2007
 
(183) Renaudin M., Qaisar S.-M., Fesquet L., Adaptive Rate Sampling and Filtering for Low Power Embedded Systems, Sampling Theory and Applications (SampTA’07), Thessaloniki, Greece, 1 - 5 June , 2007
 
(184) Labonne E., Renaudin M., Sicard G., A High Dynamic Range CMOS Imager with a Light Adaptive System and Digital Outputs, Workshop on "Image Sensors analog and digital on-chip processing", Toulouse, France, November 21-22, 2007
 
(185) André E., Renaudin M., Goulier J., A new analytical approach of the impact of jitter on continuous time delta sigma converters , International Conference on Very Large Scale Integration (VLSI-SoC'07), Atlanta, October 15-17, 2007
 
(186) Renaudin M., Labonne E., Sicard G., An on-pixel FPN reduction method for a high dynamic range CMOS imager, 33rd European Solid-State Circuits Conference (ESSCIRC’07), Munich, Germany, September 11-13, 2007
 
(187) Renaudin M., Hoogvorst P., Razafindraibe A., Guilley S., Chaudhuri S., Beyrouthy T., Danger J.-L., Fesquet L., A novel asynchronous e-FPGA architecture for security applications, International Conference on Field-Programmable Technology (ICFPT'07), Kokurakita, Kitakyushu, Japan, December 12th - 14th, 2007
 
(188) Thonnard Y., Vivet P., Renaudin M., Koch-Hofer C., ASC, a SystemC extension for Modeling Asynchronous Systems, and its application to an Asynchronous NoC, ACM/IEEE International Symposium on Networks on Chip (NOCs’07), Princeton, New Jersey, USA, May 7-9, 2007
 
(189) Ninon N., Sicard E., Boyer A., Renaudin M., Sicard G., Bouesse G.F., Asynchronous logic Vs Synchronouos logic: Concrete results on electromagnetic emissions and conducted susceptibility, 6th International workshop on electromagnetic compatibility of integrated circuits (EMC Compo'07), Torino, Italy, November 28-30, 2007
 
(190) Fesquet L., Morin-Allory K., Borrione D., Asynchronous online monitoring of logical and temporal assertions, 10th Forum on Specification and Design Languages (FDL'07), Barcelona, Spain, 18-20 September, 2007
 
(191) Bregier V., Automatic synthesis of optimised proven quasi delay insensitive asynchronous circuits, These de Doctorat, 2007
 
(192) Renaudin M., Circuits et Systèmes Electronique sans Horloge, Invited Talk on 9ème Rencontres Electronique de Dijon, Dijon, France, June 4-8, 2007
 
(193) Renaudin M., Clockless circuits and systems , Rencontres Electronique du CNRS, Dijon, France, 4 -8 juin , 2007
 
(194) Renaudin M., Qaisar S.-M., Fesquet L., Computationally Efficient Adaptive Rate Sampling and Filtering, 15th European Signal Processing Conference (EUSIPCO’07),Poznan, Poland, September 3-7, 2007
 
(195) Folco B., Contribution to the Synthesis of Quasi Delay Insensitive Asynchronous Circuits, Application to Secured Systems., These de Doctorat, 2007
 
(196) Dragulinescu A., Mir S., Lizarraga L., Sicard G., Defect and fault modelling of CMOS active pixel sensors, IEEE Latin American Test Workshop (LATW’07), Cuzco, Peru, March 11 - 14, 2007
 
(197) Renaudin M., Delay Insensitivity: a key property for future designs and technologies, 6ème journées d'études Faible Tension Faible Consommation (FTFC'07), Paris, France, May 21-23, 2007
 
(198) Sicard G., Fragoso J., Renaudin M., Estimation rapide du couple énergie/délai des circuits asynchrones QDI, Technique et Science Informatiques (TSI), 26, page: 535-565, 2007
 
(199) Lizarraga L., Sicard G., Mir S., Evaluation of a BIST technique for CMOS imagers, Asian Test Symposium (ATS’07), Beijing, China, October 8-11, 2007 , 2007
 
(200) Monnet Y., Leveugle R., Renaudin M., Formal analysis of quasi delay insensitive circuits behavior in the presence of SEUs, 13th IEEE International On-Line Testing symposium (IOLT’07), Hersonissos-Heraklion, Crete, Greece, July 8-11, 2007
 
(201) Labonne E., High dynamic range CMOS imager design, These de Doctorat, 2007
 
(202) Renaudin M., Sicard G., Bouesse G.F., Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals, VLSI-SOC: From Systems to Silicon, Springer , 11-24, Vol. 240, 2007
 
(203) Julien N., Renaudin M., Méthodes et outils pour la conception de SoC faible consommation, Technique et Science Informatiques (TSI), 26, page: 505-508, 2007
 
(204) Quartana J., Fesquet L., Renaudin M., Modular asynchronous Network-on-Chip: application to GALS systems rapid prototyping, VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005), Springer , 195-207, 2007
 
(205) Renaudin M., Buhrig A., On the use of real-time specifications for reducing power consumption in wireless sensor network, 6èmes journées d'études Faible Tension Faible Consommation (FTFC’07), Paris, France, 21-23 May, 2007
 
(206) Coulon P.Y., Galilee B., Mamalet F., Renaudin M., Parallel asynchronous watershed algorithm-architecture, IEEE Transactions on Parallel and Distributed Systems, 18, page: 44-56, 2007
 
(207) Yahya E., Renaudin M., Performance Modeling and Analysis of Asynchronous Linear-Pipeline, Journées GDR SOC-SIP'07, Paris, France, 13-15 June , 2007
 
(208) Yahya E., Renaudin M., Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays, 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS’07), Marrakech, Morocco, December 11-14, 2007
 
(209) Renaudin M., Rios D., Folco B., Monnet Y., Power consumption profile analysis of asynchronous QDI circuits , 6ème journées d'études Faible Tension Faible Consommation (FTFC’07), ISEP – Paris, France, 21-23 May, 2007
 
(210) Fesquet L., Renaudin M., Beyrouthy T., Razafindraibe A., Secure Asynchronous FPGA for Embedded Systems (SAFE), Colloque Journées GDR SOC-SIP'07, Paris, France, June 13-15, 2007
 
(211) Monnet Y., Study and modelling of secure circuits against non invasive fault injection attacks, These de Doctorat, 2007
 
(212) Renaudin M., Folco B., Bregier V., Fesquet L., Technology mapping for area optimized quasi delay insensitive circuits, VLSI-SOC: From Systems to Silicon, Springer , 55-69, Vol. 240, 2007
 
(213) Dohler M., Valois F., Heusse M., Duda A., Renaudin M., Paugnat F., Buhrig A., Dugas C., Aubert S., Mounier L., Maraninchi F., Barthel D., The ARESA Project: Facilitating Research, Development and Commercialization of WSNs, Fourth Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks, SECON 2007, June 18-21, San Diego, California, USA, 2007
 
(214) Renaudin M., Koch-Hofer C., Timed Asynchronous Circuits Modeling using SystemC, 10th Forum on Specification and Design Languages (FDL'07), Barcelona, Spain, September 18-20, 2007
 
(215) Renaudin M., Berger P.-D., Sicard G., Labonne E., A 100dB dynamic range CMOS image sensor with global shutter, 13th IEEE International Conference on Electronics, Circuits and Systems (ICECS’06), Nice, France, December 10-13, 2006
 
(216) Renaudin M., Labonne E., Sicard G., A 120dB CMOS imager with a light adaptive system and digital outputs, 2nd Conference on Ph.D. Research in Microelectronics and Electronics (PRIME’06), Otranto, Italy, June 12-15, 2006
 
(217) Labonne E., Renaudin M., Sicard G., A high dynamic range CMOS image sensor with on-chip FPN reduction method, XXI Conference on Design of Circuits and Integrated Systems (DCIS’06), Barcelona, Spain, November 22-24, 2006
 
(218) Portolan M., Leveugle R., A highly flexible hardened RTL processor core based on LEON2, IEEE Transactions on Nuclear Science, Volume 53, Part 1, Aug., page: 2069 - 2075, 2006
 
(219) Fesquet L., Morin-Allory K., Borrione D., Asynchronous Assertion Monitors for multi-Clock Domain System Verification, Proc. 17th IEEE Symposium on Rapid System Prototyping, Chania, Greece, 14-16 June, 2006
 
(220) Renaudin M., Yahya E., Asynchronous Buffers: Characteristics, Modeling and Design, ISRN: TIMA-RR--06/03-01--FR, 2006
 
(221) Renaudin M., Monnet Y., Asynchronous design: fault robustness and security characteristics, 12th IEEE International On-Line Testing symposium (IOLT’06), Como, Italy, July 10-12, 2006
 
(222) Borrione D., Morin-Allory K., Fesquet L., Asynchronous on-line monitoring of PSL assertions, Proc. 17th IEEE Symposium on Rapid System Prototyping, Chania, Greece, 14-16 June , 2006
 
(223) Caucheteux D., Crochon E., Renaudin M., Beigné E., AsyncRFID: fully asynchronous contactless systems, providing high data rates, low power and dynamic adaptation, 12th IEEE International Symposium on Asynchronous Circuits and Systems, March 13-15., 2006
 
(224) Moitrel P., Clavier C., Leveugle R., Renaudin M., Monnet Y., Case Study of a Fault Attack on Asynchronous DES Crypto-Processors, 3rd Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 06), Yokohama, Japan, October 10th, 2006
 
(225) Renaudin M., CONTACTLESS COMMUNICATIONS METHOD BASED ON ASYNCHRONOUS MODULATIONS AND DEMODULATIONS, WO2006108986, 2006
 
(226) Lizarraga L., Mir S., Sicard G., Dragulinescu A., Defect and fault modelling of a CMOS n-diffusion photodiode, 3rd International Conference on Advanced Topics in Optoelectronics, Microelectronics and Nanotechnologies (ATOM-N’06), Bucharest, Romania, November 24-26, 2006
 
(227) Leveugle R., Monnet Y., Renaudin M., Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic, IEEE Transactions on Computers, Volume: 55, page: 1104 - 1115, 2006
 
(228) Fragoso J., Renaudin M., Sicard G., Estimation rapide du couple énergie/délai des circuits asynchrones QDI, ISRN: TIMA-RR--06/10-01--FR, 2006
 
(229) Renaudin M., Bouesse G.F., Sicard G., Improving DPA resistance of Quasi Delay Insensitive Circuits using randomly time-shifted Acknowledgement Signals , ISRN: ISRN: TIMA-RR--06/02-01--FR, 2006
 
(230) Buhrig A., Sicard G., Renaudin M., Rios D., On the use of feedback control to dynamically control the supply voltage of low-power circuits, Journal of Low Power Electronics (JOLPE), 2, page: 45–55, 2006
 
(231) Sicard G., Bouesse G.F., Renaudin M., Path swapping method to improve DPA resistance of QDI asynchronous circuits, 8th International Workshop on Cryptographic Hardware and Embedded Systems (CHES’06),Yokohama, Japan, October , 2006
 
(232) Renaudin M., Monnet Y., M'Buwa Nzenguet F., Moitrel P., Feyt N., Leveugle R., Practical evaluation of fault countermeasures on an asynchronous DES cryptoprocessor, 12th IEEE International On-Line Testing Symposium (IOLT’06), Como, Italy, July 10-12, 2006
 
(233) Renaudin M., Yahya E., QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer , 583-592 , 2006
 
(234) Renaudin M., Yahya E., QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’06), Montpellier, France, September 13-15, 2006
 
(235) Yahya E., Renaudin M., QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis, ISRN: TIMA-RR--06/06-03--FR, 2006
 
(236) Maurine P., Renaudin M., Robert M., Razafindraibe A., Security evaluation of dual rail logic against DPA attacks, Proc. 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October 16-18, 2006
 
(237) Renaudin M., Qaisar S.-M., Fesquet L., Spectral analysis of a signal driven sampling scheme, 14th European Signal Processing Conference (EUSIPCO’06), Florence, Italy, September 4-8, 2006
 
(238) Renaudin M., Lopin G., Yahya E., Standard-Logic Quasi Delay Insensitive Latches, ISRN: TIMA-RR--06/06-04--FR, 2006
 
(239) Fesquet L., Renaudin M., Steiner M., Folco B., State-holding in Look-Up Tables: application to asynchronous logic, 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October 16-18, 2006
 
(240) Lizarraga L., Mir S., Sicard G., Bounceur A., Study of a BIST technique for CMOS active pixel sensors, 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October, 2006
 
(241) Borrione D., Sirianni A., Renaudin M., Mounier L., Boubekeur M., Validation of Asynchronous Circuit Specifications Using IF/CADP, VLSI-SOC: From Systems to Chips, Springer , 85-100, 2006
 
(242) Lizarraga L., Sicard G., Mir S., Vers une technique d’auto test incorporé (BIST) pour des pixels actifs CMOS, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, France, May 10-12, 2006
 
(243) Dezzani A., Allier E., André E., Renaudin M., Sicard G., Goulier J., A 120nm low power asynchronous ADC, Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on, 2005
 
(244) Allier E., André E., Sicard G., Goulier J., Renaudin M., Dezzani A., A 120nm Low Power Asynchronous ADC, ISRN: TIMA-RR--06/02-08--FR, 2005
 
(245) Germain F., Witon A., Renaudin M., Bouesse G.F., A clock-less low-voltage AES crypto-processor, Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European. Grenoble, FR, 2005
 
(246) Renaudin M., Razafindraibe A., Robert M., Maurine P., A Method to Design Compact Dual-rail Asynchronous Primitives, Integrated Circuit and System Design 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 20-23, 2005. Proceedings, 2005
 
(247) Dumont S., Renaudin M., Monnet Y., Bouesse G.F., Leveugle R., An Asynchronous DES Crypto-Processor Secured against Fault Attacks, 15th IFIP Int. Conf. on Very Large Scale Integration Systems, VLSI-SoC'05, October 17-19. Perth, AU, 2005
 
(248) Renaudin M., Bouesse G.F., Leveugle R., Monnet Y., Dumont S., An Asynchronous DES Crypto-Processor Secured against Fault Attacks, ISRN: TIMA-RR--06/02-04--FR, 2005
 
(249) Renaudin M., Beigné E., Clermidy F., Vivet P., Clouard A., An asynchronous NOC architecture providing low latency service and its multi-level design framework, Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on, 2005
 
(250) Renaudin M., Caucheteux D., Crochon E., Beigné E., A New Class of Asynchronous Inductive Contactless Devices Using Event Based Communications And Self-Timed Logic, International Conference on Very Large Scale Integration (VLSI-SoC'05),17-19 October. Perth, AU, 2005
 
(251) Fesquet L., Renaudin M., A programmable logic architecture for prototyping clockless circuits, 15th Int. Conf. on Field Programmable Logic & Applications (FPL'05), Tampere, Finland, August 24-26, 2005
 
(252) Renaudin M., Fesquet L., A PROGRAMMABLE LOGIC ARCHITECTURE FOR PROTOTYPING CLOCKLESS CIRCUITS , ISRN: TIMA-RR--06/02-16--FR, 2005
 
(253) Buhrig A., Rios D., Renaudin M., Asservissement de vitesse pour minimiser la puissance consommée par un processeur , ISRN: TIMA-RR--06/02-06--FR, 2005
 
(254) Barthel D., Renaudin M., Buhrig A., Asynchronous Architecture for Sensor Network Nodes, MedHocNet, Porquerolles, France, June 20-22, 2005
 
(255) Leveugle R., Renaudin M., Monnet Y., Asynchronous Circuits Sensitivity To Transient Faults, ISRN: TIMA-RR--05/04-02--FR, 2005
 
(256) Monnet Y., Renaudin M., Leveugle R., Asynchronous circuits transient faults sensitivity evaluation, Annual ACM IEEE Design Automation Conference, Proceedings of the 42nd annual conference on Design automation. San Diego, California,, US, 2005
 
(257) Monnet Y., Leveugle R., Renaudin M., Asynchronous circuits transient faults sensitivity evaluation, Proceedings 2005. 42nd Design Automation Conference , 2005
 
(258) Renaudin M., Monnet Y., Leveugle R., Asynchronous Circuits Transient Faults Sensitivity Evaluation, ISRN: TIMA-RR--06/02-02--FR, 2005
 
(259) Maurine P., Robert M., Renaudin M., Razafindraibe A., Asynchronous dual rail cells to secure cryptosystem against Side Channel Attacks, Sophia Antipolis MicroElectronic (SAME 2005 Forum), Sophia Antipolis, France, October 5-6, 2005
 
(260) Sicard G., Allier E., Fesquet L., Renaudin M., Asynchronous level crossing analog to digital converters, Measurement, Volume 37 , page: 296-309, 2005
 
(261) Renaudin M., Quartana J., Fesquet L., Asynchronous Systems on Programmable Logic, Reconfigurable Communication-centric SoCs (ReCoSoC'05), Montpellier, France, June 27-29, 2005
 
(262) Renaudin M., Quartana J., Fesquet L., Asynchronous Systems on Programmable Logic, ISRN: TIMA-RR--06/02-12--FR, 2005
 
(263) Labonne E., Renaudin M., Sicard P., Capteur de vision CMOS à grande dynamique et adapté aux conditions , ISRN: TIMA-RR--06/02-09--FR, 2005
 
(264) Renaudin M., Circuits Asynchrones et Consommation, 5ème Journées d'études Faible Tension, Faible Consommation (FTFC’05), Paris, France, May 18-19, 2005
 
(265) Renaudin M., Circuits et systèmes asynchrones: une approche architecturale, École thématique «Architectures des systèmes matériels enfouis et méthodes de conception associées (ARCHI’05)», Autrans (Vercors), France, March 21-25, 2005
 
(266) Renaudin M., Buhrig A., Rios D., Controlling processors ’speed using dynamic voltage scaling, 5ème Journées d'études Faible Tension, Faible Consommation (FTFC’05), Paris, France, May 18-19, 2005
 
(267) Renaudin M., Bouesse G.F., Monnet Y., Designing resistant asynchronous circuits against malicious fault injection, 3rd International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi’05), Saint-Etienne, France, June 8-11, 2005
 
(268) Renaudin M., Germain F., Dumont S., Bouesse G.F., DPA on quasi delay insensitive asynchronous circuits: formalization and improvement, Design, Automation and Test in Europe, 2005. Proceedings, 2005
 
(269) Fesquet L., Aeschlimann F., Renaudin M., Allier E., Etude Spectrale de l'’Échantillonnage par Traversée de Niveaux, ISRN: TIMA-RR--06/02-11--FR, 2005
 
(270) Renaudin M., Fragoso J., Sicard G., Fast Performance Comparison of Asynchronous Circuits , 5ème journées d'études Faible Tension, Faible Consommation (FTFC’05), Paris, France, May 18-19, 2005
 
(271) Renaudin M., Bouesse G.F., Dumont S., Germain F., Formalizing and Improving DPA resistance, ISRN: TIMA-RR--06/02-18--FR, 2005
 
(272) Dubreuil H., Fesquet L., Renaudin M., Huot N., FPGA architecture for multi-style asynchronous logic, Design Automation and Test in Europe Conference and Exhibition (DATE ’05), Munich,Germany, pp.32-33, March 7-11, 2005 , 2005
 
(273) Dubreuil H., Renaudin M., Fesquet L., Huot N., FPGA architecture for multi-style asynchronous logic, ISRN: TIMA-RR--06/02-10--FR, 2005
 
(274) Fesquet L., Huot N., Renaudin M., Dubreuil H., FPGA architecture for multi-style asynchronous logic [full-adder example], Design, Automation and Test in Europe, 2005. Proceedings, 2005
 
(275) Fesquet L., Renaudin M., Renane S., Baixas A., Quartana J., GALS Systems Prototyping using Multiclock FPGAs , ISRN: TIMA-RR--06/02-15--FR, 2005
 
(276) Fesquet L., Quartana J., Renaudin M., Renane S., Baixas A., GALS systems prototyping using multiclock fpgas and asynchronous network-on-chips, Field Programmable Logic and Applications, 2005. International Conference on, 2005
 
(277) Monnet Y., Renaudin M., Leveugle R., Hardening techniques against transient faults for asynchronous circuits, 11th-IEEE-International-On-Line-Testing-Symposium. 2005:, 2005
 
(278) Leveugle R., Renaudin M., Monnet Y., Hardening Techniques against Transient Faults for Asynchronous Circuits , ISRN: TIMA-RR--06/02-05--FR, 2005
 
(279) Kaiser A., Brillouet M., Fesquet L., Cristoloveanu S., IEEE European Solid-State Circuits Conference (ESSCIRC), IEEE Computer Society, , 2005
 
(280) Renaudin M., Bouesse G.F., Improving DPA resistance of Quasi-delay Insensitive Asynchronous Circuits, 3rd International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi’05), Saint-Etienne, France, June 8-11, 2005
 
(281) Sicard G., Bouesse G.F., Renaudin M., Improving DPA resistance of Quasi Delay Insensitive Circuits using randomly time-shifted Acknowledgement Signals, 15th IFIP Int. Conf. on Very Large Scale Integration Systems, VLSI-SoC'05, October 17-19. Perth, AU, 2005
 
(282) Fesquet L., Quartana J., Renaudin M., Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping, 15th IFIP Int. Conf. on Very Large Scale Integration Systems (VLSI-SoC'05), Perth, Australia, October 17-19, 2005
 
(283) Renaudin M., Fesquet L., Quartana J., Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping, ISRN: TIMA-RR--06/02-14--FR, 2005
 
(284) Liu Z.W., Borrione D., Fesquet L., Ostier P., Morin-Allory K., On-Line Assertion-Based Verification with Proven Correct Monitors, 3rd IEEE International Conference on Information and Communication Technology (ICICT'05), December 5-6, 2005. cairo, EG, 2005
 
(285) Leveugle R., Portolan M., On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors, IEEE International On-Line Testing Symposium (IOLT'05), Saint Raphael, France, July 6-8, 2005
 
(286) Guyot A., OPAR: combinatorial arithmetic operators, , , 2005
 
(287) Guyot A., OPAR: Cours & exercises d'arithmétique en Java , , , 2005
 
(288) Renaudin M., Panel: Power Management Adaptive techniques: Where are we? Where are we going?, 5ème Journées d'études Faible Tension, Faible Consommation (FTFC’05), Paris, France, May 18-19, 2005
 
(289) Buhrig A., Renaudin M., Rios D., Power Consumption reduction using dynamic control of microprocessor performance, ISRN: TIMA-RR--06/02-17--FR, 2005
 
(290) Rios D., Buhrig A., Renaudin M., Power Consumption reduction using dynamic control of Micro Processor performance, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, 2005
 
(291) Fesquet L., Ostier P., Liu M., Borrione D., PSL-based online monitoring of digital systems, Forum on specification and Design Languages (FDL'05), Lausanne, Switzerland, September 27-30, 2005
 
(292) Bouesse G.F., Fesquet L., Monnet Y., Renaudin M., Secure asynchronous circuits design and prototyping, at 3rd International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi’05), Saint-Etienne, France, June 8-11, 2005
 
(293) Renaudin M., Bouesse G.F., Monnet Y., Secure asynchronous circuits for Smart-Card applications: Design and Methodologies, MEDEA+ DAC Conference, Les Mesnuls, France, May 24-26, 2005
 
(294) Aeschlimann F., Renaudin M., Fesquet L., Allier E., Spectral analysis of level crossing sampling scheme, International Workshop on Sampling theory and application (SAMPTA’'05), Samsun, Turkey, July 10-15, 2005
 
(295) Renaudin M., Aeschlimann F., Fesquet L., Allier E., Spectral Analysis of Level-Crossing Sampling Scheme, ISRN: TIMA-RR--06/02-13--FR, 2005
 
(296) Fesquet L., Bregier V., Folco B., Renaudin M., Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits, ISRN: TIMA-RR--06/02-03--FR, 2005
 
(297) Bregier V., Renaudin M., Folco B., Fesquet L., Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits, 15th IFIP Int. Conf. on Very Large Scale Integration Systems (VLSI-SoC'05), October 17-19. Perth, FR, 2005
 
(298) Caucheteux D., Renaudin M., Beigné E., Crochon E., Toward Asynchronous and High Data Rates Contactless Systems, Proceedings of the 1st IEEE Ph.D. Research in Micro-Electronics and Electronics Conference (PRIME’'05), Lausanne, Switzerland, 25-28 July, 2005
 
(299) Charlot B., Matou K., Buhrig A., Basrour S., Ammar Y., Renaudin M., Marzencki M., Wireless sensor network node with asynchronous architecture and vibration harvesting micro power generator, The Smart Objects and Ambient Intelligence Conference (SoC-EUSAI'05), October 12-14. Grenoble, FR, 2005
 
(300) Portolan M., Leveugle R., A context-switch based checkpoint and rollback scheme, 19th Conference on Design of Circuits and Integrated Systems (DCIS), Bordeaux, France, November 24-26, 2004
 
(301) Sicard G., Panyasak D., Renaudin M., A current shaping methodology for lowering EM disturbances in asynchronous circuits, Microelectronics journal, June: 35(6), page: 531-40, 2004
 
(302) Slimani K., Renaudin M., Sicard G., A Methodology for estimating energy consumption of QDI asynchronous circuits, 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’04), Isle of Santorini, Greece, September 15-17, 2004
 
(303) Sicard G., Allier E., Renaudin M., Fesquet L., A new type of Asynchronous Analog to Digital Interface, Journal of International Measurement Confederation, Vol.35 , page: , 2004
 
(304) Bouesse G.F., Renaudin M., Germain F., Asynchronous AES Crypto-Processor including Secured and Optimized Blocks, Journal of Integrated Circuits and Systems, Vol. 1, page: 5-13, 2004
 
(305) Monnet Y., Renaudin M., Leveugle R., Asynchronous circuits sensitivity to fault injection, Proceedings.-10th-IEEE-International-On-Line-Testing-Symposium. 2004, 2004
 
(306) Aeschlimann F., Allier E., Fesquet L., Renaudin M., Asynchronous FIR filters: towards a new digital processing chain, Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on, 2004
 
(307) Essalhiene M., Renaudin M., Fesquet L., Asynchronous technology for energy reduction in embedded systems, Annals of telecommunications, Vol. 59-August, page: , 2004
 
(308) Renaudin M., Sicard G., Panyasak D., Asynchronus design for improved EMC behavior of ICs, 4th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo’04), Angers, France, March 31-April 1st, 2004
 
(309) Sicard G., Conception avec VHDL-AMS, , , 2004
 
(310) Abou-Samra S.-J., Guyot A., Conception pour la faible consommation , , , 2004
 
(311) Beigné E., Bouesse G.F., Robisson B., Liardet P.-Y., Renaudin M., Prevosto S., DPA on quasi delay insensitive asynchronous circuits: concrete results, XIX Conference on Design of Circuits and Integrated Systems (DCIS’04), Bordeaux, France, November 24-26, 2004
 
(312) Renaudin M., Labonne E., Sicard G., Dynamic Voltage Scaling and Adaptive Body Biasing Study for Asynchronous Design, ISRN: TIMA-RR--04/06-01--FR, 2004
 
(313) Renaudin M., Yakovlev A., From Hardware Processes to asynchronous circuits via petri nets: An Application to Arbiter Design , Workshop on Token Based Computing (TOBACO’04), Bologna, Italy, June 22, 2004
 
(314) Tual J.-P., Renaudin M., Bouesse G.F., Proust Ph., Sourgen L., Germain F., High security smartcards, Proceedings. Design, Automation and Test in Europe Conference and Exhibition, 2004
 
(315) Bouesse G.F., Renaudin M., Monnet Y., Improving DPA and DFA resistance of circuits using asynchronous logic, e-Smart 2004 and e-Government & Smartcard International Meeting, 5th Edition, Sophia Antipolis, French Riviera, France, September 22-24, 2004
 
(316) Fesquet L., Le paquetage VITAL, , , 2004
 
(317) Fesquet L., Les bases de la conception analogique intégrée, , , 2004
 
(318) Renaudin M., Slimani K., Fragoso J., Fesquet L., Low Power Asynchronous Processors, Low-Power Electronics Design, CRC Press, Chapter 22; Volume: 1, 2004
 
(319) Fesquet L., Renaudin M., Folco B., Bregier V., Modeling and synthesis of multi-rail multi-protocol QDI circuits, Thirteenth International Workshop on Logic and Synthesis, Temecula Creek (IWLS’04), California, USA, June 2-4, 2004
 
(320) Mounier L., Boubekeur M., Renaudin M., Sirianni A., Borrione D., Modeling CHP descriptions in labeled transitions systems for an efficient formal validation of asynchronous circuit specification, "Languages for System Specification", Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems and Property Specifications from FDL'03, Christoph Grimm, Kluwer, June , Kluwer Academic Publishers, , 2004
 
(321) Fesquet L., Modélisation et synthèse des systèmes matériels, , , 2004
 
(322) Baixas A., Mancini S., Fesquet L., Rolland R., Pratique d'un SOPC : application au filtrage numérique, , , 2004
 
(323) Bouesse G.F., Renaudin M., Baixas A., Sicard G., Quasi delay insensitive asynchronous circuits for low EMI, 4th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo’04), Angers, France, March 31-April 1st, 2004
 
(324) Razafindraibe A., Robert M., Maurine P., Folco B., Bouesse G.F., Renaudin M., Secured Structures for Secured Asynchronous QDI Circuits, XIX Conference on Design of Circuits and Integrated Systems (DCIS’04), Bordeaux, France, November 24-26, 2004
 
(325) Sicard G., Slimani K., Remond Y., Renaudin M., TAST profiler and low energy asynchronous design methodology, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. 14th International Workshop, PATMOS 2004. Proceedings , 2004
 
(326) Fesquet L., TD de modélisation et synthèse des systèmes matériels, , , 2004
 
(327) Fesquet L., Rolland R., Mancini S., TP d'architecture d'un SoC, , , 2004
 
(328) Boubekeur M., Rigaud J.B., Sirianni A., Borrione D., Renaudin M., Dumitrescu E., An approach to the introduction of formal validation in an asynchronous circuit design flow, 36th Hawaii International Conference on Systems Sciences. 6-9 Jan, 2003
 
(329) Borrione D., Sirianni A., Renaudin M., Boubekeur M., Rigaud J.B., Dumitrescu E., An approach to the introduction of formal validation in an asynchronous circuit design flow, ISRN: TIMA-RR--03/10-01--FR, 2003
 
(330) Allier E., Renaudin M., Sicard G., Fesquet L., A new class of asynchronous A/D converters based on time quantization, Proceedings Ninth International Symposium on Asynchronous Circuits and Systems, 2003
 
(331) Allier E., Fesquet L., Sicard P., Renaudin M., Asynchronous ADCs: Design Methodology and Case study, 8th International Workshop on ADC modelling and testing (IWADC’03), Perugia, Italy, September 8-10 , 2003
 
(332) Renaudin M., Fragoso J., Asynchronous Circuits Design: An Architectural Approach, Chapter in , , , 2003
 
(333) Fragoso J., Sicard G., Renaudin M., Automatic generation of 1-of-M QDI asynchronous adders, Proceedings 16th Symposium on Integrated Circuits and Systems Design. SBCCI , 2003
 
(334) Renaudin M., Fesquet L., Allier E., Sicard G., Conversion analogique-numérique faible consommation : conception asynchrone et echantillonnage irrégulier, 4ème Colloque sur le Traitement Analogique de l'Information, du Signal, et ses Applications (TAISA’03), Louvain-La-Neuve, Belgique, September 25-26 , 2003
 
(335) Sicard G., Remond Y., Sirianni A., Slimani K., Fesquet L., Renaudin M., Estimation et optimisation de la consommation d’énergie des circuits asynchrones, 4èmes journées d'études Faible Tension, Faible Consommation (FTFC’03), pp. 59-64, Paris, France, 15-16 May, 2003
 
(336) Guyot A., Exercices du cours d'Opérateurs Arithmétiques , , , 2003
 
(337) Sicard G., Renaudin M., Fragoso J., Generalized 1-of-M QDI adders, Third ACiD-WG Workshop of the European Commission’s Fifth Framework Programme, Heraklion, Crete, January 27-28, 2003
 
(338) Renaudin M., Nicolle S., Alacoque L., Irregular sampling and local quantification scheme A-D converter, Electronics Letters, 6 Feb.: 39(3), page: 263-4, 2003
 
(339) Renaudin M., Boubekeur M., Sirianni A., Mounier L., Borrione D., Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications, ISRN: TIMA--RR-03/10-04--FR, 2003
 
(340) Borrione D., Boubekeur M., Renaudin M., Mounier L., Sirianni A., Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications, Forum on specification and Design Languages (FDL'03), Frankfurt, Germany, September 23-26, 2003
 
(341) Renaudin M., Sicard G., Fragoso J., Power/Area trade-offs in 1-of-M parallel-prefix asynchronous adders, 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'03), Torino, Italy, September 10-12, 2003
 
(342) Maurine P., Renaudin M., Sicard G., Rigaud J.B., Static Implementation of QDI asynchronous primitives, 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'03), Torino, Italy, September 10-12, 2003
 
(343) Maurine P., Renaudin M., Bouesse G.F., Rigaud J.B., Sicard G., TAL : une bibliothèque de cellules pour le design de circuits asynchrones QDI, 4èmes journées d'études Faible Tension, Faible Consommation (FTFC’03), Paris, France,15-16 May , 2003
 
(344) Sirianni A., Boubekeur M., Borrione D., Renaudin M., Mounier L., Validation of asynchronous circuit specifications using IF/CADP, 12th IFIP International Conference on Very Large Scale Integration (VLSI’03), Darmstadt, Germany, December 1-3, 2003
 
(345) Renaudin M., Sicard G., Fesquet L., Allier E., A 6-bit Low-Power Asynchronous Analog-to-Digital Converter, ISRN: TIMA-RR--02/03-06--FR, 2002
 
(346) Sicard G., Renaudin M., Panyasak D., A current shaping methodology for low EMI asynchronous circuits, 3rd International Workshop on Electromagnetic Compatibility of Integrated design (EMC Compo’02), Toulouse, France, November 14-15, 2002, 2002
 
(347) Coulon P.Y., Renaudin M., Mamalet F., Galilee B., Algorithme-Architecture asynchrone massivement parallèle de ligne de partage des eaux, ISRN: TIMA-RR--02/03-05--FR, 2002
 
(348) Renaudin M., Asynchronous System Design, ISRN: TIMA--RR-02/03-01--FR, 2002
 
(349) Alacoque L., Abouchi N., Nicolle S., Renaudin M., Boucle analogique-numérique verrouillée sur l'amplitude, application à la conversion analogique-numérique pour la basse consommation, 3ème Colloque sur le Traitement Analogique de l'Information, du Signal et ses Applications (TAISA'02), ENST, Paris, France, September 12 -13, 2002, 2002
 
(350) Renaudin M., Fesquet L., Essalhiene M., Dynamic voltage scheduling for real time asynchronous systems, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 12th International Workshop, PATMOS 2002. Proceedings Lecture Notes in Computer Science , 2002
 
(351) Rigaud J.B., Renaudin M., Etude de l'art sur la conception des circuits asynchrones, perspectives pour l'intégration des systèmes complexes, ISRN: TIMA-RR--02/12-02--FR, 2002
 
(352) Fesquet L., Renaudin M., Rigaud J.B., Quartana J., High-level modeling and design of asynchronous arbiters for on-chip communication systems, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition., 2002
 
(353) Rigaud J.B., Quartana J., Fesquet L., Renaudin M., High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems, ISRN: TIMA-RR--02/03-3--FR, 2002
 
(354) Quartana J., Rigaud J.B., Fesquet L., Renaudin M., High-Level Modeling and Design of Asynchronous Arbiters. Poster presentation, ISRN: TIMA-RR--02/03-4--FR, 2002
 
(355) Fesquet L., Renaudin M., Rolland R., Thai-Ho Quoc, Rigaud J.B., Implementing asynchronous circuits on LUT based FPGAs, Field Programmable Logic and Applications. Reconfigurable Computing Is Going Mainstream. 12th International Conference, FPL 2002. Proceedings Lecture Notes in Computer Science Vol.2438., 2002
 
(356) Boubekeur M., Rigaud J.B., Dumitrescu E., Borrione D., Sirianni A., Renaudin M., Introducing formal validation in an asynchronous circuit design flow, The Fourth International Workshop on Designing Correct Circuits, Grenoble, France, April 6-7, 2002, 2002
 
(357) Renaudin M., La conception de systèmes asynchrones, Conception logique et physique des systèmes monopuces (Traité EGEM Série électronique et micro-électronique), Hermès, chapitre 5 : 143-220, 2002
 
(358) Renaudin M., La conception logique, Conception logique et physique des systèmes monopuces, Hermès, 27-64 ; chapitre 2, 2002
 
(359) Fesquet L., Allier E., Renaudin M., Sicard G., Low-power asynchronous A/D conversion, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 12th International Workshop, PATMOS 2002. Proceedings Lecture Notes in Computer Science, 2002
 
(360) Fesquet L., Renaudin M., Rigaud J.B., Quartana J., Modeling and design of asynchronous priority arbiters for on-chip, SOC Design Methodologies Series: IFIP International Federation for Information Processing, Kluwer Academic Publishers, 313-324, 2002
 
(361) Rigaud J.B., Quartana J., Renaudin M., Fesquet L., Modeling and design of asynchronous priority arbiters for on-chip communication systems, SOC Design Methodologies. IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems on Chip VLSI SOC'01, 2002
 
(362) Fesquet L., Bouesse G.F., Renaudin M., QDI Circuits to Improve Smartcard Security, ISRN: TIMA-RR--02/03/10--FR, 2002
 
(363) Mamalet F., Galilee B., Renaudin M., Coulon P.Y., Réseau calculant asynchrone dédié à la segmentation d'images, Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM'02), Grenoble, France, April 23-25, 2002, 2002
 
(364) Panyasak D., Renaudin M., Sicard G., Shaping Current Profile of Asynchronous Circuits, ISRN: TIMA-RR-02/03/09--FR, 2002
 
(365) Renaudin M., Dinh Duc Anh Vu, Fesquet L., Synthesis of QDI asynchronous circuits from DTL-style petri-net, 11th IEEE/ACM International Workshop on Logic & Synthesis (IWLS'02), New Orleans, Louisiana,USA, June 4-7, 2002, 2002
 
(366) Sirianni A., Fragoso J., Rezzag A., Rigaud J.B., Dinh Duc Anh Vu, Renaudin M., TAST CAD Tools, ISRN: TIMA--RR-02/04/01--FR, 2002
 
(367) Renaudin M., Rigaud J.B., Fesquet L., Sirianni A., Dinh Duc Anh Vu, Rezzag A., Fragoso J., TAST: TIMA Asynchronous Synthesis Tools, ISRN: TIMA-RR--02/03-08--FR, 2002
 
(368) Renaudin M., Essalhiene M., Fesquet L., Towards a Low Power RTOS for Asynchronous Processors, ISRN: TIMA-RR--02/03/07--FR, 2002
 
(369) Renaudin M., Galilee B., Mamalet F., Coulon P.Y., Watershed parallel algorithm for asynchronous processors array, : Proceedings-2002-IEEE-International-Conference-on-Multimedia-and-Expo-(ICME), 2002
 
(370) Coulon P.Y., Galilee B., Mamalet F., Renaudin M., Algorithme-Architecture Parallèle Asynchrone pour la Segmentation d'Image par Ligne de Partage des Eaux, ISRN: TIMA-RR--01/05-01--FR, 2001
 
(371) Senn P., Vivet P., Bouvier J., Abrial A., Renaudin M., A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller, IEEE Journal of Solid State Circuits, July ; 36(7), page: 1101-7, 2001
 
(372) Essalhiene M., Fesquet L., Renaudin M., Lhuillery F., Ho Q. T., Démonstration de prototypes d'objets communicants en technologie asynchrone, ISRN: TIMA--RR-01/10-14--FR, 2001
 
(373) Renaudin M., Ho Q. T., Essalhiene M., Lhuillery F., Fesquet L., La technologie asynchrone pour la conception d'objets communicants : une revue. Asynchronisme de la puce au système , ISRN: TIMA--RR-01/10-11--FR, 2001
 
(374) Fesquet L., Les fonctions analogiques intégrées , , , 2001
 
(375) Quartana J., Renaudin M., Rigaud J.B., Fesquet L., Modeling and design of asynchronous priority arbiters for on-chip communication systems, ISRN: TIMA--RR-01/10-10--FR, 2001
 
(376) Renaudin M., Quartana J., Fesquet L., Rigaud J.B., Modeling and design of asynchronous priority arbiters for on-chip communication systems, IFIP International Conference On Very Large Scale Integration (VLSI-SOC'01), Le Corum, Montpellier, France, December 3-5, 2001, 2001
 
(377) Piguet CH., Omnes T.-J.-F., Renaudin M., Special Session on Low-Power Systems on Chips & Marc RENAUDIN's Talk, ISRN: TIMA--RR-01/10-9--FR, 2001
 
(378) Omnes T.-J.-F., Renaudin M., Piguet CH., Special session on low-power systems on chips (SOCs), Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001., 2001
 
(379) Abrial A., Vivet P., Bouvier J., Renaudin M., A contactless smart-card chip based on an asynchronous 8-bit microcontroller, Asynchronous Circuits Design (ACiD) Workshop, Grenoble, January 31st - February 1st, 2000, 2000
 
(380) Abrial A., Vivet P., Senn P., Bouvier J., Renaudin M., A new contactless smartcard IC using an on-chip antenna and an asynchronous micro-controller, Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26th European, 2000
 
(381) Renaudin M., ASPRO : a toy demo , Asynchronous Circuits Design Workshop (AciD 2000), Grenoble, France, January 31- February 1, 2000, 2000
 
(382) Renaudin M., Asynchronous circuits and systems, Invited Talk at International Summer School on Advanced Microelectronics-Grenoble "MIGAS", Autrans, France, June 28 - July 4 2000, 2000
 
(383) Renaudin M., Asynchronous circuits and systems : a promising design alternative, Microelectronic Engineering, Volume 54 , page: 133-149, 2000
 
(384) Renaudin M., Asynchronous logic : a promising design alternative, Invited Tutorial at the XV Conference on Design of Circuits and Integrated Systems (DCIS 2000), Le Corum, Montpellier, France, November 21-24, 2000, 2000
 
(385) Sicard G., Conception d'une rétine analogique/numérique en technologie avancée, Invited Talk at Operation Thématique "Rétines", GDR, March 10, 2000, 2000
 
(386) Rigaud J.B., Renaudin M., Modeling and design/synthesis of arbitration problems , Asynchronous Interfaces : Tools, Techniques and Implementations Workshop (AINT'2000), TU Delft, The Netherlands, July 19-20 2000, 2000
 
(387) Guyot A., Web based exercices on computer arithmetic, Proceedings of the 3rd European Workshop on Microelectonics Education (EWME'2000), Aix-en-Provence, France 18-19 May 2000 , 2000
 
(388) Zimmermann J., Guyot A., Negoi A.C., Bara S., A dedicated circuit for charged particles simulation using the Monte Carlo method, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, June ; 21(2), page: 103-16, 1999
 
(389) Renaudin M., Vivet P., Robin F., A design framework for asynchronous/synchronous circuits based on CHP to HDL translation, Proceedings Fifth International Symposium on Advanced Research in Asynchronous-Circuits and Systems, 1999
 
(390) Robin F., Vivet P., Renaudin M., ASPRO: an asynchronous 16-bit RISC microprocessor with DSP capabilities, ESSCIRC'99. Proceedings of the 25th European Solid State Circuits Conference, 1999
 
(391) Guyot A., Bernal A., Hardware implementation of M-ary modular exponentiation algorithm, XIV Conference on Design of Circuits and Integrated Systems (DCIS'99), Palmas de Mallorca, Spain, 17-20 November 1999, 1999
 
(392) Abou-Samra S.-J., Guyot A., Multiple V dd combinatorial divider without DC to DC converter, ISRN: TIMA-RR--99/04-3--FR, 1999
 
(393) Courtois B., Aisa P.A., Abou-Samra S.-J., Guyot A., 3D CMOS SOI for high performance computing, International Symposium on Low Power Electronics and Design, 1998
 
(394) Bernal A., Guyot A., A new low-power GaAs two-single-port memory cell, IEEE Journal of Solid State Circuits, July ; 33(7), page: 1103-10, 1998
 
(395) Robin F., Renaudin M., Vivet P., ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor, Proceedings. Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems Cat. No.98EX138, 1998
 
(396) Mehrez H., Aberbour M., Houelle A., Guyot A., Vaucher Ch., A time driven adder generator architecture, 9th IFIP International Conference on VLSI, VLSI'97, Gramado, RS, Brazil, 26-29 August 1997, 1998
 
(397) Guyot A., Cours d'opérateurs arithmétiques, , , 1998
 
(398) Bernal A., Guyot A., Design of a modular multiplier based on Montgomery's algorithm, 13th Conference on Design of Circuits and Integrated Systems (DCIS'98) Madrid, Spain, 17-20 November 1998, 1998
 
(399) Bernal A., Guyot A., Hardware for computing modular multiplication algorithm, ESSCIRC '98. Proceedings of the 24th European Solid State Circuits Conference., 1998
 
(400) Abou-Samra S.-J., Guyot A., Low power CMOS digital design, Proceedings of the Tenth International Conference on Microelectronics Cat. No.98EX186, 1998
 
(401) Arweiler J., Guyot A., Abou-Samra S.-J., Low power SOI CMOS multipliers: 2D vs. 3D, ESSCIRC '98. Proceedings of the 24th European Solid State Circuits Conference., 1998
 
(402) Montalvo L.-A., Parhi K.-K., Guyot A., New Svoboda-Tung division, IEEE Transactions on Computers, Sept. ; 47(9), page: 1014-20, 1998
 
(403) Vaucher N., Guyot A., Mehrez H., Houelle A., Aberbour M., On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, March ; 6(1), page: 114-21, 1998
 
(404) Guyot A., Abou-Samra S.-J., Performance/complexity space exploration : Bulk vs. SOI, 8th International Workshop Power and Timing Modeling Optimization and Simulation (PATMOS'98), Copenhagen, Denmark, October 1998, 1998
 
(405) Abou-Samra S.-J., Guyot A., Power consumption in digital circuits, 3rd International Conference on ASIC (ASICON'98), Beijing,China, 20-23 October 1998, 1998
 
(406) Vassileva T., Tchoumatchenko V., Guyot A., Reuse and customisation of parallel prefix adders, International Workshop on IP Based Synthesis and System Design (IWLAS'98), Grenoble, France, 15-16 December 1998, 1998
 
(407) Guyot A., Negoi A.C., Zimmermann J., Bara S., Virtual device : a new approach in microelectronics device education, 2nd European Workshop on Microelectronics Education (EWME'98), Noordwijkerhout, The Netherlands, 14-15 May 1998, 1998
 
(408) Negoi A.C., Guyot A., Zimmermann J., A dedicated circuit for charged particles simulation using the Monte Carlo method, Proceedings. IEEE International Conference-on-Applications Specific Systems, Architectures and Processors. Cat. No.97TB100177. 1997:, 1997
 
(409) Kanan R., Hochet B., Declercq M., Guyot A., A divided decoder-matrix (DDM) structure and its application to a 8 kb GaAs MESFET ROM, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age. ISCAS '97 Cat. No.97CH35987., 1997
 
(410) Guyot A., Kanan R., Hochet B., Declercq M., A low-power high storage capacity structure for GaAs MESFET ROM, Proceedings. International Workshop on Memory Technology, Design and Testing Cat. No.97TB100159., 1997
 
(411) Guyot A., Abou-Samra S.-J., Analytical modelling of spurious transitions in adder circuits , 7th International Workshop Power and Timing Modeling Optimization and Simulation (PATMOS'97), Louvain-la-Neuve, Belgium, September 1997, 1997
 
(412) Robin F., Vivet P., Renaudin M., Asynchronisme et adéquation algorithme architecture, Traitement du Signal, , page: , 1997
 
(413) Vivet P., Robin F., Renaudin M., Asynchronism in a joint algorithm-architecture perspective, Traitement du Signal, 14(6), page: 589-604, 1997
 
(414) Robin F., Privat G., Renaudin M., Asynchronous relaxation of morphological operators: a joint algorithm-architecture perspective, International Journal of Pattern Recognition and Artificial Intelligence, 11(7): Nov., page: 1085-94, 1997
 
(415) Abou-Samra S.-J., Hoefflinger B., Courtois B., Guyot A., Ayache F., Dudek V., Designing with 3D SOI CMOS, Proceedings of the Eighth International Symposium on Silicon on Insulator Technology and Devices, 1997
 
(416) Robin F., Renaudin M., Privat G., Functionally asynchronous VLSI cellular array for morphological filtering of images, Traitement du Signal, 14(6), page: 655-64, 1997
 
(417) Perez Ribas R., Bernal A., Guyot A., GaAs MESFET SRAM using a new high speed memory cell, 5th European Gallium Arsenide and related III-V compounds Applications Symposium (GAAS'97), Bologna, Italy, 3-5 September 1997, 1997
 
(418) Vassileva T., Guyot A., Shishkov V., Tchoumatchenko V., High performance adder's synthesis using efficient macro generator, ECCTD '97. Proceedings of the 1997 European Conference on Circuit Theory and Design., 1997
 
(419) Guyot A., Abou-Samra S.-J., Modeling power consumption in arithmetic operators, Microelectronic Engineering, Dec. ; 39(1-4), page: 245-53, 1997
 
(420) Guyot A., Vaucher Ch., Mehrez H., Houelle A., Aberbour M., Abou-Samra S.-J., Modelling and synthesis of optimal adders under left-to-right input arrival, IFIP International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, France, December1997, 1997
 
(421) Bernal A., Guyot A., Perez Ribas R., New high speed GaAs memory cell, 12th Conference on Design of Integrated Circuits and Systems (DCIS'97) , Sevilla, Spain, November 1997, 1997
 
(422) Bernal A., Guyot A., New two single-port GaAs memory cell, ESSCIRC '97. Proceedings of the 23rd European Solid State Circuits Conference, 1997
 
(423) Coissard V., Guyot A., OCAPI : A coprocessor for infinite precision arithmetic, International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN'97), Lyon, France, September 1997, 1997
 
(424) Laurent B., Guyot A., Abou-Samra S.-J., Spurious transitions in adder circuits: analytical modelling and simulation, VLSI'97, Gramado, Brazil, 26-29 August 1997, 1997
 
(425) Bernal A., Guyot A., Ribas R.P., A low-power differential cross-coupled FET logic for GaAs asynchronous design, GAAS 96. European Gallium Arsenide and Related III V Compounds Applications Symposium and Associated CAD Workshop., 1996
 
(426) Guyot A., Ribas R.P., Bernal A., A low-power enable/disable GaAs MESFET differential logic, 18th Annual GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. Technical Digest 1996 Cat. No.96CH35964, 1996
 
(427) Robin F., Privat G., Renaudin M., An asynchronous 16*16 pixel array-processor for morphological filtering of greyscale images, ESSCIRC '96. Proceedings of the 22nd European Solid State Circuits Conference, 1996
 
(428) El-Hassan B., Guyot A., Renaudin M., A new asynchronous pipeline scheme: application to the design of a self-timed ring divider, IEEE Journal of Solid State Circuits, Volume 31, July, page: 1001 - 1013, 1996
 
(429) Renaudin M., El-Hassan B., Guyot A., Boutamine H., Asynchronous SRT dividers: the real cost, Proceedings. European Design and Test Conference ED&TC 96 Cat. No.96TB100027, 1996
 
(430) Vassileva T., Tchoumatchenko V., Ribas R.P., Guyot A., FPGA design migration: some remarks, Field Programmable Logic. Smart Applications, New Paradigms and Compilers. 6th International Workshop on Field Programmable Logic and Applications, FPL '96 Proceedings., 1996
 
(431) Renaudin M., Robin F., Privat G., Van-Den-Bossche N., Functionally asynchronous array processor for morphological filtering of greyscale images, IEE-Proceedings-Computers-and-Digital-Techniques, 1996
 
(432) Catérini R., Kerckhoeve A., Gourmelon P., Renaudin M., Clarençon D., Fatôme M., Hille B., Ellis E., Boivin E., Real-time spike detection in EEG signals using the wavelet transform and a dedicated digital signal processor card, Journal of Neurosciences Methods, 70(1): Dec., page: 5-14, 1996
 
(433) El-Hassan B., Levering V., Renaudin M., Guyot A., Self timed division and square-root extraction, Proceedings. Ninth International Conference on VLSI Design Cat. No.96TB100010, 1996
 
(434) Robin F., El-Hassan B., Privat G., Renaudin M., A fine-grain asynchronous VLSI cellular array processor architecture, 1995 IEEE Symposium on Circuits and Systems Cat. No.95CH35771, 1995
 
(435) Bederr H., Nicolaidis M., Guyot A., Analytic approach for error masking elimination in on-line multipliers, Proceedings of the 12th Symposium on Computer Arithmetic Cat. No.95CB35822, 1995
 
(436) Houelle A., Montalvo L.-A., Vaucher Ch., Guyot A., Mehrez H., Application of fast layout synthesis environment to dividers evaluation, Proceedings of the 12th Symposium on Computer Arithmetic Cat. No.95CB35822., 1995
 
(437) Houelle A., Guyot A., Vaucher Ch., Mehrez H., Montalvo L.-A., Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers, Proceedings-of-the-8th-International-Conference-on-VLSI-Design-Cat.-No.95TH802. 1995:, 1995
 
(438) Guyot A., Ribas R.P., DCFL- and DPTL-based approaches to self-timed GaAs circuits, ESSCIRC '95. Twenty First European Solid State Circuits Conference. Proceedings., 1995
 
(439) Tchoumatchenko V., Guyot A., Vassileva T., Delay directed adder synthesis and optimization, ECCTD '95 Proceedings of the 12th European Conference on Circuit Theory and Design., 1995
 
(440) Guyot A., Tchoumatchenko V., Vassileva T., Macromodelling of pass-transistor logic circuits, ECCTD '95 Proceedings of the 12th European Conference on Circuit Theory and Design., 1995
 
(441) El-Hassan B., Levering V., Renaudin M., Guyot A., New self-timed rings and their application to division and square root extraction, ESSCIRC '95. Twenty First European Solid State Circuits Conference. Proceedings., 1995
 
(442) Guyot A., Vacher A., Radix-8 butterflies for folded FFT, Proceedings of the Twenty Seventh Southeastern Symposium on System Theory., 1995
 
(443) Guyot A., Skaf A., SAGA: the first general-purpose on-line arithmetic co-processor, Proceedings of the 8th International Conference on VLSI Design Cat. No.95TH802., 1995
 
(444) Vacher A., Guyot A., Spread and folded architectures for FFT, Proceedings of the Twenty Seventh Southeastern Symposium on System Theory., 1995
 
(445) Guyot A., Montalvo L.-A., Svoboda-Tung division with no compensation, Proceedings of the 8th International Conference on VLSI Design Cat. No.95TH802., 1995
 
(446) Skaf A., Muller J.-M., Guyot A., Bajard J.-C., A VLSI circuit for on-line polynomial computing: application to exponential, trigonometric and hyperbolic functions, IFIP Transactions A Computer Science and Technology, A-42, page: 93-100, 1994
 
(447) Skaf A., Rousseau T., Guyot A., Benkhebbab M., Vacher A., A VLSI implementation of parallel fast Fourier transform, Proceedings. The European Design and Test Conference. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design Cat. No.94TH0634 6., 1994
 
(448) Guyot A., Vassileva T., Behnam B., Montalvo L.-A., CMOS implementation of a hybrid radix-4 divider, ESSCIRC '94. Twentieth European Solid State Circuits Conference. Proceedings., 1994
 
(449) Guyot A., Montalvo L.-A., Combinational digit-set converters for hybrid radix-4 arithmetic, Proceedings IEEE International Conference on Computer Design: VLSI in Computers and Processors Cat. No.94CH35712., 1994
 
(450) Bederr H., Nicolaidis M., Guyot A., Design for testability of on-line multipliers, Proceedings 12th IEEE VLSI Test Symposium Cat. No.94TH0645 2., 1994
 
(451) Moussa I., Skaf A., Guyot A., Design of a GaAs redundant divider, IFIP Transactions A Computer Science and Technology, A-42:, page: 63-72, 1994
 
(452) Vacher A., Guyot A., Error-speed compromise for FFT VLSI, Proceedings of the 26th Southeastern Symposium on System Theory Cat. No.94TH0599 1, 1994
 
(453) Guyot A., Mullar J.-M., Skaf A., On-line hardware implementation for complex exponential and logarithm, ESSCIRC '94. Twentieth European Solid State Circuits Conference. Proceedings., 1994
 
(454) El-Hassan B., Renaudin M., The design of fast asynchronous adder structures and their implementation using DCVS logic, 1994 IEEE International Symposium on Circuits and Systems Cat. No.94CH3435 5, 1994
 
(455) Venier P., Renaudin M., Poize M., A general time domain approach for the design of perfect reconstruction modulated filter banks, ICASSP 93. 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing Cat. No.92CH3252 4, 1993
 
(456) Planet P., Privat G., Renaudin M., Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms, : Proceedings.-International-Conference-on-Application-Specific-Array-Processors-Cat.-No.93TH0572-8, 1993
 
(457) Guyot A., Moussa I., Rost P., Design and comparison of GaAs and CMOS redundant divider, ESSCIRC 93. Nineteenth European Solid State Circuits Conference. Proceedings., 1993
 
(458) Bajard J.-C., Skaf A., Muller J.-M., Guyot A., Design of a VLSI circuit for on-line evaluation of several elementary functions using their Taylor expansions, Proceedings.-International-Conference-on-Application-Specific-Array-Processors-Cat.-No.93TH0572-8. 1993:, 1993
 
(459) Betts A., Sicard G., Renaudin M., Johnstone A., Bolsens I., SMILE: a scalable microcontroller library element, Microprocessing and Microprogramming, 39(2-5): Dec., page: 259-62, 1993
 
(460) Skaf A., Guyot A., VLSI design of on-line add/multiply algorithms, Proceedings 1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors Cat. No.93CH3335 7., 1993
 
(461) Venier P., Renaudin M., Poize M., A fast algorithm for lapped nonorthogonal transform: application to the image Gabor transform, Proceedings of the SPIE The International Society for Optical Engineering., 1992
 
(462) Spitz R., Dassaud J.P., Guyot A., Copolymerization propene non-conjugated dienes: derivatization through hydroboration and epoxidation , Proceedings of the American Chemical Society Division of Polymeric Materials - Science and Engineering, Washington, DC, USA, 23-27 August 1992 , 1992
 
(463) Guyot A., Spitz R., Pasquet V., Gomez C., Dassaud J.P., General aspects of activation-deactivation processes with Ziegler-Natta olefin polymerization catalysts , Proceedings of the American Chemical Society Division of Polymeric Materials - Science and Engineering, Washington, DC, USA, 23-27 August 1992 , 1992
 
(464) Kusumaputri-Hornik Y., Guyot A., OCAPI: A prototype for high precision arithmetic, IFIP Transactions A Computer Science and Technology, A-1, page: 11-18, 1992
 
(465) Revillon A., Espiard Ph., Mark J.E., Guyot A., Nucleation of emulsion polymerization in the presence of small silica particles, Proceedings of the American Chemical Society, Spring Meeting, Atlanta, GA, USA, April 15, 1990, 1991
 
(466) Guyot A., OCAPI: architecture of a VLSI coprocessor for the GCD and the extended GCD of large numbers, Proceedings. 10th IEEE Symposium on Computer Arithmetic Cat. No.91CH3015 5., 1991
 
(467) Privat G., Renaudin M., VLSI architectural assessment of standard image coding systems, Annales des Telecommunications, 46(1-2), page: 121-41; Jan.-Feb., 1991
 
(468) Nicolaidis M., Chaumontet G., Guyot A., Courtois B., Castro-Alves V., Gruere Y., Trousson D., Description of a safe programming microprocessing unit for railway signalling, 7th International Conference on Reliability and Maintainability. Proceedings., 1990
 
(469) Ziade H., Guyot A., Conard D., Velazco R., Top down IC failure analysis using an E-beam system coupled to a functional teste, Microelectronic Engineering, May 1990; 12(1-4), page: 113-120, 1990
 
(470) Herreros Y., Muller J.-M., Guyot A., JANUS, an on-line multiplier/divider for manipulating large numbers, Proceedings of 9th Symposium on Computer Arithmetic, 1989
 
(471) Renaudin M., Privat G., Motion estimation VLSI architecture for image coding, Proceedings. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors Cat. No.89CH2794 6., 1989
 
(472) Privat G., Renaudin M., CORDIC-based digital signal processing hardware algorithms, Traitement du Signal, 5(6), page: 421-34, 1988
 
(473) Hochet B., Guyot A., Muller J.-M., A way to build efficient carry-skip adders, IEEE Transactions on Computers, Oct. ; C-36(10), page: 1144-52, 1987
 
(474) Zysman E., Cosnard M., Guyot A., Hochet B., Muller J.-M., Ouaouicha H., Paul P., The FELIN arithmetic coprocessor chip, Proceedings of the 8th Symposium on Computer Arithmetic Cat. No.87CH2419 0, 1987
 
(475) Guyot A., Lux A., Bogo G., Payan C., Mermet J., CASSANDRE and the computer aided logical systems design, Information Processing 71 Proceedings of the IFIP Congress 1971. , 1971