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(1) Vincent L., Lesecq S., Mancini S., Charles H.P., Adaptive Data Prefetching for High Performance Processors, HPES (High Performance Embedded Systems) Workshop at the HIPEAC Conférence, 2015
 
(2) Kaminska B., Stratigopoulos H., Analog and Mixed-Signal Test, Electronic Design Automation for Integrated Circuits , CRC Press, , 2015
 
(3) Mir S., Analog, mixed-signal and MEMS design-for-test and its use for WSN, Invited tutorial talk at Winter School on Wireless Sensor Networs (WSWSN'15), 2015
 
(4) Aktouf C., Fesquet L., Al Khatib Ch., Gana M., A new methodology for implementing a distributed clock management system for low-power design, Workshop on High Performance Embedded Systems (HiPEAC'15), 2015
 
(5) Barragan M., Leger G., A Procedure for Alternate Test Feature Design and Selection , IEEE Design and Test of Computers, 32, page: 18-25, 2015
 
(6) Cherkaoui A., Fischer V., Aubert A., Fesquet L., A Self-timed Ring based True Random Number Generator with Monitoring and Entropy Assessment, University Booth at DATE 2015, 2015
 
(7) Euler R., Mir S., Beznia K., Bounceur A., A tool for analog/RF BIST evaluation using statistical models of circuit parameters, ACM Transactions on Design Automation of Electronic Systems (TODAES), 20, page: Article No. 31 , 2015
 
(8) Bonnaud O., Fesquet L., Communicating and Smart Objects: multidisciplinary topics for the innovative education in microelectronics and its applications, 14th International Conference on Information Technology Based Higher Education and Training (ITHET'15), 2015
 
(9) Gines A., Peralias E., Rueda A., Vazquez D., Barragan M., Doldan R., Fiorelli R., Villegas A., Design of an energy efficient ZigBee transceiver, Mixed-Signal Circuits, CRC Press, , 2015
 
(10) Bidegaray-Fesquet B., Fesquet L., Digital Filtering with non-uniformly sampled data: from the algorithm to the implementation, Event-Based Control and Signal Processing, CRC Press, , 2015
 
(11) Borrione D., Morin-Allory K., Javaheri N., Efficient and Correct by Construction Assertion-Based Synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, PP, page: 1, 2015
 
(12) Stratigopoulos H., Liaperdos J., Tsiatouhas Y., Abdallah L., Li X., Arapoyanni A., Fast Deployment of Alternate Analog Test Using Bayesian Model Fusion, Design, Automation and Test in Europe Conference (DATE'15), 2015
 
(13) Barragan M., Leger G., Feature selection for alternate test using wrappers: application to a LNA case study, Design Automation and Test in Europe Conference (DATE'15), 2015
 
(14) Droniou T., Fei R., Moreau J., Mir S., Marcellin A., Mandier G., Huiss E., Palmigiani G., Vitrou P., Horizontal-FPN fault coverage improvement in production test of CMOS imagers, 33rd IEEE International VLSI Test Symposium (VTS'15), 2015
 
(15) Kieffer Y., Mir S., Euler R., Bounceur A., Bentobache M., Minimizing test frequencies for linear analog circuits: new models and efficient solution methods, VLSI-SoC: At the Crossroads of Emerging Trends, Springer , , 2015
 
(16) Barragan M., Rueda A., Leger G., Vazquez D., On-chip sinusoidal signal generation with harmonic cancelation for analog and mixed-signal BIST applications, Analog Integrated Circuits and Signal Processing, 82, page: 67-79, 2015
 
(17) Pierre L., Runtime Verification of Embedded Systems Requirements throughout the Design Flow, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'2015), 2015
 
(18) Papavramidou P., Nicolaidis M., Test Algorithms for ECC-based Memory Repair in Ultimate CMOS and Post-CMOS, ISRN: TIMA-RR--2015/01--FR, 2015
 
(19) Bonnaud O., Fesquet L., Towards multidisciplinarity for microelectronics education: a strategy of the French national network, International Conference on Microelectronic Systems Education (MSE'15) , 2015
 
(20) Fesquet L., Sicard G., Darwish A., 1-level Crossing Sampling Scheme for Low Data Rate Image Sensors, 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), 2014
 
(21) Evans A., Abstraction techniques for scalable soft error analysis and mitigation, These de Doctorat, 2014
 
(22) Baylac M., Rey S., Rossetto O., Mansour W., Ramos P., Velazco R., Hubert G., Villa F., Accelerator-Based Neutron Irradiation of Integrated Circuits at GENEPI-2 (France), REDW (Radiation Effects Data Workshop) of IEEE NSREC (Nuclear and Space Radiation Effects Conference), 2014
 
(23) Chabot M., Pierre L., A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems, Proc. 26th IFIP International Conference on Testing Software and Systems (ICTSS'2014), 2014
 
(24) Mancini S., Adaptation dynamique en boucle fermée d'un pré-chargement stochastique dans les tableaux , Conférence en Parallélisme, Architecture et Système (COMPAS'14), 2014
 
(25) Qaisar S.-M., Fesquet L., Renaudin M., Adaptive rate filtering a computationally efficient signal processing approach, Signal Processing, 94, page: 620-630 , 2014
 
(26) Pétrot F., Advanced Virtual Prototyping of Multiprocessor SoCs, IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips'14), 2014
 
(27) Papadimitriou A., Beroulle V., Hély D., Maistri P., Leveugle R., A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks, Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, 2014
 
(28) Stratigopoulos H., Barragan M., Alhakim R., Mir S., Dubois M., Analog/RF test problem solving with statistically sampled data, IEEE VLSI Test Symposium (VTS'14), 2014
 
(29) Mir S., Analog/RF test techniques, 14th European Test Symposium, Test Spring School, 2014
 
(30) Leveugle R., Chibani K., Portolan M., Analyse de criticité des registres dans un microprocesseur SPARC, 17èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), 2014
 
(31) Faix M., Mazer E., Fesquet L., An asynchronous CMOS probabilistic computer Idea, 20th International Symposium on Asynchronous Circuits and Systems (ASYNC), Fresh Idea Session, Postdam, Germany, 2014
 
(32) Maistri P., Pontié S., Leveugle R., An Elliptic Curve Crypto-Processor Secured by Randomized Windows, Digital System Design (DSD), 2014 17th Euromicro Conference on, 2014
 
(33) Gascard E., Simeu-Abazi Z., Suiphon B., A Polynomial-Time Algorithm for Diagnosability Verification of Discrete Event Systems, 2nd World Conference on Complex Systems (WCCS'14), 2014
 
(34) Bonnaud O., Fesquet L., A Prospective on Education of New Generations of devices in the FDSOI and FinFET Technologies: from the technological process to the Circuit Design Specifications, 29th Symposium on Microeletronics Technology and Devices (SBMicro'14), 2014
 
(35) Pontié S., Architecture d’un crypto processeur ECC sécurisé contre les attaques physiques, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), 2014
 
(36) Marchand N., Durand S., Zakaria H., Fesquet L., A Robust and Energy-Efficient DVFS Control Algorithm for GALS-ANoC MPSoC in Advanced Technology under Process Variability Constraints , Advances in Computer Science : an International Journal, 3, page: 97-105, 2014
 
(37) Picco A., Goulahsen A., Saadé J., Pétrot F., Huloux J., A Scalable Low Overhead Line Coding For Asynchronous High Speed Serial Transmission, 18th IEEE Workshop on Signal and Power Integrity (SPI'14), Ghent, Belgium, 2014
 
(38) Bel Hadj Amor Z., Pierre L., Borrione D., A Tool for the Automatic TLM-to-RTL Conversion of Embedded Systems Requirements for a Seamless Verification Flow, International Conference on Very Large Scale Integration (VLSI-SoC'14), 2014
 
(39) Alleysson D., Sicard G., Capteurs CMOS à Photosites standard, FR2014/051307, 2014
 
(40) Casset F., Danel J., Renaux Ph., Chappaz C., Le Rhun G., Dieppedale C., Gorisse M., Basrour S., Fanget S., Ancey P., Devos A., Defay E., Characterization and post simulation of thin-film PZT actuated plates for haptic applications, 15th international conference on Thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems (eurosime'14), Ghent, Belgium , 2014
 
(41) Fei R., Mir S., Moreau J., Circuit and method for on-chip testing of a pixel array, , 2014
 
(42) Vincent L., Mancini S., Closed-loop Adaptive and Stochastic Prefetch Mechanism for Data Array, Conference on Design and Architectures for Signal and Image Processing (DASIP'14), 2014
 
(43) Possamai Bastos R., Dutertre J.M., Torres F.S., Comparison of Bulk Built-In Current Sensors in terms of Transient-Fault Detection Sensitivity, European Workshop on CMOS Variability (VARI'14), 2014
 
(44) Bollo M., Maistri P., Composite Fields against Side Channel Analysis for the Advanced Encryption Standard, 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), 2014
 
(45) Ebrahimi M., Evans A., Tahoori M., Seyyedi R., Alexandrescu D., Costenaro E., Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales , Design, Automation & Test in Europe Conference (DATE'14), 2014
 
(46) Schlichtmann U., Kleeberger Veit B., Abraham J., Evans A., Gimmler-Dumont Ch., Glaβ M., Nassif, Sani R. , Herkersdorf A., Wehn N., Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test , Design, Automation & Test in Europe Conference & Exhibition (DATE'14), 2014
 
(47) Michel L., Contributions to Dynamic Binary Translation: instruction parallelism support and optimized translators generator, These de Doctorat, 2014
 
(48) Fesquet L., Morin-Allory K., Robin R., Contrôle autonome d'un nano-drone par caméra externe, 13ème journées pédagogiques du CNFM (JPCNFM), 2014
 
(49) Chibani K., Bergaoui S., Portolan M., Leveugle R., Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options, IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014
 
(50) Pierre L., Chabot M., Customization of the Runtime Verification of Hardware Software Virtual Platforms in ISIS, Forum on specification & Design Languages (FDL'2014), 2014
 
(51) Zhou Z., Wong M., Rufer L., Damped Aero-Acoustic Microphone with Improved High-Frequency Characteristics, Journal of Microelectromechanical Systems, 23, page: 1094 - 1100 , 2014
 
(52) Mir S., Fei R., Moreau J., Défauts catastrophiques dans les capteurs optiques CMOS 1T75 PIN photodiode, Journées GDR ondes, 2014
 
(53) Roa G., Le Pelleter T., Bonvilain A., Chagoya A., Fesquet L., Designing ultra-low power systems with non-uniform sampling and event-driven logic, 27th Symposium on Integrated Circuits and Systems Design (SBCCI'14), 2014
 
(54) Maistri P., Pontié S., Design of a secure architecture for scalar multiplication on elliptic curves, 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME'14), 2014
 
(55) Dutertre J.M., Possamai Bastos R., Potin O., Flottes M.-L., Rouzeyre B., Di Natale G., Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts, Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'14), 2014
 
(56) Chefi A., Design of Low Power CMOS Image Sensor for Wireless Sensor Networks, These de Doctorat, 2014
 
(57) Morin-Allory K., Javaheri N., Borrione D., Design Understanding with Fast Prototyping from Assertions, Workshop on Design Automation for Understanding Hardware Designs (Friday Workshop DATE'14), Dresden (Germany), 2014
 
(58) Aupetit C., Chevalier C., Fesquet L., Al Khatib Ch., Sicard G., Chagoya A., Distributed Asynchronous Controllers for Clock Management in Low Power Systems, 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), 2014
 
(59) Nicolaidis M., Double-sampling Achitectures, IEEE International Reliability Physics Symposium (IRPS'14), 2014
 
(60) Gang Yi, Anghel L., Benabdenbi M., Dimopoulos M., Efficient Fault-Tolerant Adaptive Routing under an unconstrained Set of Node and Link Failures for Many Cores System On Chip, Workshop on Dependable Multicore and Transactional Memory Systems (DMTM'14), (joint to HIPEAC event), 2014
 
(61) Sunter S., Stratigopoulos H., Efficient Monte Carlo-Based Analog Parametric Fault Modelling, IEEE VLSI Test Symposium, Napa, CA, USA, 2014
 
(62) Alhakim R., Simeu E., Efficient tracking design in UWB communication systems , IEEE International Conference on Ultra-Wideband (ICUWB'14), 2014
 
(63) Bossuet L., Fischer V., Aubert A., Maistri P., Maurine P., Robisson B., Dutertre J.M., Lisart M., Moro N., Leveugle R., Electromagnetic analysis and fault injection onto secure circuits, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), 2014
 
(64) Alberto D., Maistri P., Leveugle R., Electromagnetic attacks on embedded devices: a model of probe-circuit power coupling, 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14), 2014
 
(65) Nicolaidis M., Emergence of Euclidian Geometry in a Computational Universe, 50th AISB Convention, 2014
 
(66) Nicolaidis M., Emergence of Euclidian Geometry in a Computational Universe, ISRN: , 2014
 
(67) Bousquet L., Enriched high level model generation for heterogeneous and multiphysic systems, These de Doctorat, 2014
 
(68) Ekobo Akoa B., Error detection and concealment integrated in a video decoder using technics of statistical analysis, These de Doctorat, 2014
 
(69) Dubois M., Stratigopoulos H., Mir S., Barragan M., Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs , IFIP/IEEE 22nd International Conference on Very Large Scale Integration (VLSI-SoC'14), 2014
 
(70) Clemente J.A., Velazco R., Hubert G., Mansour W., Palomar C., Franco F., Baylac M., Rey S., Villa F., Rossetto O., Evidences of the robustness of a COTS soft-error free SRAM to neutron radiation, IEEE Nuclear and Space Radiation Effects Conference (NSREC'14), 2014
 
(71) Naimi A., Bonvilain A., Expérimentations de microjauges de déformation réalisées par microfabrication sur des aiguilles médicales, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14) , 2014
 
(72) Toczek T., Mathieu Y., Larabi Z., Mancini S., Pierrefeu L., Exploration of 3D grid caching strategies for ray-shooting, Journal of Real Time Image Processing, 7, page: 3-19, 2014
 
(73) Chibani K., Ben Jrad M., Portolan M., Leveugle R., Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), 2014
 
(74) Prost-Boucle A., Fast hardware accelerator generation using high-level synthesis under resource constraints, These de Doctorat, 2014
 
(75) Stratigopoulos H., Sunter S., Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics, 1st Workshop on Statistical Test Methods (Fringe event to ETS 2014) , 2014
 
(76) Sunter S., Stratigopoulos H., Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33, page: 1977 - 1990 , 2014
 
(77) Borrione D., Fast Prototyping from Assertions, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH 2014), Ottawa, Canada, 2014
 
(78) Chibani K., Portolan M., Leveugle R., Fast register criticality evaluation in a SPARC microprocessor, 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME'14), 2014
 
(79) Anghel L., Gang Yi, Dimopoulos M., Nicolaidis M., Zergainoh N.-E., Benabdenbi M., Fault-Tolerant Adaptive Routing under an Unconstrained Set of Node and Link Failures for Many-Core Systems-on-Chip, Microprocessors and Microsystems, 38, page: 620–635, 2014
 
(80) Barragan M., Leger G., Feature selection for Alternate Test using wrappers: application to an RF LNA case study, 1st Workshop on Statistical Test Methods (STEM'14), Paderborn, Germany, 2014
 
(81) Bonnaud O., Nouet P., Fesquet L., Tayeb M.-B, FINMINA: a French national project to promote Innovation in Higher Education in Microelectronics and Nanotechnologies, International Conference on Information Technology Based Higher Education and Training (ITHET'14), 2014
 
(82) Gangneron M., Bonvilain A., First experimentations of microsensors microfabricated on a long and thin medical needle, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 14), Cannes, France, 2014
 
(83) Papavramidou P., Hély D., Beroulle V., Maistri P., Leveugle R., FPGA emulation of laser attacks against secure deep submicron integrated circuits, Second Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'14), 2014
 
(84) Basrour S., Colin M., Générateur implantable à poutre piézoélectrique, 14/54616, 2014
 
(85) Bernard F., Chappaz C., Basrour S., Génération d'’un interposeur pour surface tactile vibrante pour rendu haptique, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14) , 2014
 
(86) Sicard G., Chefi A., Soudani A., Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs, AEU - International Journal of Electronics and Communications, 68, March, page: 193-200, 2014
 
(87) Bergaoui S., Vanhauwaert P., Leveugle R., IDSM: an improved disjoint signature monitoring scheme for processor behavioral checking, 15th Latin-American Test Workshop (LATW'14), 2014
 
(88) Bonnaud O., Salaün A-C, Bsiesy Ah., Fesquet L., Improvement of doctoral studies in Electrical and Information Engineering through the High level courses in Europe, 25th EAEEIE Annual Conference, 2014
 
(89) Flottes M.-L., Rouzeyre B., Di Natale G., Sarafianos A., Dutertre J.M., Possamai Bastos R., Potin O., Improving the ability of Bulk Built-In Current Sensors to detect SEEs by using triple-well CMOS, Microelectronics Reliability, 54, page: 2289–2294, 2014
 
(90) Ganapathy S., Canal R., Alexandrescu D., Costenaro E., Gonzales A., Rubio A., INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis , Design, Automation & Test in Europe Conference & Exhibition (DATE'14), 2014
 
(91) Rufer L., Koumela A., Zhou Z., Wong M., Ollivier S., Salze E., Yuldashev P., Basrour S., Large band MEMS microphone for high frequency acoustic applications in air (10 kHz -1MHz), 12th Congrès Français d’Acoustique, Poitiers, France, 2014
 
(92) Candelier P., Tavernier C., Leveugle R., Maistri P., Vanhauwaert P., Lu F., Di Natale G., Flottes M.-L., Rouzeyre B., Papadimitriou A., Hély D., Beroulle V., Hubert G., De Castro S., Dutertre J.M., Sarafianos A., Boher N., Lisart M., Damiens J., Laser-induced fault effects in security-dedicated circuit, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), 2014
 
(93) Xu Yan, Lightweight Software Services for Dynamic Partial Reconfiguration of FPGAs, These de Doctorat, 2014
 
(94) Abbas H., Local adaptive control in a sensor CMOS vision, These de Doctorat, 2014
 
(95) Serhan A., Abdallah L., Stratigopoulos H., Mir S., Low-cost EVM built-in test of RF transceivers, 9th IEEE International Design and Test Symposium (IDT'14), 2014
 
(96) Sicard G., Fesquet L., Darwish A., Low data rate architecture for smart image sensor , Image Sensors and Imaging Systems, San Francisco, California, USA, 2014
 
(97) Tu C., Zhu H., Rufer L., Lee J., Low Impedance Very-High-Frequency (VHF) Band Thermal Piezoresistive Silicon Bulk Acoustic Resonator, The 7th Asia-Pacific Conference on Transducers and Micro/Nano Technologies (APCOT'14), 2014
 
(98) Bhasin S., Maistri P., Regazzoni F., Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch, International Symposium on Electromagnetic Compatibility (EMC 2014), Raleigh Convention Center Raleigh, NC, USA, 2014
 
(99) Papavramidou P., Memory Repair Architectures for High Defect Densities , These de Doctorat, 2014
 
(100) Muller O., Rousseau F., Ghiti A., Bourge A., Méthode de sélection de checkpoint matériel avec outil de synthèse de haut niveau , Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), 2014
 
(101) Alexandrescu D., Evans A., Costenaro E., Minimization of SER-Induced Costs through Linear Programming, The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), 2014
 
(102) Darwish A., Fesquet L., Beyrouthy T., Bidegaray-Fesquet B., Le Pelleter T., Mitigating the data-deluge by an adequate sampling for low-power systems, 5th International Conference on Computational Harmonic Analysis, 2014
 
(103) Anghel L., New Approaches in Soft Errors Fault Tolerant Design for digital circuits based on Double Sampling Techniques, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH 2014), Ottawa, Canada, 2014
 
(104) Saliva M., Cacho F., Angot D., Durand M., Parra M., Bravaix A. , Huard V., Federspiel X., Blanc-Benon P., Anghel L., New Insight about Oxide Breakdown Occurrence at Circuit Level, IEEE International Reliability Physics Symposium (IRPS'14), 2014
 
(105) Lagraa S., New MPSoC profiling tools based on data mining techniques , These de Doctorat, 2014
 
(106) Ferlet-Cavrois V., Nicolaidis M., Alexandrescu D., Evans A., New Techniques for SET Sensitivity and Propagation Measurement in Flash-Based FPGAs, Nuclear and Space Radiation Effects Conference (NSREC'14), 2014
 
(107) Stratigopoulos H., De Foucauld E., Mir S., Dimakos A., Siligaris A., Non-intrusive built-in test for 65nm RF LNA , IEEE International Mixed-signals, Sensors and Systems Test Workshop (IMS3TW'14), 2014
 
(108) Barragan M., Renaud G., Mir S., On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test , 23rd IEEE Asian Test Symposium (ATS'14), 2014
 
(109) Vanhauwaert P., Papadimitriou A., Hély D., Maistri P., Leveugle R., Beroulle V., On error models for RTL security evaluations, 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14), 2014
 
(110) Andraud M., Simeu E., Stratigopoulos H., One-shot calibration of RF circuits based on non-intrusive sensors, Design Automation Conference, San Francisco, CA, USA, 2014
 
(111) Pecheux F., Benabdenbi M., Greiner A., Refauvelet D., Zhang Z., On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22, page: 1364 - 1376 , 2014
 
(112) Schwambach V., Mancini S., Cleyet-Merle S., Issard A., Optimisation de performance au niveau applicatif: étude de cas de vision embarquée sur STHORM , Conférence en Parallélisme, Architecture et Système (COMPAS'14), 2014
 
(113) Pierre L., Outils de démonstration automatique et preuve de circuits électroniques, Forum Méthodes Formelles "Preuve de modèle, preuve de programme" (Aerospace Valley - Minalogic) Toulouse, France, 2014
 
(114) Gascard E., Suiphon B., Simeu-Abazi Z., Premiers pas vers le diagnostic de défaillances par exploitation d'un modèle, 19e Congrès de Maîtrise des Risques et Sûreté de Fonctionnement (LambdaMu 19), 2014
 
(115) Ancey P., Basrour S., Monfray S., Muralt P., Skotnicki T., Trioux E., Procédé de fabrication de lamelles bistables de courbures différentes, 14/51833, 2014
 
(116) Simeu-Abazi Z., Di Mascolo M., Gascard E., Queuing Network-based methodology for designing and assessing performance of centralized maintenance workshops, Journal of Manufacturing Technology Management, 25, page: , 2014
 
(117) Pontié S., Maistri P., Randomized Windows for a Secure Crypto-Processor on Elliptic Curves, 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2014), 2014
 
(118) Gomez D., Abdallah L., Mir S., Aldrete-Vidrio E., Dilhaire S., Martineau B., Perpinà X., Stratigopoulos H., Jordà X., Silva-Martinez J., Aragonès X., Altet J., Vellvehi M., Mateo D., Onabajo M., Gonzalez J.L., Reverter F., Review of temperature sensors as monitors for RF mmW built-in testing and self-calibration schemes, 57th IEEE Midwest Symposium on Circuits and Systems (MWSCAS'14), 2014
 
(119) Stratigopoulos H., RF Built-In Test with Non-Intrusive Sensors, IEEE VLSI Test Symposium (VTS'14), 2014
 
(120) Cherkaoui A., Ring oscillator based true random number generators , These de Doctorat, 2014
 
(121) Pétrot F., Termier A., Lagraa S., Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces, Best Paper Award in Design Automation and Test in Europe (DATE'14), Dresden, Germany, 2014
 
(122) Cherkaoui A., Fesquet L., Elissati O., Self-timed rings as low-phase noise programmable oscillators, 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), 2014
 
(123) Velazco R., Ramos P., Mansour W., Ayoubi R., SEU fault-injection at system level: method, tools and preliminary results, Latin American Test Workshop (LATW), Fortaleza, Brazil, 2014
 
(124) Sicard G., Abbas H., Chefi A., Amhaz H., Simple intra-pixel interaction for smart CMOS image sensors, 14th International Workshop on the Cellular Nanoscale Networks and their Applications (CNNA'14), 2014
 
(125) Sarrazin G., Pétrot F., Fournel N., Gerin P., Simulation native de systèmes many-cœurs pouvant avoir des caractéristiques architecturales non génériques, Conférence d’informatique en Parallélisme (COMPAS'14), Architecture et Système, 2014
 
(126) Anghel L., Savulimedu Veeravalli V., Alexandrescu D., Steininger A., Schneider-Hornstein K., Costenaro E., Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum, The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), 2014
 
(127) Andraud M., Deluthault A., Dieng M., Azais F., Bernard S., Cauvet P., Comte M., Kervaon T., Kerzerho V., Mir S., Pugliesi-Conti P., Renovell M., Soulier F., Simeu E., Stratigopoulos H., Solutions for the self-adaptation of communicating systems in operation, IEEE International On-line Test Symposium (IOLTS'14), 2014
 
(128) Pétrot F., Some Design Issues for 3D NoCs : From Circuits to Systems, Keynote in 8th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'14), 2014
 
(129) Chefi A., Sicard G., SPIHT-based image compression scheme for energy conservation over Wireless Vision Sensor Networks, 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), 2014
 
(130) Costa-Marques G., Study of ....., These de Doctorat, 2014
 
(131) Costenaro E., Gaillard R., Cawley J., Alexandrescu D., Evans A., Lauzeral O., Supply Chain Management for Reliability: Identifying SER-critical components in a large system-Bill Of Material, IEEE International Reliability Innovations Conference (IRIC'14), 2014
 
(132) Bel Hadj Amor Z., Pierre L., Borrione D., System-on-Chip Verification: TLM-to-RTL Assertions Transformation, 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME'14), Grenoble, France, 2014
 
(133) Souari A., Thibeault Cl., Blaquière Y., Velazco R., Towards a realistic SEU effects emulation on SRAM Based FPGAs, IEEE Nuclear and Space Radiation Effects Conference (NSREC '14), 2014
 
(134) Pétrot F., Traces non intrusives : un outil d'analyse du logiciel et du matériel pour les MPSoCs, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH 2014), Ottawa, Canada, 2014
 
(135) Mir S., Trends in mixed-signal test cost in current and future ICs, Panel moderator at 19th IEEE International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW'14), 2014
 
(136) Bonnaud O., Fesquet L., Trends in Nanoelectronic Education: From FDSOI and FinFET Technologies to Circuit Design Specifications, The 10th European Workshop on Microelectronics Education (EWME 2014), 2014
 
(137) Ekobo Akoa B., Lebowsky F., Simeu E., Using statistical analysis and artificial intelligence tools for automatic assessment of video sequences, Color Imaging XIX: Displaying, Processing, Hardcopy, and Applications, 2014
 
(138) Bel Hadj Amor Z., Validation of complex systems on a chip, from TLM level to RTL, These de Doctorat, 2014
 
(139) Flottes M.-L., Di Natale G., Rouzeyre B., Torres F.S., Dutertre J.M., Possamai Bastos R., A Bulk Built-in Sensor for Detection of Fault Attacks, International Symposium on Hardware Oriented Security and Trust (HOST'13), Austin, TX, USA, 2013
 
(140) Sicard G., Abbas H., Amhaz H., Zimouche H., Rolland R., A CMOS HDR Imager with an Analog Local Adaptation, International Image Sensor Workshop (IISW’13), Snowbird, USA, 2013
 
(141) Sicard G., Chefi A., Soudani A., A CMOS Image Sensor with Low-Complexity Video Compression for Wireless Sensor Networks, International New Circuits and Systems Conference (NEWCAS’13), Paris, France, 2013
 
(142) Rousseau F., Fresse V., Tan J., Adaptive NoC-Based MPSoC System for Spectral Imaging Algorithm Dedicated to Art Authentication, 21st European Signal Processing Conference (EUSIPCO 2013), Marrakech, Morocco, 2013
 
(143) Nicolaidis M., ADDA: Adaptive Double-sampling Architecture for Highly Flexible Robust Design, Design Automation and Test in Europe Conference (DATE'13), Grenoble, France, 2013
 
(144) Rehman Saif-Ur, Ben Dhia A., Blanchardon A., Naviner L., Benabdenbi M., Chotin-Avot R., Mehrez H., Amouri E., Marrakchi Z., A defect-tolerant cluster in a mesh SRAM-based FPGA, International Conference on Field-Programmable Technology (ICFPT'13), Kyoto, Japan, 2013
 
(145) Akesson B., Goossens G., Pétrot F., Foroutan S., A General Framework for Average-Case Performance Analysis of Shared Resources, Euromicro Conference on Digital System Design (DSD'13), Santander, Spain , 2013
 
(146) Dubois F., A machine-learning based methodology to design analytical area and power models of highly parametric networks-on-chip, These de Doctorat, 2013
 
(147) Hedde D., Analyse, These de Doctorat, 2013
 
(148) Fesquet L., Beyrouthy T., An asynchronous FPGA block with its tech-mapping algorithm dedicated to security applications, International Journal of Reconfigurable Computing, 2013, Article ID 517947, page: 12 pages, 2013
 
(149) Velazco R., Mansour W., An Automated SEU Fault-Injection Method and Tool for HDL-Based Designs , IEEE Transactions on Nuclear Science, 60, page: 2728 - 2733 , 2013
 
(150) Pétrot F., Horrein P.-H, Hennebert Ch., An environment for (re)configuration and execution management of heterogeneous flexible radio platforms, Microprocessors and Microsystems, 37, page: 701-712, 2013
 
(151) Tiran S., Maurine P., Koren I., Leveugle R., Maistri P., An evaluation of an AES implementation protected against EM analysis, 23rd ACM international conference on Great lakes symposium on VLSI (GLSVLSI'13), Paris, France, 2013
 
(152) Possamai Bastos R., Rouzeyre B., Lu F., Flottes M.-L., Di Natale G., A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic, JETTA - Journal of Electronic Testing: Theory and Application, 29, page: 331-340, 2013
 
(153) Thonnard Y., Pétrot F., Foroutan S., An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip, IEEE Transactions on Computers, 62, page: 1641-1655, 2013
 
(154) Alhakim R., Simeu E., Raoof K., A novel design for delay-locked loop using internal model control approach, Journées scientifiques du projet SEmba 2013, Lyon, France, 2013
 
(155) Rufer L., Colin M., Basrour S., Application driven design, fabrication and characterization of piezoelectric energy scavenger for cardiac pacemakers, Joint UFFC, EFTF and PFM Symposium, International Symposium on the Applications of Ferroelectrics – Piezoresponse Force Microscopy Workshop, Prague, Czech Republic, 2013
 
(156) Alexandrescu D., Nicolaidis M., Belhaddad K., Costenaro E., A Practical Approach to Single Event Transient Analysis For Highly Complex Design, JETTA - Journal of Electronic Testing: Theory and Application, 29, June, page: 301-315, 2013
 
(157) Rohani A., Kerkhoff H., Costenaro E., Alexandrescu D., A Pulse-Length Determination Techniques for the SET Fault Model, First RIIF Workshop, 2013
 
(158) Bahmani M., Architectural exploration and performance analysis of Vertically-Partially-Connected Mesh-based 3D-NoC , These de Doctorat, 2013
 
(159) Aubert A., Fesquet L., Cherkaoui A., Fischer V., A Self-timed Ring Based True Random Number Generator, 19th International Symposium on Asynchronous Circuits and Systems (ASYNC'13), Santa Monica, USA, 2013
 
(160) Possamai Bastos R., Torres F.S., Flottes M.-L., Dutertre J.M., Di Natale G., Rouzeyre B., A Single Built-in Sensor to Check Pull-up and Pull-down CMOS Networks against Transient Faults, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'13), Karlsruhe, Germany, 2013
 
(161) Pierre L., Assertion-Based Verification for the validation and safety analysis of hardware/software systems on chip, TORRENTS Working day (RTRA Sciences et Technologies pour l'Aéronautique et l'Espace) Toulouse, France, 2013
 
(162) Evans A., Nicolaidis M., Costenaro E., Alexandrescu D., A Standards Based Approach to the Reliability Specification of IP Components, 2nd Workshop on Manufacturable and Dependable, Multicore Architectures at Nanoscale (MEDIAN'13), Avignon, France, 2013
 
(163) Saadé J., Pétrot F., Picco A., Huloux J., Goulahsen A., A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0, Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Karlovy Vary, Czech Republic, 2013
 
(164) Ben Jrad M., Leveugle R., Automated design flow for no-cost configuration error detection in SRAM-based FPGAs, International Conference on ReConFigurable Computing and FPGAs (ReConFig' 13), Cancun, Mexico, 2013
 
(165) Fournel N., Michel L., Pétrot F., Automated generation of efficient instruction decoders for instruction set simulators, Conference on Computer Aided Design (ICCAD'13), San Jose, CA, USA, 2013
 
(166) Borrione D., Javaheri N., Morin-Allory K., Porcher A., Automatic Prototyping of declarative properties on FPGA, Electronic System Level Synthesis Conference (ESLsyn 2013), Austin, Texas, USA, 2013
 
(167) Pierre L., Bel Hadj Amor Z., Automatic Refinement of Requirements for Verification throughout the SoC Design Flow, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'13), Embedded Syst Week), Montreal (Canada), 2013
 
(168) Cherkaoui A., Aubert A., Fischer V., Fesquet L., A Very High Speed True Random Number Generator with Entropy Assessment, Workshop on Cryptographic Hardware and Embedded Systems (CHES'2013), Santa Barbara, California, USA, 2013
 
(169) Bergaoui S., Behavioral monitoring for embedded systems and software by disjoint signature analysis, These de Doctorat, 2013
 
(170) Rehman Saif-Ur, Anghel L., Benabdenbi M., BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), NY, USA, 2013
 
(171) Fei R., Moreau J., Mir S., BIST of interconnection lines in the pixel matrix of CMOS imagers, 5th International Workshop on Advances in Sensors and Interfaces (IWASI), Bari, Italy, 2013
 
(172) Rufer L., Salze E., Yuldashev P., Ollivier S., Wong M., Zhou Z., Bulk micro-machined wide-band aero-acoustic microphone and its application to acoustic ranging , Journal of Micromechanics and Microengineering, 23, page: 10, 2013
 
(173) Velazco R., Cheminet A., Hubert G., Lacoste V., Boscher D., Characterization of the Neutron Environment and SEE Investigations at the CERN-EU High Energy Reference Field and at the Pic du Midi , IEEE Transactions on Nuclear Science, 60, August, page: 2411-2417, 2013
 
(174) Evans A., Nicolaidis M., Wen S.J., Rocha De Assis T., Clustering Techniques and Statistical Fault Injection for Selective Mitigation of SEUs in Flip-Flops, International Symposium on Quality Electronic Design (ISQED), Santa Clara, California, USA, 2013
 
(175) Esteves J., CMOS-MEMS technology for acoustic apllications, These de Doctorat, 2013
 
(176) Rufer L., Esteves J., Basrour S., Ekeom D., CMOS-MEMS technology with front-end surface etching of sacrificial SiO2 dedicated for acoustic devices, International Workshop on Advances in Sensors and Interfaces (IWASI’13), Bari, Italy, 2013
 
(177) Pineda F., Hubert G., Velazco R., Federico C.A., Cheminet A., Silva Cardenas C., Caldas L.V., Pancher F., Lacoste V., Palumbo F., Mansour W., Artola L., Duzellier S., Continuous High-Altitude Measurements of Cosmic Ray Neutrons and SEU/MCU at Various Locations: Correlation and Analyses Based-On MUSCA SEP, IEEE Transactions on Nuclear Science, 60, August, page: 2418-2426, 2013
 
(178) Chaix F., Contributions for late CMOS many-cores processors: NoC fault-tolerant routing and auto-adaptive applications, These de Doctorat, 2013
 
(179) Soudani A., Sicard G., Chefi A., Contribution to the design of a CMOS Image Sensor with Low-Complexity Video Compression for Wireless Sensor Networks, Journal of Systems Architecture (JSA), 59, page: 818-825, 2013
 
(180) Pétrot F., Foroutan S., Sheibanyrad H., Cost-Efficient Buffer Sizing in Shared-Memory 3D-MPSoCs Using Wide I/O Interfaces, 5th Design for 3D Silicon Integration Workshop, Grenoble, France, 2013
 
(181) Rehman Saif-Ur, Benabdenbi M., Anghel L., Cost-efficient Testing of LUT and Intra-cluster Interconnect of a Novel SRAM-based FPGA, Colloque National System-On-Chip System-In-Package (SoC-SiP'13), 2013
 
(182) Maistri P., Tiran S., Maurine P., Koren I., Leveugle R., Countermeasures against EM analysis for a secured FPGA-based AES implementation, International Conference on ReConFigurable Computing and FPGAs (ReConFig' 13), Cancun, Mexico, 2013
 
(183) Simeu E., Serrestou Y., Raoof K., Alhakim R., Cramer-Rao lower bounds and maximum likelihood timing synchronization for dirty template UWB communications , Signal Image and Video Processing Journal, 7, July, page: 741-757, 2013
 
(184) Pétrot F., Termier A., Lagraa S., Data Mining MPSoC Simulation Traces to Identify Concurrent Memory Access Patterns, Design Automation and Test in Europe Conference (DATE), Grenoble, France, 2013
 
(185) Stratigopoulos H., Mir S., Altet J., Abdallah L., Defect-Oriented Non-Intrusive RF Test Using On-Chip Temperature Sensors, IEEE VLSI Test Symposium (VTS'13), Berkeley, CA, USA, 2013
 
(186) Basrour S., Rufer L., Colin M., Design, fabrication and characterization of a very low frequency piezoelectric energy harvester designed for heart beat vibration scavenging, Smart Sensors, Actuators, and MEMS Conference, SPIE Microtechnologies, Grenoble, France, 2013
 
(187) Laraba A., Design-For-Test of pipeline Analog-to-Digital Converters, These de Doctorat, 2013
 
(188) Chabanet S., Pétrot F., Lambelin S., Rahmouni K., Design of a medium voltage protection device using system simulation approaches: a case study, IJES - International Journal of Embedded Systems , 5, page: 53-66, 2013
 
(189) Mancini S., Rousseau F., Lavagno L., Butt S., Design of a pseudo-log image transform IP in an HLS-based memory management framework, Conference of Real-Time Image and Video Processing 2013, Burlingame, California, USA, 2013
 
(190) Bergaoui S., Wecxsteen A., Leveugle R., Detailed analysis of compilation options for robust software-based embedded systems, JETTA - Journal of Electronic Testing: Theory and Application, 29, April, page: 211-222, 2013
 
(191) Possamai Bastos R., Torres F.S., Detection of Transient Faults in Nanometer Technologies by using Modular Built-In Current Sensors, Journal of Integrated Circuits and Systems, 8, page: 89-97, 2013
 
(192) Alhakim R., Raoof K., Simeu E., Detection of UWB signal using dirty template approach, Signal Image and Video Processing Journal, October, page: 1-15, 2013
 
(193) Pasca V., Development of HW / SW Fault-Tolerant and Self-Configurable Architectures for 3D Integration Technologies, These de Doctorat, 2013
 
(194) Rufer L., Le Boulbar E., Edwards M.J., Allsopp D.W.E., Bowen C.R., Vittoz S., Vanko G., Brinkfeldt K., Lalinsky T., Johander P., Effect of bias conditions on pressure sensors based on AlGaN/GaN High Electron Mobility Transistor, Sensors and Actuators A : Physical, 194, May, page: 247–251, 2013
 
(195) Bentobache M., Bounceur A., Mir S., Euler R., Kieffer Y., Efficient minimization of test frequencies for linear analog circuits, 13th IEEE European Test Symposium (ETS'13), Avignon, France, 2013
 
(196) Gascard E., Mayol G., Simeu-Abazi Z., Elaboration du comportement dynamique d'un système pour le diagnostic des défaillances, Congrès International de Génie Industriel (CIGI'13), La Rochelle, France, 2013
 
(197) Pétrot F., Sheibanyrad H., Bahmani M., Dubois F., Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs, IEEE Transactions on Computers, 62, page: 609-615, 2013
 
(198) Sliwinski P., Berezowski K., Wachel P., Sicard G., Fesquet L., Empirical recovery of input nonlinearity in distributed element models, International Workshop on Adaptation and Learning in Control and Signal Processing (ALCOSP'13), Caen, France, 2013
 
(199) Bousquet L., Energy Consumption Information in High-level Models, PhD Forum at IEEE Design, Automation and Test in Europe Conference (DATE'13), Grenoble, 2013
 
(200) Pontarelli S., Ottavi M., Evans A., Wen S.J., Error detection in Ternary CAMs using Bloom Filters , Design Automation and Test in Europe Conference (DATE'13), 2013
 
(201) Velazco R., Hubert G., Mansour W., Error-Rate Estimation Combining SEE Static Cross-Section Predictions and Fault-Injections Performed on HDL-Based Designs, IEEE Transactions on Nuclear Science, 60, December, page: 4238-4242, 2013
 
(202) Velazco R., Error-rate prediction for programmable circuits: methodology, tools and studied cases , SPIE Micro- and Nanotechnology Sensors, Systems, and Applications, Baltimore (USA), 2013
 
(203) Euler R., Mir S., Beznia K., Bounceur A., Estimation des métriques de test analogique à base d’un échantillon multivarié de circuits extrêmes, 16ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'13), Grenoble, France, 2013
 
(204) Ben Jrad M., Leveugle R., Evaluating a low cost robustness improvement in SRAM-based FPGAs, IEEE International On-Line Testing symposium (IOLTS'13), Chania, Crete, Greece, 2013
 
(205) Santini T., Houssany S., Guibbaud N., Bougerol A. , Leveugle R., Miller F., Experimental assessment of cache memory soft error rate prediction technique, IEEE Transactions on Nuclear Science, 60, page: 2734-2741, 2013
 
(206) Prost-Boucle A., Rousseau F., Muller O., Fast and Autonomous HLS Methodology for Hardware Accelerator Generation Under Resource Constraints, Euromicro Conference on Digital System Design (DSD'13), Santander, Spain, 2013
 
(207) Muller O., Prost-Boucle A., Rousseau F., Fast and Standalone Design Space Exploration for High-Level Synthesis under Resource Constraints, Journal of Systems Architecture (JSA), online le 5 nov. 2013, page: , 2013
 
(208) Morin-Allory K., Javaheri N., Borrione D., Fast Prototyping from Assertions: a Pragmatic Approach, 11th ACM-IEEE International Conference on "Formal Methods and Models for Codesign (MEMOCODE 2013), Portland , Oregon, USA, 2013
 
(209) Alhakim R., Simeu E., Fast-tracking delay-locked loop for UWB communication systems , International Conference on Microelectronics (ICM'13), 2013
 
(210) Huang K., Stratigopoulos H., Mir S., Fault modeling and diagnosis for nanometric analog circuits, IEEE International Test Conference (ITC'13), Anaheim, CA, USA, 2013
 
(211) Velazco R., Ayoubi R., El Falou W., Ziade H., Mansour W., Fault-tolerance capabilities of a software-implemented Hopfield Neural Network, 3rd International Conference on Communications and Information Technology (ICCIT 2013), Beirut, Lebanon, 2013
 
(212) Dimopoulos M., Benabdenbi M., Anghel L., Zergainoh N.-E., Nicolaidis M., Gang Yi, Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip , IEEE International On-Line Testing symposium (IOLTS'13), Chania, Crete, Greece, 2013
 
(213) Fall D., Fault tolerant techniques for the design of reliable circuits in advanved process nodes, These de Doctorat, 2013
 
(214) Alcântara O., Fresse V., Rousseau F., FlexOE: A Congestion-Aware Routing Algorithm for NoCs, International Symposium on Rapid System Prototyping (RSP'13), Montréal, Canada, 2013
 
(215) Maistri P., Leveugle R., Alberto D., Forecasting the effects of electromagnetic fault injections on embedded cryptosystems, Information Security Journal: A Global Perspective, 22, page: pp, 2013
 
(216) Rousseau F., Jaber M., Chagoya-Garzon A., From System Model Formalization Towards Correct and Efficient HW/SW Design, 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Abu Dhabi, UAE, 2013
 
(217) Costenaro E., Alexandrescu D., Chen Liang, Evans A., Hierarchical RTL-based combinatorial SER estimation, IEEE International On-Line Testing symposium (IOLTS'13), Chania, Crete, Greece, 2013
 
(218) Zhou Z., High Frequency MEMS Sensor for Aero-acoustic Measurements, These de Doctorat, 2013
 
(219) Nguyen A., Colin M., Rufer L., Bantignies C., Basrour S., Highly Effective Low Frequency Energy Harvester Using Bulk Piezoelectric Ceramics, International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS), London, UK, 2013
 
(220) Evans A., Aktan B., Aitken R., Nicolaidis M., Lauzeral O., Hot topic session 4A: Reliability analysis of complex digital systems, , 2013
 
(221) Gascard E., Simeu-Abazi Z., Suiphon B., Implementation of a fault diagnosis method for timed discrete-event systems, International Conference on Industrial Engineering and Systems Management (IESM 2013), Rabat, Morocco, 2013
 
(222) Bonnaud O., Fesquet L., Innovating projects as a pedagogical strategy for the French network for education in microelectronics and nanotechnologies, International Conference on Microelectronic Systems Education (MSE 2013), Austin, Texas, USA, 2013
 
(223) Maistri P., Alberto D., Leveugle R., Investigation of Electromagnetic Fault Injection Effects on Embedded Cryptosystems, First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'13), Avignon, France, 2013
 
(224) Nicolaidis M., Papavramidou P., Iterative Diagnosis for ECC-based Memory Repair, IEEE VLSI Test Symposium (VTS'13), Berkeley, CA, USA, 2013
 
(225) Rousseau F., El-Antably A., Lightweight task migration in embedded multi-tiled architectures using task code replication, Commuting Architectures Software tools and nano-Technologies for Numerical Embedded ans Scalable Systems (CASTNESS), Barcelona, Spain, 2013
 
(226) Nicolaidis M., Lorentz Transformations: structure of space-time or implication of interaction laws and measurement means?, ISRN: TIMA-RR--2013/01--FR, 2013
 
(227) Rolland R., Fesquet L., Le Pelleter T., Leroy Y., Beyrouthy T., Bonvilain A., Low-power signal processing platform based on non-uniform sampling and event-driven circuitry, Design, Automation and Test in Europe (DATE'13), Grenoble, France, 2013
 
(228) Renaux Ph., Defay E., Casset F., Gorisse M., Ancey P., Le Rhun G., Dieppedale C., Danel J., Fanget S., Chappaz C., Devos A., Basrour S., Civet Y., Low voltage actuated plate for haptic applications with PZT thin-film , International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers & Eurosensors'13), Barcelona, Spain , 2013
 
(229) Houssany S., Methodology to evaluate microprocessor sensitivity towards cosmic radiations, These de Doctorat, 2013
 
(230) Gascard E., Simeu-Abazi Z., Modular Modelling for the Diagnostic of Complex Discrete-Event Systems , IEEE Transactions on Automation Science and Engineering , 9, page: 1100-1125, 2013
 
(231) Mohamed F., Faubet P., Courant Y., Stratigopoulos H., Multidimensional analog test metrics estimation using extreme value theory and statistical blockade , 50th ACM / EDAC / IEEE Design Automation Conference (DAC), Austin, TX, USA, 2013
 
(232) Mir S., Huang K., Abdallah L., Stratigopoulos H., Bounceur A., Multivariate Statistical Techniques for Analog Parametric Test Metrics Estimation, 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Abu Dhabi, UAE, 2013
 
(233) Pétrot F., Hamayun M.M., Fournel N., Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization, Asian South-Pacific Design Automation Conference (ASP-DAC'13), Pacifico Yokohama, Yokohama, Japan, 2013
 
(234) Hamayun M.M., Native Simulation of Multi-Processor System-on-Chip using Hardware-Assisted Virtualization, These de Doctorat, 2013
 
(235) Bounceur A., Mir S., Euler R., Bentobache M., Kieffer Y., New techniques for selecting test frequencies for linear analog circuits, 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'13), Istanbul, Turkey, 2013
 
(236) Abdallah L., Stratigopoulos H., Mir S., Non-intrusive sensors for testing RF circuits, IEEE International Test Conference (ITC'13), Anaheim, CA, USA, 2013
 
(237) Rolland B., Bonvilain A., Le Pelleter T., Fesquet L., Beyrouthy T., Non-uniform sampling pattern recognition based on atomic decomposition, International Conference on Sampling Theory and Applications (SampTA'13), Bremen, Germany, 2013
 
(238) Abbas H., Amhaz H., Alleysson D., Sicard G., Novel Auto-Adaptative Integration-Time Technique for CMOS Image Sensor, International Image Sensor Workshop (IISW’13), Snowbird, USA, 2013
 
(239) Simeu E., Alhakim R., Raoof K., Novel control for delay-locked loop in IR-UWB communication systems, Control Engineering Practice, 21, page: 1437-1454, 2013
 
(240) Simeu E., Alhakim R., Novel design of tracking process for UWB communication systems, IEEE AFRICON 2013, Pointe-Aux-Piments, Mauritius, 2013
 
(241) Amhaz H., Sicard G., Alleysson D., Abbas H., Novel Mixed Design of Tone Mapping Technique for HDR CMOS Image Sensor, International Conference on Microelectronics (ICM’13), Beirut, Lebanon, 2013
 
(242) Leveugle R., Ben Jrad M., On improving at no cost the quality of products built with SRAM-based FPGAs, 5th Asia Symposium on Quality Electronic Design (ASQED 2013), Penang, Malaysia, 2013
 
(243) Quévremont J., Pancher F., Suescun R., Pierre L., On the Effectiveness of Assertion-Based Verification in an Industrial Context, 18th International Workshop on Formal Methods for Industrial Critical Systems (FMICS'2013), Madrid (Spain), 2013
 
(244) Nicolaidis M., On the State of Superposition and the Parallel or not Parallel Nature of Quantum Computing: a controversy raising point of view, ISRN: TIMA-RR--2013/02--FR, 2013
 
(245) Sohier D., Mansour W., Marques C.A., Pancher F., Velazco R., Bui A., Optimization of a self-converging algorithm at assembly level to improve SEU Fault-Tolerance, 4th Latin American Symposium on Circuits And Systems (LASCAS'13), Cusco, Peru, 2013
 
(246) Alhakim R., Optimizing the performance of sensor networks by controlling synchronization in ultra-wideband systems, These de Doctorat, 2013
 
(247) Raoof K., Simeu E., Alhakim R., Optimizing the performance of synchronization process: in ultra-wideband communication systems, LAMBERT Academic Publishing (LAP), 1-284, 2013
 
(248) Bounceur A., Beznia K., Mir S., Euler R., Output parameter reduction for an efficient evaluation of alternative test techniques, 28th International Conference on Design of Circuits and Integrated Systems (DCIS'13), San Sebastian, Spain, 2013
 
(249) Basrour S., PiezoMEMS for energy harvesting applications, PiezoNEMS Workshop, PHELMA-Polygone, Grenoble, France, 2013
 
(250) Kerkhoff H., Alexandrescu D., Costenaro E., Rohani A., Pulse-Length Determination Techniques in the Rectangular Single Event Transient Fault Model, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013
 
(251) Velazco R., . Radiation Effects on integrated circuits: origines, test methodologies and real life experiments, XV Reunión de Trabajo en Procesamiento de la Información y Control, San Carlos de Bariloche, Argentina, 2013
 
(252) Mir S., Stratigopoulos H., Laraba A., Bret G., Naudet H., Reduced code linearity testing of pipeline ADCs, IEEE Design and Test of Computers, 30, page: 80-88, 2013
 
(253) Mir S., Stratigopoulos H., Laraba A., Bret G., Naudet H., Reduced code linearity testing of pipeline adcs in the presence of noise , IEEE VLSI Test Symposium (VTS'13), Berkeley, CA, USA, 2013
 
(254) Nicolaidis M., Papavramidou P., Reducing Power Dissipation in Memory Repair for High Defect Densities, IEEE European Test Symposium (ETS'13), Avignon, France, 2013
 
(255) Bounceur A., Euler R., Mir S., Beznia K., Réduction des paramètres de sortie des circuits analogiques par l’estimation des métriques de test, Journées GDR SoC-SiP, Lyon, France, 2013
 
(256) Bonnot Ph., Grasset A., Hamdioui S., Nicolaidis M., Gizopoulos D., Groeseneken G., Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes, Design Automation and Test in Europe Conference (DATE'13), Grenoble, France, 2013
 
(257) Ben Jrad M., Robust design of circuits implemented on SRAM-based FPGAs and validation by fault injection, These de Doctorat, 2013
 
(258) Pierre L., Runtime verification of functional requirements for SoC models: integration of PSL in SystemC TLM, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, Leysin, Suisse, 2013
 
(259) Rouzeyre B., Potin O., Dutertre J.M., Flottes M.-L., Possamai Bastos R., Di Natale G., Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'13), Arcachon, France, 2013
 
(260) Rouzeyre B., Potin O., Flottes M.-L., Di Natale G., Possamai Bastos R., Dutertre J.M., Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection, Microelectronics Reliability, 53, Issues 9–11, September–November , page: 1320–1324, 2013
 
(261) Sicard G., Souza Alexandre K. P. , de Moraes Cruz Carlos A. , de Lima Monteiro Davies W. , Simple Technique to Reduce FPN in a linear-logarithm APS, International Image Sensor Workshop (IISW’13), Snowbird, USA, 2013
 
(262) Pétrot F., Hamayun M.M., Fournel N., Simulation native des systèmes intégrés utilisant le support matériel à la virtualisation, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, Leysin, Suisse, 2013
 
(263) Velazco R., Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques, Workshop Education Society and Computational Iintelligence Society (WESCIS’13),Tucuman, Argentina, 2013
 
(264) Arques M., Dupont B., Rohr P., Sicard G., Tchagaspanian M., Verger L., Habib A., Sphinx1: Spectrometric Photon Counting and Integration Pixel for X-Ray Imaging with a 100 Electrons LSB, Medical Imaging Conference (MIC’13), Seoul, Korea, 2013
 
(265) Costenaro E., Alexandrescu D., Evans A., State-aware single event analysis for sequential logic , IEEE International On-Line Testing symposium (IOLTS'13), Chania, Crete, Greece, 2013
 
(266) Mir S., Statistical learning for test and control of analog/RF circuits, 4th European Workshop on CMOS Variability (VARI), Karlsruhe, Germany, 2013
 
(267) Bounceur A., Mir S., Euler R., Beznia K., Statistical Modelling of Analog Circuits for Test Metrics Computation, 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'13), Abu Dhabi, UAE, 2013
 
(268) Fesquet L., Yahya E., Ismail Y., Renaudin M., Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation, 19th International Symposium on Asynchronous Circuits and Systems (ASYNC'13), Santa Monica, USA, 2013
 
(269) Costenaro E., Evans A., Alexandrescu D., Subtleties of Single Event Upset Analysis and Mitigation in Sequential Cells, IEEE International Reliability Innovations Conference (IRIC'13), 2013
 
(270) Xie Hao, Chen Liang, Evans A., Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance, The 19th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2013) Vancouver, British Columbia, Canada, 2013
 
(271) Javaheri N., Borrione D., Morin-Allory K., SyntHorus-2: Automatic Prototyping from PSL, IFIP/IEEE International Conference On Very Large Scale Integration (VLSI-SoC'13), Istanbul (Turkey), 2013
 
(272) Bousquet L., Simeu E., System-level modeling of electromechanical devices with energy consumption, 7th International IEEE Systems Conference (Syscon 2013), Orlando, Florida, 2013
 
(273) Bonnaud O., Fesquet L., The new strategy based on Innovative Projects in Microelectronics and Nanotechnologies, Symposium on Microelectronics Technology and Devices (SBMicro'13), Curitiba, Brazil, 2013
 
(274) Nicolaidis M., The scandal of the computational universe, First part: the qualitative concepts , Computing and Philosophy Symposium (AISB Convention'13), Exeter, UK, 2013
 
(275) Nicolaidis M., The scandal of the computational universe, Second part: relativity and quantum mechanics , Computing and Philosophy Symposium (AISB Convention'13), Exeter, UK, 2013
 
(276) Robert A.L.G., Chagnon G., Bonvilain A., Cinquin Ph., Moreau-Gaudry A., Toward a real-time tracking of a medical deformable needle from strain measurements , Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC'13), Osaka, Japan, 2013
 
(277) Evans A., Alexandrescu D., Chen Liang, Tahoori M., Nicolaidis M., Costenaro E., Towards a Hierarchical and Scalable Approach for Modeling the Effects of SETs, IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Stanford University, CA, 2013
 
(278) Nicolaidis M., Papavramidou P., Transparent BIST for ECC-based memory repair , IEEE International On-Line Testing Symposium (IOLTS'13), Chania, Crete, Greece, 2013
 
(279) Ekobo Akoa B., Simeu E., Lebowsky F., Using Artificial Neural Network for Automatic Assessment of Video Sequences , 27th International Conference on Advanced Information Networking and Applications Workshops (WAINA'13), Barcelona, Spain, 2013
 
(280) Ekobo Akoa B., Simeu E., Lebowsky F., Using Classification for Video Quality Evaluation, IEEE International Conference on Microelectronics (ICM'13), Beirut, Lebanon, 2013
 
(281) Nicolaidis M., Bonnoit T., Zergainoh N.-E., Using Error Correcting Codes without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study, JETTA - Journal of Electronic Testing: Theory and Application, 29, page: 383-400, 2013
 
(282) Pétrot F., Hamayun M.M., Fournel N., Using Hardware Assisted Virtualization for Native Simulation of MPSoC, Embedded MPSoC and Multicore, Otsu, Japan, 2013
 
(283) Chaix F., Zergainoh N.-E., Bizot G. , Nicolaidis M., Variability-aware and fault-tolerant self-adaptive applications for many-core chips , IEEE International On-Line Testing Symposium (IOLTS'13), Chania, Crete, Greece, 2013
 
(284) Nicolaidis M., Bizot G. , Chaix F., Zergainoh N.-E., Variability-Aware and Fault-tolerant Self-Adaptive applications for Many-Core chips, European Test Symposium (ETS'13), Avignon, France, 2013
 
(285) Colin M., Basrour S., Rufer L., Very low frequency piezoelectric energy harvester designed for heart beat vibration scavenging, 3èmes Journées Nationales sur la Récupération et le Stockage d'Energie pour l'Alimentation des Microsystèmes Autonomes (JNRSE’13), Toulouse, France, 2013
 
(286) Simeu E., Ekobo Akoa B., Lebowsky F., Video decoder monitoring using non-linear regression, IEEE 19th International On-Line Testing Symposium (IOLTS'13), Chania, 2013
 
(287) Zhou Z., Ollivier S., Wong M., Salze E., Rufer L., Wide-band aero-acoustic microphone with improved low-frequency characteristics , International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers & Eurosensors'13), Barcelona, Spain, 2013
 
(288) Rouxel D., Vincent B., Rufer L., Leroy M., Nguyen V.S., Arthaud Y., 3D MEMS-based tactile vibration sensor for measurement on lightweight objects, International Symposium on Applications of Ferroelectrics (ISAF-ECAPD-PFM'12), Aveiro, Portugal, 2012
 
(289) Durante P., Bahmani M., Sheibanyrad H., Pétrot F., Dubois F., A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies , IEEE Computer Society Annual Symposium on VLSI (ISVLSI'12), Amherst, USA, 2012
 
(290) Beznia K., Mir S., Bounceur A., Euler R., Abdallah L., Huang K., Accurate estimation of analog test metrics with extreme circuits, 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Sevilla, Spain, 2012
 
(291) Coppola M., Pétrot F., Catalano V., Dubois F., Accurate on-chip router Area modeling with Kriging methodology, International Conference on Computer-Aider Design (ICCAD'12), San José, CA, USA, 2012
 
(292) Bizot G. , Activity and power management in massively parallel multi-cores architectures., These de Doctorat, 2012
 
(293) Stratigopoulos H., Mir S., Adaptive alternate analog test, IEEE International Test Workshop on Defect and Adaptive Test Analysis (DATA'12), Anaheim, CA, USA, 2012
 
(294) Mir S., Stratigopoulos H., Adaptive Alternate Analog Test, IEEE Design and Test of Computers, 29, page: 71-79, 2012
 
(295) Thabuis T., Villard P., Belleville M., Sicard G., Decaens G., Zecri M., Adaptive Gain and Analog Wavelet Transform for Low-Power Infrared Image Sensors, Active and Passive Electronic Components Journal (APEC), 2012, Article ID 610176, page: 1-6 , 2012
 
(296) Simeu E., Cenni F., Mir S., Abdallah L., Khereddine R., Adaptive logical control of RF LNA performances for efficient energy consumption, VLSI-SoC: Forward-Looking Trends in IC and Systems Design , Springer , 43-68, Volume 373, 2012
 
(297) Stratigopoulos H., De Jonghe D., Maricau E., Tasic B., Gielen G., McConaghy T., Advances in variation-aware modeling, verification, and testing of analog ICs , IEEE Design, Automation and Test in Europe Conference, Dresden, Germany, 2012
 
(298) Hübner M., Becker J., Altieri M., Pagliarini S., Azambuja J.R., Lima Kastensmidt F., Velazco R., Foucard G., A Fault Tolerant Approach to Detect Transient Faults in Microprocessors Based on a Non-Intrusive Reconfigurable Hardware , IEEE Transactions on Nuclear Science, 59, page: 1117 - 1124 , 2012
 
(299) Pierre L., A Formal Framework for Testing with Assertion Checkers in Mixed-Signal Simulation, IEEE International Conference on Electronics, Circuits, and Systems (ICECS'2012), Seville (Spain), 2012
 
(300) Pierre L., Tsiligiannis G., A Mixed Verification Strategy Tailored for Networks on Chip, Sixth IEEE/ACM International Symposium on Networks on Chip (NoCS'12), Copenhagen, Denmark, 2012
 
(301) Mir S., Simeu E., Slamani M., Akkouche N., Analog/RF test ordering in the early stages of production testing , 30th IEEE VLSI Test Symposium, Hawaii, USA, 2012
 
(302) Velazco R., Mansour W., An automated SEU fault-injection method and tool for HDLbased designs, Radiation Effects on Components and Systems (RADECS'12), Biarritz, France , 2012
 
(303) Cherkaoui A., Fischer V., Aubert A., Fesquet L., A New Robust True Random Numbers Generator Using Self-Timed Rings, Workshop on Cryptographic architectures embedded in reconfigurable devices (Cryptarchi'12), Chateau de Goutelas, Marcoux, France, 2012
 
(304) Huard V., Pion E., Cacho F., Robert V., Delater R., Mergault P., Engels S., Anghel L., Ruiz Amador N., Croain D., A predictive bottom-up hierarchical approach to digital system reliability , IEEE International Reliability Physics Symposium (IRPS'12), Anaheim, CA, USA, 2012
 
(305) Bonnoit T., Architectural solutions for reliable and high performance circuits, These de Doctorat, 2012
 
(306) Alexandrescu D., Costenaro E., Nicolaidis M., Evans A., A Standards Based Approach to the Reliability Specification of IP Components, IP-SOC Conference, Grenoble, France, 2012
 
(307) Yahya E., Fesquet L., Renaudin M., Asynchronous circuit performance analysis, fundamentals and efficient tools, Tutorial in 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'12), Copenhagen, Denmark, 2012
 
(308) Porcher A., Asynchronous monitors synthesis from temporal assertions for the robust observation of synchronous circuits, These de Doctorat, 2012
 
(309) Bounceur A., Beznia K., Euler R., Mir S., Saoud B., A tool for statistical modeling by means of Copulas of analog and mixed-signal circuits, 27th International Conference on Design of Circuits and Integrated Systems (DCIS'12), Avignon, France, 2012
 
(310) Lagraa S., Termier A., Pétrot F., Automatic congestion detection in MPSoC programs using data mining on simulation traces, 23rd IEEE International Symposium on Rapid System Prototyping (RSP'12), Tampere, Finland, 2012
 
(311) Nicolaidis M., Biologically Inspired Robust Tera-Device Processors, IEEE Design and Test of Computers, 29, September/October, page: 94-99, 2012
 
(312) Rouxel D., Rufer L., Capteur de vibrations souple à base de film polymère nanocomposite piézoélectrique pour application médicale , 447359, 2012
 
(313) Tan J., Fresse V., Rousseau F., GE Zhiwei, Case Study: Deployment of the 2D NoC on 3D for the Generation of Large Emulation Platforms, 23rd International Symposium on Rapid System Prototyping (RSP'12), Tampere, Finland, 2012
 
(314) Evans A., Nicolaidis M., Wen S.J., Case Study of SEU Effects in a Network Processor, IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'12), Urbana-Champagne, USA, 2012
 
(315) Nicolaidis M., Cells: A Framework for Designing Robust Tera-Device Processors, Workshop on Low Power Design Impact on Test and Reliability (LPonTR'12), Annecy, France, 2012
 
(316) Boscher D., Hubert G., Lacoste V., Velazco R., Cheminet A., Characterization of the neutron environment at the CERN-EU High Energy Reference Field and at the Pic du Midi, Radiation Effects on Components and Systems (RADECS'12), Biarritz, France, 2012
 
(317) Stratigopoulos H., Makris Y., Checkers for Online Self-Testing of Analog Circuits, Advanced Circuits for Emerging Technologies, Wiley, Chichester, UK, Chapter 21, 2012
 
(318) Leveugle R., Ben Jrad M., Comparison of FPGA platforms for emulation-based fault injections using run-time reconfiguration, Conference on Design of Circuits and Integrated Systems (DCIS'12), Avignon, France, 2012
 
(319) Cherkaoui A., Fischer V., Aubert A., Fesquet L., Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs, Design Automation and Test in Europe (DATE'12), Dresden, Germany, 2012
 
(320) Hubert G., Velazco R., Federico C.A., Cheminet A., Silva Cardenas C., Caldas L.V., Palumbo F., Lacoste V., Mansour W., Artola L., Pineda F., Duzellier S., Pancher F., Continuous high-altitude measurements of cosmic ray neutrons and SEU/MCU at various locations: correlation and analyses based on MUSCA SEP3, Radiation Effects on Components and Systems (RADECS'12), Biarritz, France, 2012
 
(321) Bonvilain A., Contribution to the design and the realization of microsystems : from energy to the medical, HDR, 2012
 
(322) Fesquet L., Controling variability and energy by design, CMOS Emerging Technologies, Vancouver, BC, Canada, 2012
 
(323) Dubois M., Mir S., Stratigopoulos H., Convertisseur analogique-numérique sigma-delta muni d’un circuit de test, 10/02741 , 2012
 
(324) Foroutan S., Sheibanyrad H., Pétrot F., Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces, The Design Automation Conference (DAC), San Francisco, USA, 2012
 
(325) Pasca V., Benabdenbi M., Anghel L., Nicolaidis M., CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems , JETTA - Journal of Electronic Testing: Theory and Application, 28, page: 137-150, 2012
 
(326) Nicolaidis M., Zergainoh N.-E., Zorian Y., Karnik T., Lu S.-L., Tokunaga C., Raychowdhury A., Tschanz J., Anghel L., Khellah M., Kulkarini J., Vivek De, Avresky D., Bowman K., Design for Test and Reliability in Ultimate CMOS, Design, Automation and Test in Europe (DATE'12), Dresden, Germany, 2012
 
(327) Nicolaidis M., Designing Robust Single-Chip Massively-Parallel Tera-Device Processors, Keynote in Opening Session at 4th Design for Reliability Workshop (DFR), 7th International Conference on High Performance and Embedded Architecture and Compilation (HiPEAC), Paris, France, 2012
 
(328) Mancini S., Rousseau F., Design of non-linear kernel IPs for vision systems , WACS Congress, 2012
 
(329) Raoof K., Alhakim R., Simeu E., Design of Tracking Loop for UWB Systems, International Conference on Information Processing and Wireless Systems (IP-WIS), Sousse, Tunisia, 2012
 
(330) Alhakim R., Raoof K., Simeu E., Design of tracking loop with dirty templates for UWB communication systems, Signal Image and Video Processing Journal, June, page: 1-7, 2012
 
(331) Wecxsteen A., Bergaoui S., Leveugle R., Detailed analysis of compilation options for robust software-based embedded systems, 13th Latin-American Test Workshop (LATW'12), Quito, Ecuador, 2012
 
(332) Mir S., Huang K., Xing Y., Kruseman B., Stratigopoulos H., Hora C., Diagnosis of Local Spot Defects in Analog Circuits , IEEE Transactions on Instrumentation and Measurement, 61, page: 2701 - 2712 , 2012
 
(333) Arthaud Y., Mélé P., Rufer L., Dispositif de mesure de vibrations, Demande de brevet FR No 12/54614, 2012
 
(334) Pasca V., Rehman Saif-Ur, Anghel L., Benabdenbi M., Efficient link-level error resilience in 3D NoCs , IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS'12) , 2012
 
(335) Frank T., Chappaz C., Federspiel X., Arnaud L., Colella F., Petitprez E., Anghel L., Electromigration degradation mechanism analysis of SnAgCu interconnects for eWLB package , International Reliability Physics Symposium (IRPS'12), Anaheim, CA, USA, 2012
 
(336) Fresse V., Tan J., Rousseau F., Emulation platform for an adaptive NoC-based MPSoC architecture dedicated to spectral imaging for art authentication, International Conference on Image Processing Theory, Tools and Applications (IPTA'12), Istanbul, Turkey, 2012
 
(337) Naudet H., Laraba A., Stratigopoulos H., Forel C., Mir S., Enhanced Reduced Code Linearity Test Technique for Multi-bit/Stage Pipeline ADCs, IEEE 17th European Test Symposium (ETS’12), Annecy, France, 2012
 
(338) Mancini S., Rousseau F., Enhancing Non-Linear Kernels by an Optimized Memory Hierarchy in a High Level Synthesis Flow, Design, Automation and Test in Europe (DATE'12), Dresden, Germany, 2012
 
(339) Abdallah L., Mir S., Stratigopoulos H., Kelma C., Experiences with non-intrusive sensors for RF built-in test, IEEE International Test Conference (ITC), Anaheim, CA, USA, 2012
 
(340) Houssany S., Guibbaud N., Bougerol A. , Leveugle R., Miller F., Experimental Assessment of Cache Memory Soft Error Rate Prediction Technique, European Conference on Radiation and its Effects on Components and Systems (RADECS'12), Biarritz, France, 2012
 
(341) Tan J., Exploration of a generic architecture on FPGA for the algorithms of the multispectral imaging , These de Doctorat, 2012
 
(342) Fournel N., Pétrot F., Michel L., Fast simulation of systems embedding VLIW processors, IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS), Tampere, Finland, 2012
 
(343) Cherkaoui A., Fesquet L., Hamon J., Générateurs de nombres aléatoires vrais, FR 12 51079 , 2012
 
(344) Damri L., Generation of test sequences for accelerating assertions, These de Doctorat, 2012
 
(345) Chefi A., Soudani A., Sicard G., Hardware compression scheme based on low-complexity arithmetic encoding for low power image transmission over WSNs, 1st Workshop on Architecture of Smart Camera (WASC'12), Clermont-Ferrand, France, 2012
 
(346) Muller O., Pétrot F., Horrein P.-H, Xu Yan, HCM: An Abstraction Layer for Seamless Programming of DPR FPGA, 2nd Internation Conference on Field Programmable Logic and Applications (FPL'12), Oslo, Norway, 2012
 
(347) Cenni F., High level modeling of heterogeneous systems, analog/digital interfacing, These de Doctorat, 2012
 
(348) Bousquet L., Simeu E., High-level Modeling of Power Consumption in Active Linear Analog Circuits, 22nd Great Lakes Symposium on Very Large Scale Integration (GLSVLSI 2012), Salt Lake City, Utah, 2012
 
(349) Lévêque A., Pêcheux F., Louërat M.-M., Aboushady A., Scotti S., Massouriz A., Clavierz L., Cenni F., Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System, Design, Automation and Test in Europe (DATE'12), Dresden, Germany, 2012
 
(350) Mansour W., Velazco R., Pancher F., Costa-Marques G., Sohier D., Bui A., Improving SEU Fault Tolerance Capabilities of a Self-Converging Algorithm , IEEE Transactions on Nuclear Science, 59, page: 818 - 823, 2012
 
(351) Abbas H., Amhaz H., Sicard G., Alleysson D., In Pixel Implementation of autoadaptative integration time, 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS’12), Seville, Spain, 2012
 
(352) Ferro L., Pierre L., Bel Hadj Amor Z., Bourgon P., Quévremont J., Integrating PSL Properties into SystemC Transactional Modeling - Application to the Verification of a Modem SoC, IEEE International Symposium on Industrial Embedded Systems (SIES'2012), Karlsruhe (Germany), 2012
 
(353) Benabdenbi M., Anghel L., Pasca V., Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis, JETTA - Journal of Electronic Testing: Theory and Application, 28 , page: Online First™, 2012
 
(354) Amhaz H., Low level image processing integrated in CMOS vision sensor, These de Doctorat, 2012
 
(355) Federico C.A., Velazco R., Pancher F., Hubert G., Silva Cardenas C., Pineda F., Palumbo F., Goncalez O.L., Mansour W., Duzellier S., Caldas L.V., Medições de nêutrons oriundos de radiação cósmica em Puno (Peru) , XXII WAI (IEAv anual Workshop), Sao José dos Campos, Brazil, 2012
 
(356) Civet Y., MEMS Resonator Frequency Compensation for Time Reference, These de Doctorat, 2012
 
(357) Bonvilain A., Fesquet L., Le Pelleter T., Méthode à faible coût de calcul et robuste pour la détection d’un motif dans un signal, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'12), Marseille, France, 2012
 
(358) Paugnat F., Method for the Modelling and the Refinement of the Heterogeneous Systems, These de Doctorat, 2012
 
(359) Mansour W., Methods and tools for the early analysis in the design flow of the sensitivity to soft-errors of applications and integrated circuits, These de Doctorat, 2012
 
(360) Bougerol A. , Buard N., Miller F., Leveugle R., Guibbaud N., Houssany S., Microprocessor Soft Error Rate Prediction Based on Cache Memory Analysis, IEEE Transactions on Nuclear Science, 59, page: 980-987, 2012
 
(361) Ekeom D., Rufer L., Modelling of wide frequency range piezoresistive MEMS microphone, 11th International Workshop on Micromachined Ultrasonic Transducers, Tours, France, 2012
 
(362) Ekeom D., Rufer L., Modelling of wide frequency range silicon microphone for acoustic measurement, 11th Congrès Français d’Acoustique and the 2012 Annual IOA Meeting , Nantes, France, 2012
 
(363) Paugnat F., Morin-Allory K., Fesquet L., Model of a Simple yet effective Operational Amplifier, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), Seville, Spain, 2012
 
(364) Rousseau F., Pétrot F., Chagoya-Garzon A., Multi-Device Driver Synthesis Flow for Heterogeneous Hierarchical Systems, 15th Euromicro Conference on Digital System Design (DSD'12), Izmir, Turkey, Sept. 5-8, 2012
 
(365) Ruiz Amador N., Multilevel aging phenomena analysis in complex ultimate CMOS designs, These de Doctorat, 2012
 
(366) Shen H., Pétrot F., Hamayun M.M., Native Simulation of MPSoC Using Hardware-Assisted Virtualization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31, page: 1074 - 1087 , 2012
 
(367) Excoffon E., Papillon F., Fesquet L., Bonnaud O., Bsiesy Ah., New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school , International Conference on Information Technology Based Higher Education and Training (ITHET'12), Istanbul, Turkey, 2012
 
(368) Amhaz H., Sicard G., New smart readout technique performing edge detection designed to control vision sensors dataflow, 24th IS&T/SPIE Electronic Imaging Conference, Burlingame, California, USA, 2012
 
(369) Abdallah L., Non-intrusive embedded sensors for testing RF circuits, These de Doctorat, 2012
 
(370) Possamai Bastos R., Torres F.S., Di Natale G., Flottes M.-L., Rouzeyre B., Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode, Microelectronics Reliability, 52, page: 1781–1786, 2012
 
(371) Possamai Bastos R., Torres F.S., Di Natale G., Flottes M.-L., Rouzeyre B., Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode, 23rd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'12), Cagliari, Italy, 2012
 
(372) Gerin P., Hamayun M.M., Pétrot F., On Software Simulation for MPSoC. A Modeling Approach for Functional Validation and Performance Estimation, Design Technology for Heterogeneous Embedded Systems, Springer , 91-114, 2012
 
(373) Anghel L., On the Dependability of 3D Interconnects, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), Alpes d'Huez, France, 2012
 
(374) Bourdarie S., Velazco R., Artola L., Duzellier S., Ecoffet R., Hubert G., Operational risk assessment at solar events using a new statistical approach for SEU rate prediction, Nuclear and Space Radiation Effects Conference (NSREC'12), Miami, USA, 2012
 
(375) Kamsu-Foguem B., Simeu E., Optimizing Construction of Scheduled Data Flow Graph for Online testability, The Mediterranean Journal of Computers and Networks , 8, page: 125-133, 2012
 
(376) Bounceur A., Mir S., Saoud B., Kerkar M., Beznia K., Outil de modélisation statistique des circuits analogiques et mixtes, Journées GDR SoC-SiP, Paris, France, 2012
 
(377) Ben Jrad M., Leveugle R., Pattern-based injections in processors implemented on SRAM-based FPGAs, 13th Latin-American Test Workshop (LATW'12), Quito, Ecuador, 2012
 
(378) Di Mascolo M., Gascard E., Simeu-Abazi Z., Performance evaluation of centralized maintenance workshop by using Queuing Networks, IFAC Workshop on Advanced Maintenance Engineering, Service and Technology (AMEST'12), Seville, Spain, 2012
 
(379) Vittoz S., Le Boulbar E., Vanko G., Brinkfeldt K., Rufer L., Johander P., Lalinsky T., Bowen C.R., Allsopp D.W.E., Edwards M.J., Pressure and temperature dependence of GaN/AlGaN high electron mobility transistor based sensors on a sapphire membrane, Physica Status Solidi C: Current Topics in Solid State Physics, 9, page: 960-963, 2012
 
(380) Edwards M.J., Lalinsky T., Vittoz S., Bowen C.R., Allsopp D.W.E., Vanko G., Johander P., Brinkfeldt K., Rufer L., Le Boulbar E., Pressure sensors based on AlGaN/GaN High Electron Mobility Transistor: An investigation of electricalparameters influences to response sensitivity, UK Nitride Consortium (UKNC) Meeting, Bailbrook House, Bath, UK, 2012
 
(381) Morin-Allory K., Borrione D., Oddos Y., Property-Based Dynamic Verification and Test, Design Technology for Heterogeneous Embedded Systems, Springer , 157-176, 2012
 
(382) Costenaro E., Nicolaidis M., Wen S.J., Alexandrescu D., Evans A., RIIF - Reliability Information Interchange Format, International On-Line Testing Symposium (IOLTS’12), Sitges, Spain, 2012
 
(383) Torres F.S., Possamai Bastos R., Robust modular Bulk Built-in Current Sensors for detection of transient faults, 25th Symposium on Integrated Circuits and Systems Design (SBCCI'12), Brasilia, 2012
 
(384) Rieubon S., Fesquet L., Elissati O., Yahya E., Self-Timed Rings: A Promising Solution for Generating High-Speed High Resolution Low-Phase Noise Clocks, VLSI-SoC: Forward-Looking Trends in IC and Systems Design 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers, Springer , 22-42, 2012
 
(385) Fesquet L., Fischer V., Aubert A., Cherkaoui A., Self-Timed Rings as Entropy Sources, 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'12), Copenhagen, Denmark, 2012
 
(386) Cherkaoui A., Fischer V., Aubert A., Fesquet L., Self-Timed Rings as Sources of Entropy, 6ème colloque du GDR SOC-SIP du CNRS, Paris, France, 2012
 
(387) Mansour W., Velazco R., SEU Fault-Injection in VHDL-Based Processors: A Case Study, 13th Latin-American Test Workshop (LATW'12), Quito, Ecuador, 2012
 
(388) Bidegaray-Fesquet B., Fesquet L., Signal Processing for AsynchronouS Systems (SPASS), IDDN.FR.001.080019.000.S.P.2012.000.31235, 2012
 
(389) Valadimas S., Tsiatouhas Y., Arapoyanni A., Evans A., Single event upset tolerance in flip-flop based microprocessor cores , IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, Texas, USA, 2012
 
(390) Horrein P.-H, Software design for flexible radio: integration of heterogeneous computing units, These de Doctorat, 2012
 
(391) Ferron J.B., Static analysis of configuration error effects in SRAM-based FPGAs and robustness improvement, These de Doctorat, 2012
 
(392) Gustavo F., Basrour S., Yang W., Bonvilain A., Strain microgauge implementation on cylindrical metal substrates, Microelectronic Engineering, 97, September, page: 285–288, 2012
 
(393) Wong R., Bhuva B.L., Evans A., Wen S.J., System-level reliability using component-level failure signatures , International Reliability Physics Symposium (IRPS'12), Anaheim, CA, USA, 2012
 
(394) Mir S., Stratigopoulos H., Dubois M., Ternary Stimulus for Fully Digital Dynamic Testing of SC ΣΔ ADCs , IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, Taipei, Taiwan, 2012
 
(395) Papavramidou P., Nicolaidis M., Test algorithms for ECC-based memory repair in nanotechnologies, VLSI Test Symposium (VTS'13), Maui, Hawaii, US, 2012
 
(396) Abdallah L., Altet J., Stratigopoulos H., Mir S., Testing RF Circuits With True Non-Intrusive Built-In Sensors, Design, Automation and Test in Europe (DATE'12), Dresden, Germany, 2012
 
(397) Beznia K., Bounceur A., Mir S., Euler R., Test metrics computation using the statistical model of analog circuits, Journées GDR SoC-SiP, Paris, France, 2012
 
(398) Stratigopoulos H., Test Metrics Model for Analog Test Development, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31, page: 1116 - 1128 , 2012
 
(399) Nicolaidis M., Pasca V., Anghel L., Through-Silicon-Via Built-In Self-Repair for Aggressive 3D Integration, International On-Line Testing Symposium (IOLTS’12), Sitges, Spain, 2012
 
(400) Alhakim R., Raoof K., Simeu E., Timing Synchronisation for IR-UWB Communication Systems, Ultra Wideband - Current Status and Future Trends, InTech Europe, Rijeka, Croatia, 15-40, 2012
 
(401) Anghel L., Leveugle R., Ferron J.B., Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K, 3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12), Playa del Carmen, Mexico, 2012
 
(402) Choi C.-H., Reis R., Tsui C.-Y., Mir S., VLSI-SoC: The Advanced Research for Systems on Chip, Springer , VII, 187 p. 104 illus., 2012
 
(403) Rufer L., Wong M., Salze E., Ollivier S., Zhou Z., Yuldashev P., Wide-Band Piezoresistive Microphone for Aero-Acoustic Applications, The 11th Annual IEEE Conference on Sensors, Taipei, Taiwan, 2012
 
(404) Maistri P., Leveugle R., 10-gigabit throughput and low area for a hardware implementation of the Advanced Encryption Standard, 14th Euromicro/IEEE Conference on Digital System Design (DSD'11), Oulu, Finland, 2011
 
(405) Pétrot F., Sheibanyrad H., Jantsch A., 3D Integration for NoC-based SoC Architectures, Springer , 278 p., 2011
 
(406) Firmin F., Sicard G., Abouzeid F., Clerc S., Renaudin M., 40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), 16, page: article 35, 2011
 
(407) Stratigopoulos H., Mir S., Adaptive Alternate Analog Test, IEEE Latin-American Test Workshop (LATW’11), Porto de Galinhas, Brazil, 2011
 
(408) Avresky D., Rusu C., Anghel L., Adaptive inter-layer message routing in 3D networks-on-chip, Microprocessors and Microsystems, 35, page: 613-631, 2011
 
(409) Khereddine R., Adaptive logical control and test of AMS/RF circuits, These de Doctorat, 2011
 
(410) Chaix F., Avresky D., Zergainoh N.-E., Nicolaidis M., A Fault-Tolerant Deadlock-Free Adaptive Routing for On Chip Interconnects, Best IP Award, Design Automation and Test in Europe Conference (DATE’11), Grenoble, France, 2011
 
(411) Edwards M.J., Allsopp D.W.E., Bowen C.R., Vanko G., Lalinsky T., Heinle U., Le Boulbar E., Brinkfeldt K., Johander P., Napier R., Vittoz S., Rufer L., AlGaN/GaN High Electron Mobility Transistor based Pressure Sensor for Harsh Environments, Design and Test, IEEE Sensors Conference, Limerick, Ireland, 2011
 
(412) Renaudin M., Fesquet L., Sicard G., Alsayeg K., A modular synthesis method for low-power QDI state machines , 9th IEEE International NEWCAS Conference, Bordeaux, France, 2011
 
(413) Paugnat F., Bousquet L., Fesquet L., Analog Design Abstraction Levels and SystemC AMS Models of Computation, SystemC-AMS Day 2011: Industry Adoption of the SystemC AMS Standard, Dresden, Germany, 2011
 
(414) Ferron J.B., Anghel L., Leveugle R., Analysis of configuration bit criticality in designs implemented with SRAM-based FPGAs, IEEE Symposium on Industrial Electronics & Applications (ISIEA('12), Langkawi, Malaysia, 2011
 
(415) Rehder G.P., Rufer L., Vittoz S., Benkart P., Heinle U., Analytical and numerical modelling of AlGaNnext term/previous termGaNnext term/previous termAlNnext term heterostructure based cantilevers for mechanical sensing in harsh environments, Sensors and Actuators A : Physical, 172, page: 27-34, 2011
 
(416) Pétrot F., An analytical model for Many-Functionally Asymmetric Core SoC Architectures, 11th International Forum on Embedded MPSoC and Multicore, Beaune, France, 2011
 
(417) Beyrouthy T., Fesquet L., Greitans M., Shavelis R., Robin R., An Asynchronous FIR Filter Architecture coupled to a Level-Crossing ADC, 9th International Conference on Sampling Theory and Applications (SampTA), Singapore, 2011
 
(418) Hennebert Ch., Pétrot F., Horrein P.-H, An Environment for (re)configuration and Execution Managenment of Flexible Radio Platforms , 14th Euromicro Conference on Digital System Design (DSD’11), Oulu, Finland, 2011
 
(419) Beyrouthy T., Fesquet L., An event-driven FIR filter: Design and implementation , 22nd IEEE International Symposium on Rapid System Prototyping (RSP'11), Karlsruhe, Germany, 2011
 
(420) Idriss T., Ziade H., Ayoubi R., Velazco R., A new fault injection approach to study the impact of bitflips in the configuration of SRAM-based FPGAs, International Arab Journal of Information Technology (IAJIT), 8, page: 155-162, 2011
 
(421) Amhaz H., Abbas H., Zimouche H., Sicard G., An improved smart readout technique based on temporal redundancies suppression designed for logarithmic CMOS image sensor, 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS’11), Beirut, Lebanon, 2011
 
(422) Pétrot F., Hedde D., A non intrusive simulation-based trace system to analyse Multiprocessor Systems-on-Chip software, 22nd IEEE International Symposium on Rapid System Prototyping (RSP’11), pp.171-177, Karlsruhe, Germany, 2011
 
(423) Velazco R., El Falou W., Ziade H., Ayoubi R., Mansour W., An Optimal Implementation on FPGA of a Hopfield Neural Network, Advances in Artificial Neural Systems, Article ID 189368, page: 9 pages, 2011
 
(424) Bousquet L., Paugnat F., Morin-Allory K., Fesquet L., A Performance Comparison Between the SystemC-AMS Models of Computation, edaWorkshop 2011, Dresden, Germany, 2011
 
(425) Costenaro E., Nicolaidis M., Alexandrescu D., A Practical Approach to Single Event Transients Analysis for Highly Complex Designs , IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems (DFT’11), Vancouver, Canada, 2011
 
(426) Morin-Allory K., Fesquet L., Paugnat F., A refinement process for top-down mixed-signal designs thanks to SystemC-AMS , IEEE 9th International New Circuits and Systems Conference (NEWCAS'11), Bordeaux, France, 2011
 
(427) Pétrot F., Sheibanyrad H., Asynchronous 3D-NoCs Making Use of Serialized Vertical Links, 3D Integration for NoC-based SoC Architectures , Springer , 149-165, 2011
 
(428) Zakaria H., Asynchronous Architecture for Power Efficiency and Yield Enhancement in the Decananometric Technologies: Application to a Multi-Core System-on-Chip, These de Doctorat, 2011
 
(429) Cenni F., Scotti S., Simeu E., A SystemC AMS/TLM platform for CMOS video sensors , IEEE Conference on Design and Architectures for Signal and Image Processing (DASIP’11), Tampere, Finland, 2011
 
(430) Simeu-Abazi Z., Gascard E., Automatic Construction of Diagnoser for Complex Discrete Event Systems, International Workshop on Dependable Control of Discrete Systems (DCDS’11), Saarbrücken, Germany, 2011
 
(431) Cenni F., Scotti S., Simeu E., Behavioral modeling of a CMOS video sensor platform using SystemC AMS / TLM, IEEE Forum for Design Languages (FDL’11), Oldenburg, Germany, 2011
 
(432) Nicolaidis M., Biological Inspired Single-chip Massively Parallel Self-healing, Self-regulating, Tera-device Computers, International Conference of IACAP (International Association of Computing and Philosophy), Aarhus, Denmark, 2011
 
(433) Croain D., Robert V., Engels S., Flatresse P., Pion E., Cacho F., Anghel L., Huard V., Ruiz Amador N., Bottom-up digital system-level reliability modeling , Custom Integrated Circuits Conference (CICC'11), San Jose, Ca., USA, 2011
 
(434) Esteves J., Rufer L., Rehder G.P., Capacitive Microphone fabricated with CMOS MEMS Surface-Micromachining Technology, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'11), Aix-en Provence, France, 2011
 
(435) Ouchet F., Morin-Allory K., Fesquet L., C-elements for hardened self-timed circuits, 21st International Workshop Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), Madrid, Spain, 2011
 
(436) Zimouche H., CMOS image sensors insensitive to temperature variations, These de Doctorat, 2011
 
(437) Beyrouthy T., Greitans M., Fesquet L., Shavelis R., Combined Peak and Level-Crossing Sampling Scheme, 9th International Conference on Sampling Theory and Applications (SampTA), Singapore, 2011
 
(438) Abdallah L., Stratigopoulos H., Mir S., Conception et évaluation d’une technique de test pour un mélangeur RF, Journées GDR SoC-SiP, Lyon, France, 2011
 
(439) Fesquet L., Hamon J., Configurable Self-Timed Ring Oscillators, 9th IEEE International NEWCAS Conference, Bordeaux, France, 2011
 
(440) Anghel L., Benabdenbi M., Pasca V., Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis , IEEE Latin America Test Symposium Workshop (LATW’11), Porto de Galinhas (PE), Brazil, 2011
 
(441) Alleysson D., Sicard G., Contrôle Contraste Local, 1158472, 2011
 
(442) Maistri P., Countermeasures against fault attacks: The good, the bad, and the ugly , IEEE International On-line Testing Symposium (IOLTS'11), Athens, Greece, 2011
 
(443) Leveugle R., Ferron J.B., Anghel L., Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results, Workshop on Design for Reliability and Variability (DRVW’11), Dana Point, CA, USA, 2011
 
(444) Hassan K., Customizable Memory Controller Architecture and Service Continuity for Off-Chip SDRAM Access in NoC-Based MPSoCs, These de Doctorat, 2011
 
(445) Alhakim R., Serrestou Y., Simeu E., Raoof K., Data-aided timing estimation in UWB communication systems using dirty templates, IEEE International Conference on Ultra Wideband (ICUWB’11), Bologna, Italy, 2011
 
(446) Defosseux M., Design and characterization of piezoelectric micro-harvesters for autonomous microsystems, These de Doctorat, 2011
 
(447) Defosseux M., Ivaldi P., Defay E., Basrour S., Allain M., Design, fabrication and characterization of wideband piezoelectric energy harvesters?, International Conference Piezo 2011-Electroceramics for End-users VI, Sestriere, Italy, 2011
 
(448) Fesquet L., Zakaria H., Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs , IEEE Journal on Emerging and Selected Topics in Circuits and Systems , 1, page: 160 - 172 , 2011
 
(449) Huard V., Anghel L., Designing cost-effective robust systems by accurate reliability modeling, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’11), Vancouver, Canada, 2011
 
(450) Nicolaidis M., Designing Single-Chip Massively Parallel Tera-Device Processors: Towards the Terminator Chip, Keynote in Opening Session at 29th IEEE VLSI TEST SYMPOSIUM (VTS’11), Dana Point,California, USA, 2011
 
(451) Arthaud Y., Design of a monitoring MEMS sensor for middle ear surgery, These de Doctorat, 2011
 
(452) Ghandour S., Design of MEMS based DC/DC converters, These de Doctorat, 2011
 
(453) Basrour S., Moreau-Gaudry A., Yang W., Bonvilain A., Alonso T., Développement de microjauges pour détecter la déformée des instruments médicaux percutanés, Colloque national sur la Recherche en Imagerie et Technologies pour la Santé (RITS’11), Rennes, 2011
 
(454) Stratigopoulos H., Mir S., Huang K., Diagnostic de fautes de circuits analogiques basé sur l’estimation non paramétrique de densité , Journées GDR SoC-SiP, Lyon, France, 2011
 
(455) Simeu-Abazi Z., Gascard E., Chalagiraud F., Diagnostic of discrete event systems using timed automata in Matlab Simulink, European Safety and Reliability Conference (ESREL'11), Troyes, France, 2011
 
(456) Fesquet L., Porcher A., Morin-Allory K., Does Asynchronous technology bring robustness in synchronous circuit monitoring?, Forum on specification & Design Languages (FDL’11), Oldenburg, Germany, 2011
 
(457) Ferro L., Pierre L., Dynamic Verification of SystemC Transactional Models, Model-Based Testing for Embedded Systems , CRC Press, Chapter 22, 2011
 
(458) Pétrot F., Coppola M., Locatelli R., Hassan K., EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip, Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC '11), Heraklion, Greece, 2011
 
(459) Velazco R., Effects of Radiation on Integrated Circuits : origines, mitigation techniques, test and real-life experiments, Conférence magistrale in Congreso de Informática Univ. Tecnológica de Machala (III CIU/), Machala (Equateur), 2011
 
(460) Nicolaidis M., Zergainoh N.-E., Anghel L., Yu H., Efficient Fault Dectection Architecture Design of Latch-based Low Power DSP/MCU Processor, ISRN: TIMA-RR--2011/01--FR, 2011
 
(461) Anghel L., Zergainoh N.-E., Yu H., Nicolaidis M., Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor , 16th IEEE European Test Symposium (ETS'11),Trondheim, Norway, 2011
 
(462) Thuaire A., Arnaud L., Frank T., Moreau S., Anghel L., Chappaz C., Leduc P., Lorut F., Electromigration Behavior of 3D-IC TSV, Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC, Anaheim, USA, 2011
 
(463) Bonnoit T., Nicolaidis M., Zergainoh N.-E., Eliminating speed penalty in ECC protected memories , Design Automation and Test in Europe Conference (DATE’11), Grenoble, France, 2011
 
(464) Bounceur A., Stratigopoulos H., Mir S., Estimation of Analog Parametric Test Metrics Using Copulas, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30, page: 1400-1410, 2011
 
(465) Stratigopoulos H., Dubois M., Mir S., Laraba A., Evaluation de la technique de test basée sur la mesure d’un nombre réduit de codes pour les convertisseurs analogique-numérique de type pipeline, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’11), Rennes, France, 2011
 
(466) Beznia K., Euler R., Bounceur A., Mir S., Evaluation d’un BIST d’un capteur de vision CMOS à base d’une copule non Gaussienne, Journées GDR SoC-SiP, Lyon, France, 2011
 
(467) Guibbaud N., Leveugle R., Carriere T., Buard N., Bougerol A. , Miller F., Experimental demonstration of pattern influence on DRAM SEU and SEFI radiation sensitivities, IEEE Transactions on Nuclear Science, 58, part 2, page: 1032-1039, 2011
 
(468) Lamraoui H., Mozer P., Bonvilain A., Cinquin Ph., Expérimentations d’un Sphincter Urinaire Artificiel Actif : résultats et perspectives, Colloque national sur la Recherche en Imagerie et Technologies pour la Santé (RITS’11), Rennes, 2011
 
(469) Younes J., Simeu-Abazi Z., Gascard E., Exploitation of built in test for diagnosis by using Dynamic Fault Tree: Implementation in Matlab Simulink, European Safety and Reliability Conference (ESREL’11), Troyes, France, 2011
 
(470) Simeu-Abazi Z., Gascard E., Exploitation of Built in test for diagnosis by using Dynamic Fault Trees: Implementation in Matlab Simulink, Advances in Safety, Reliability and Risk Management: ESREL 2011, CRC Press, 436-444, 2011
 
(471) Bougerol A. , Failure modes induced by natural radiation environment on DRAM memories: study, test methodology and mitigation technique, These de Doctorat, 2011
 
(472) Hedde D., Pétrot F., Fast Memory Consistency Analysis using Non-Intrusive Simulation Traces, The 2011 System, Software, SoC and Silicon Debug Conference (S4D), Munich, Germany, 2011
 
(473) Huang K., Fault modeling and diagnosis for nanometric mixed-signal/RF circuits, These de Doctorat, 2011
 
(474) Ouchet F., Yan C., Fesquet L., Morin-Allory K., Formal Verification of C-element Circuits, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’11), Ithaca (NY), 2011
 
(475) Tan J., Fresse V., Rousseau F., Generation of emulation platforms for NoC exploration on FPGA , International Symposium on Rapid System Prototyping (RSP’11), Karlshrue, Germany, 2011
 
(476) Maistri P., Canivet G., Leveugle R., Clédière J., Valette F., Renaudin M., Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA, Journal of Cryptology, 24, page: 247-268, 2011
 
(477) Pétrot F., Gligor M., Handling dynamic frequency changes in statically scheduled cycle-accurate simulation, 16th Asia and South Pacific Design Automation Conference (ASP-DAC’11), Yokohama, 2011
 
(478) Chefi A., Sicard G., Soudani A., Hardware compression solution based on HWT for low power image transmission in WSN, 23rd IEEE International Conference on Microelectronics (ICM'11), Hammamet, Tunisia, 2011
 
(479) Allain M., Defosseux M., Defay E., Ivaldi P., Basrour S., Highly efficient piezoelectric micro harvester for low level of acceleration fabricated with a CMOS compatible process, 16th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers’11), Beijing, China, 2011
 
(480) Civet Y., Icard B., Carpentier JF., Bustos J., Leverd F., Mercier D., Basrour S., Casset F., Holed MEM Resonators for High Accuracy Frequency Trimming , European Conference on sensors, actuators and microsystems (Eurosensors’11), Athens, Greece, 2011
 
(481) Civet Y., Carpentier JF., Icard B., Bustos J., Casset F., Mercier D., Leverd F., Basrour S., Holed MEM Resonators with High Aspect Ratio, for High Accuracy Frequency Trimming , European Solid-State Device Research Conference (ESSDERC'11), Helsinki, Finland, 2011
 
(482) Civet Y., Basrour S., Leverd F., Casset F., Bustos J., Carpentier JF., Icard B., Mercier D., Holed MEMS resonators with High aspect ratio and frequency compensated, 22nd Micromechanics and Micro systems Europe Workshop (MME’11), Tonsberg, Norway, 2011
 
(483) Nicolaidis M., Pasca V., Anghel L., I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems , 16th IEEE European Test Symposium (ETS'11), Trondheim, Norway, 2011
 
(484) Leveugle R., Bergaoui S., Impact of software optimization on variable lifetimes in a microprocessor-based system, IEEE International Symposium on Electronic Design, Test and Applications (DELTA'11), Queenstown, New Zealand, 2011
 
(485) Masson F., Leveugle R., Maistri P., Implementation of the Advanced Encryption Standard on GPUs with the NVIDIA CUDA framework, IEEE Symposium on Industrial Electronics9-28, 2011
 
(486) Mir S., Abdallah L., Stratigopoulos H., Implicit Test of High-Speed Analog Circuits Using Non-Intrusive Sensors, IEEE European Conference on Circuit Theory and Design (ECCTD’11), Linköping, Sweden, 2011
 
(487) Damri L., Pierre L., Improvement of Assertion-Based Verification through the Generation of Proper Test Sequences, Forum on specification & Design Languages (FDL'11), Oldenburg, Germany, 2011
 
(488) Velazco R., Mansour W., Pancher F., Costa-Marques G., Sohier D., Bui A., Improving SEU fault tolerance capabilities of a self-converging algorithm, European Conference on Radiation Effects on Component and Systems (RADECS’11), Sevilla, Spain, 2011
 
(489) Bousquet L., Simeu E., Including power consumption information in SystemC-AMS modeling of linear analog blocks at LSF MoC Level, Journées GDR SoC-SiP, Lyon, France, 2011
 
(490) Bousquet L., Simeu E., Cenni F., Inclusion of Power Consumption Information in High-Level Modeling of Linear Analog Blocks , Journal of Low Power Electronics (JOLPE), 7, page: 541-551, 2011
 
(491) Hubert G., Artola L., Nuns T., Guerard B., Peronnard P., Mansour W., Bezerra F., Pancher F., Velazco R., Duzellier S., In Flight SEU/MCU Sensitivity of Commercial Nanometric SRAMs: Operational Estimations , IEEE Transactions on Nuclear Science, 58, page: 2644 - 2651 , 2011
 
(492) García-Cámara B., Ayala J.L., Ruggiero M., Prieto M., Sicard G., Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings, Springer , 350 p., 2011
 
(493) Peronnard P., Foucard G., Velazco R., Integrated circuit qualification for Space and Ground-level Applications: Accelerated test and Error-Rate Prediction, Soft Errors in modern electronic systems, Springer , 167-202, 2011
 
(494) Waltisperger G., Integrated power management architectures for autonomous microsystems, These de Doctorat, 2011
 
(495) Raoof K., Simeu E., Alhakim R., Internal model control for a self-tuning Delay-Locked Loop in UWB communication systems , 17th IEEE International On-Line Testing Symposium (IOLT’11), Athens, Greece, 2011
 
(496) Greiner A., Refauvelet D., Benabdenbi M., Pecheux F., Zhang Z., Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure, 29th IEEE VLSI Test Symposium (VTS’11), Dana Point,California, USA, 2011
 
(497) Yu H., Low-Cost Highly-Efficient Fault Tolerant Processor Design for Mitigating the Reliability Issues in Nanometric Technologies, These de Doctorat, 2011
 
(498) Godezt-Bar G., Chen Hui, Rousseau F., Pétrot F., Me3D: A model-driven methodology expediting embedded device driver development , 22nd IEEE International Symposium on Rapid System Prototyping (RSP’11), Karlsruhe, Germany, 2011
 
(499) Fradi A., Nicolaidis M., Anghel L., Memory BIST with address programmability , IEEE international On Line Testing Symposium (IOLTS'11), Athenes, Greece, 2011
 
(500) Basrour S., Carpentier JF., Casset F., Civet Y., Method of adjusting the resonance frequency of a micro-machined element, 11/52729, 2011
 
(501) Dubois M., Methodology for test metrics estimation - Application to a new BIST for sigma-delta converters, These de Doctorat, 2011
 
(502) Houssany S., Guibbaud N., Leveugle R., Miller F., Buard N., Bougerol A. , Microprocessor soft error rate prediction based on cache memory analysis, 12th European Conference on Radiation and its Effects on Components and Systems (RADECS'11), Sevilla, Spain, 2011
 
(503) Yang W., Microsystem design and integration on a cylinder for strain measurement: application to a medical instrument, These de Doctorat, 2011
 
(504) Vittoz S., Modelling and test of integrated mechanical sensors based on AlGaN/GaN heterostructures for harsh environments, These de Doctorat, 2011
 
(505) Mir S., Abdallah L., Stratigopoulos H., Moniteurs embarqués pour le test à bas coût d’un front-end RF, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’11), Rennes, France, 2011
 
(506) Foucard G., Azambuja J.R., Pagliarini S., Altieri M., Lima Kastensmidt F., Hübner M., Velazco R., Non-Intrusive Reconfigurable HW/SW Fault Tolerance Approach to Detect Transient Faults in Microprocessor Systems, 12th European Conference on Radiation and its Effects on Components and Systems (RADECS’11), Sevilla, Spain, 2011
 
(507) Bidegaray-Fesquet B., Fesquet L., Non-Uniform Filter Design in the Log-Scale, 9th International Conference on Sampling Theory and Applications (SampTA), Singapore, 2011
 
(508) Bidegaray-Fesquet B., Fesquet L., Non-uniform Filter interpolation in the frequency domain, An International Journal on Sampling Theory in Signal and Image Processing (STSIP), 10, page: 17-35, 2011
 
(509) Basrour S., Carpentier JF., Casset F., Civet Y., Numerical and analytical modelling of holed MEMS resonators, Sensors and Actuators A : Physical, , page: 6 p, 2011
 
(510) Vivet P., Beigné E., Lebreton H., Zergainoh N.-E., On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling, Journal of Low Power Electronics (JOLPE), 7, page: 265-273, 2011
 
(511) Hamayun M.M., Gligor M., Shen H., Fournel N., Gerin P., Pétrot F., On MPSoC Software Execution at the Transaction Level, IEEE Design and Test of Computers, 28, page: 32-43, 2011
 
(512) Drineas P., Kupp N., Stratigopoulos H., Makris Y., On Proving the Efficiency of Alternative RF Tests, IEEE/ACM International Conference on Computer-Aided Design (ICCAD'11), San Jose, CA, USA, 2011
 
(513) Abdallah L., Stratigopoulos H., Mir S., Spyronasios A., On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study, IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011
 
(514) Nicolaidis M., Anghel L., Pasca V., On the dependability of 3D interconnects, Keynote in Opening Session at Dependability Issues in Deep-submicron Technologies Workshop (DDT’11), European Test Symposium (ETS), Trondheim, Norvège, 2011
 
(515) Nicolaidis M., On the State of Superposition and the Parallel or not Parallel Nature of Quantum Computing: a controversy raising point of view, AISB’11 Convention, York, UK, 2011
 
(516) Akkouche N., Optimisation of the production test of analog and RF circuit using statistical modeling techniques, These de Doctorat, 2011
 
(517) Akkouche N., Optimization of production test of analog and RF circuits using statistical modeling techniques, PhD Forum at IEEE Design, Automation and Test in Europe Conference, Grenoble, 2011
 
(518) Beznia K., Euler R., Bounceur A., Mir S., Parametric test metrics estimation using non-Gaussian copulas, IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW’11), Santa Barbara, California, USA, 2011
 
(519) Ferreyra P., Velazco R., Marques C.A., Sanchez A.E., Performance de Computadoras SIMD Implementadas en FPGAs, XVII IBERCHIP workshop, Bogotá, Colombie, 2011
 
(520) Vivet P., Pétrot F., Darve F., Sheibanyrad H., Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'11), Chennai, 2011
 
(521) Stratigopoulos H., Drineas P., Kupp N., Makris Y., PPM-Accuracy Error Estimates for Low-Cost Analog Test: A Case Study, IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW’11), Santa Barbara, California, USA, 2011
 
(522) Brinkfeldt K., Vanko G., Lalinsky T., Rufer L., Edwards M.J., Le Boulbar E., Johander P., Vittoz S., Allsopp D.W.E., Bowen C.R., Pressure and temperature dependence of GaN/AlGaN HEMT based sensors on a sapphire membrane, 9th International Conference on Nitride Semiconductors (ICNS’11), Glasgow, UK, 2011
 
(523) Fesquet L., Zakaria H., Process variability robust energy-efficient control for nano-scaled complex SoCs , 10th Edition of Faible Tension Faible Consommation (FTFC’11), Marrakech, Morocco, 2011
 
(524) Velazco R., Peronnard P., Foucard G., Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions, JETTA - Journal of Electronic Testing: Theory and Application, 27, page: , 2011
 
(525) Arnaud L., Lorut F., Moreau S., Thuaire A., El Farhane R., Anghel L., Chappaz C., Leduc P., Frank T., Resistance Increase Due to Electromigration Induced Depletion Under TSV , IEEE International Reliability Physics Symposium (IRPS’11), Monterey, CA, USA, 2011
 
(526) Abdallah L., Stratigopoulos H., Mir S., Kelma C., RF Front-End Test Using Built-in Sensors , IEEE Design and Test of Computers, 28, page: 76-84, 2011
 
(527) Fesquet L., Elissati O., Rieubon S., Ring Oscillators : The Asynchronous Alternative, 10th Edition of Faible Tension Faible Consommation (FTFC’11), Marrakech, Morocco, 2011
 
(528) Ouchet F., Robustness analysis and improvement of QDI self-timed circuits, These de Doctorat, 2011
 
(529) Foucard G., Bui A., Velazco R., Pancher F., Mansour W., Costa-Marques G., Sohier D., Robustness with respect to SEUs of a self-converging algorithm, IEEE Latin America Test Symposium Workshop (LATW’11), Porto de Galinhas (PE), Brazil, 2011
 
(530) Lefftz V., Bel Hadj Amor Z., Pierre L., Ferro L., Lachaize J., Runtime Verification of Typical Requirements for a Space Critical SoC Platform, Proc. 16th International Workshop on Formal Methods for Industrial Critical Systems (FMICS’11), Trento (Italy), 2011
 
(531) Fesquet L., Torresani B., Sampling Theory in Signal and Image Processing, Sampling Publishing ISSN: 1530-6429, Vol. 10, N°1-2, 2011
 
(532) Yahya E., Zakaria H., Fesquet L., Self Adaption in SoCs, Autonomic Networking-on-Chip (Bio-inspired Specification, Development, and Verification), CRC Press, 287p, 2011
 
(533) Bizot G. , Avresky D., Zergainoh N.-E., Nicolaidis M., Chaix F., Self-Recovering Parallel Applications in Multi-Core Systems, 10th IEEE International Symposium on Network Computing and Applications (NCA’11), Cambridge, MA, USA, 2011
 
(534) Elissati O., Self-Timed Ring Oscillators : from theory to practice, These de Doctorat, 2011
 
(535) Rousseau F., Chagoya-Garzon A., Poste N., Semi-Automation of Configuration Files Generation for Heterogeneous Multi-Tile Systems, Computer Software and Application Conference (COMPSAC’11), Munich, Germany, 2011
 
(536) Amhaz H., Zimouche H., Sicard G., Smart Readout Technique based on Temporal Redundancies Suppression Designed for Logarithmic CMOS Image Sensor, International Image Sensor Workshop (IISW’11), Hokkaido, Japan, 2011
 
(537) Zimouche H., Sicard G., Amhaz H., Smart readout technique designed for logarithmic CMOS image sensor including a motion detection scheme, 9th IEEE International Conference on New Circuits and Systems (NEWCAS’11), Bordeaux, France, 2011
 
(538) Mir S., SoC for biomedical applications: trends and challenges, 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Hong-Kong, 2011
 
(539) Velazco R., Soft-error-rate prediction for programmable circuits: methodology, tools and studied cases , Conférence magistrale in Congreso Internacional de Ingenieria Eléctrica, Electrónica, Sistemas y Ramas Afines (XVIII INTERCON), Lima, Perou, 2011
 
(540) Nicolaidis M., Soft Errors in modern electronic systems, Springer , 368 p. 59 illus., 2011
 
(541) Michel L., Fournel N., Pétrot F., Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation , Design Automation and Test in Europe Conference (DATE’11), Grenoble, France, 2011
 
(542) Coppola M., Dubois F., Pétrot F., Cano J., Flich J., Spidergon STNoC design flow , IEEE/ACM International Symposium on Networks on Chip (NoCS’11), Pittsburg, Pa., USA, 2011
 
(543) Stratigopoulos H., Statistical Learning for Analog Circuit Testing, Conference on International Design & Technology of Integrated Systems in Nanoscale Era (DTIS’11), Athens, Greece, 2011
 
(544) Bonvilain A., Gustavo F., Basrour S., Yang W., Strain microgauge implementation on cylindrical metal substrates, 37th International Conference on Micro and Nano Engineering (MNE’11), Berlin, Germany, 2011
 
(545) Vittoz S., Rufer L., Rehder G.P., Srnanek R., Kovac J., Study of built-in stress distribution in AlGaN/GaN/AlN heterostructure based cantilevers for mechanical sensing in harsh environments , 4th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI’11), Borgo Egnazia Savelletri di Fasano, Brindisi, Italy, 2011
 
(546) Fesquet L., Porcher A., Morin-Allory K., Synthesis of Quasi Delay Insensitive Monitors, 7th Conference on PhD Research in Microelectronics and Electronics (PRIME’11), Madonna Di Campiglio (Trento), Italy, 2011
 
(547) Scotti S., Simeu E., Cenni F., SystemC-AMS behavioral modeling of a CMOS video sensor, 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC’11),Hong Kong, China, 2011
 
(548) Bousquet L., Cenni F., Simeu E., SystemC-AMS high-level modeling of linear analog blocks with power consumption information, IEEE 12th IEEE Latin American Test Workshop (LATW’11), Porto de Galinhas, Brazil, 2011
 
(549) Cenni F., Scotti S., Simeu E., SystemC-AMS model of a CMOS video sensor. Open SystemC Initiative (OSCI) , SystemC AMS Day 2011: Industry Adoption of the SystemC AMS Standard, Dresden, Germany, 2011
 
(550) Pétrot F., Meunier Q., Systèmes de mémoire transactionnelle pour les architectures à base de NoC Conception, implémentation et comparaison de deux politiques, Technique et Science Informatiques (TSI), 30/9 , page: 1061-1087, 2011
 
(551) Amhaz H., Zimouche H., Sicard G., Temperature compensated logarithmic CMOS image sensor using CMOS voltage reference Bandgap method , 9th IEEE International Conference on New Circuits and Systems (NEWCAS’11), Bordeaux, France, 2011
 
(552) Zimouche H., Amhaz H., Temperature Compensation Scheme for Logarithmic CMOS Image Sensor, International Image Sensor Workshop (IISW’11), Hokkaido, Japan, 2011
 
(553) Dubois M., Test metrics estimation of complex analog and mixed-signal circuits at the design stage, PhD Forum at IEEE Design, Automation and Test in Europe Conference, Grenoble, 2011
 
(554) Fesquet L., Thinking and Designing Differently: The Asynchronous Alternative, Dresden Microelectronic Academy, Dresden, Germany, 2011
 
(555) Leblond N., Porcher A., Fesquet L., Tiempo Asynchronous Design Flow Tutorial - Modeling and Debug, Design Automation Conference (DAC’11), San Diego, USA, 2011
 
(556) Bonnoit T., Nicolaidis M., Zergainoh N.-E., Towards a Tool for Implementing Delay-Free ECC in Embedded Memories, IEEE International Conference on Computer Design (ICCD’11), Amherst, Ma, USA, 2011
 
(557) Clavel R., Pierre L., Leveugle R., Towards Robustness Analysis using PVS, Proc. Conference on Interactive Theorem Proving (ITP’11), Nijmegen, Netherlands, 2011
 
(558) Leveugle R., Ben Jrad M., Maistri P., Towards Virtual Fault-based Attacks for Security Validation, IARIA Fourth International Conference on Dependability (DEPEND'11), Nice/Saint Laurent du Var, France, 2011
 
(559) Shen H., Pétrot F., Using Amdahl’s Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric Processors , Architecture of Computing Systems - ARCS 2011, Springer , 38-49, 2011
 
(560) Pétrot F., Utilisation de techniques de traduction binaire dynamique pour la simulation rapide et précise des MPSoCs, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (Fetch'11), Quebec, Canada, 2011
 
(561) Chaix F., Zergainoh N.-E., Bizot G. , Nicolaidis M., Variability-aware task mapping strategies for many-cores processor chips , IEEE International On-line Testing Symposium (IOLTS'11), Athens, Greece, 2011
 
(562) Chaix F., Zergainoh N.-E., Bizot G. , Nicolaidis M., Variability-aware Task mapping strategies for Many-cores processor chips, Workshop on Design for Reliability and Variability (DRVW’11), Dana Point, CA, USA, 2011
 
(563) Ferro L., Verification of temporal properties for SystemC TLM specifications, These de Doctorat, 2011
 
(564) Zhou Z., Rufer L., Wong M., Wide-Band Piezoresistive Aero-Acoustic Microphone, 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC’11), Hong Kong, China, 2011
 
(565) Heinrich V., Sicard G., Jain A., Roche P., Veggetti A., Crippa D., Clerc S., Abouzeid F., A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder, IEEE International Conference on Integrated Circuit Design and Technology (ICICDT’10), Grenoble, France, 2010
 
(566) Asquini A., A BIST technique for RF frequency synthesizers, These de Doctorat, 2010
 
(567) Stratigopoulos H., Adaptive analog test: feasibility and opportunities Ahead, 28th IEEE VLSI Test Symposium (VTS'10), Santa Cruz, USA, 2010
 
(568) Khereddine R., Abdallah L., Cenni F., Simeu E., Mir S., Adaptive Logical Control of RF LNA performances for efficient energy consumption, 18th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Madrid, 2010
 
(569) Bertrand J., Cassé H., Clienti C., Coussy P., Maillet-Contoz L., Mercier P., Moreau P., Pierre L., Vaumorin E., Lefftz V., A Design Flow for Critical Embedded Systems, Proc. IEEE Symposium on Industrial Embedded Systems (SIES’10), Trento, Italy, 2010
 
(570) Borrione D., Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's, Springer , 246 p., 2010
 
(571) Shen H., Pétrot F., A flexible hybrid simulation platform targeting multiple configurable processors SoC, IEEE Asia South-Pacific Design Automation Conference (ASP-DAC’10),Taipei, Taiwan, 2010
 
(572) Amhaz H., Sicard G., A high output voltage swing logarithmic image sensor designed with on chip FPN reduction, 6th IEEE Conference on Ph.D. Research in Microelectronics & Electronics (PRIME'10), Berlin, Germany, 2010
 
(573) Elissati O., Yahya E., Rieubon S., Fesquet L., A High-Speed High-Resolution Low-Phase Noise Oscillator Using Self-Timed Rings, 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'10), Madrid, Spain, 2010
 
(574) Maliuk D., Stratigopoulos H., Huang K., Makris Y., Analog neural network design for RF built-in self-test, IEEE International Test Conference (ITC), Austin, TX, USA, 2010
 
(575) Stratigopoulos H., Mir S., Analog test metrics estimates with PPM accuracy, IEEE/ACM International Conference on Computer-Aided Design (ICCAD'10), San Jose, CA, USA, 2010
 
(576) Rufer L., Rehder G.P., Benkart P., Vittoz S., Heinle U., Analytical and numerical modeling of AlGaN/GaN/AlN heterostructure based cantilevers for mechanical sensing in harsh environments, European Conference on sensors, actuators and microsystems (Eurosensors'10), Linz, Austria, 2010
 
(577) Guérin X., An efficient embedded software development approach for multiprocessor system-on-chips, These de Doctorat, 2010
 
(578) Vanhauwaert P., Bergaoui S., Leveugle R., A new critical variable analysis in processor-based systems, IEEE Transactions on Nuclear Science, 57, part 1, page: 1992-1999, 2010
 
(579) Ben Jrad M., Leveugle R., A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Athens, Greece, 2010
 
(580) Gligor M., Pétrot F., Fournel N., Annotation within dynamic binary translation for fast and accurate system simulation, 10th International Forum on Embedded MPSoC and Multicore (MPSoc'10), Gifu, Japan, 2010
 
(581) Hedde D., Pétrot F., A Non-Intrusive Simulation-Based Trace System for Fine-Grain Analysis of Multiprocessor Systems-on Chips Software , The 2011 System, Software, SoC and Silicon Debug Conference (S4D), Southampton, UK, 2010
 
(582) Alhakim R., Raoof K., Simeu E., A Novel Fine Synchronization Method for Dirty Template UWB Timing Acquisition, Wireless Communications Networking and Mobile Computing (WiCOM), 6th International Conference, Chengdu , China, 2010
 
(583) Rieubon S., Yahya E., Fesquet L., Elissati O., A novel High-Speed Multi-Phase Oscillator on Asynchronous Rings, IEEE International Conference on Microelectronics ICM’2010, Cairo, Egypte, 2010
 
(584) Sicard G., Labonne E., Rolland R., A Standard 3.5T CMOS Imager Including a Light Adaptive System for Integration Time Optimization , Algorithm-Architecture Matching for Signal and Image Processing , Springer , 81-93, 2010
 
(585) Renaudin M., Sicard G., Kastensmidt F., Possamai Bastos R., Reis R., Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies , Microelectronics and Reliability, 50, page: 1241-1246, 2010
 
(586) Possamai Bastos R., Renaudin M., Sicard G., Kastensmidt F., Reis R., Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies , 15th IEEE European Test Symposium (ETS’10), Prague, Czecoslovaquia, 2010
 
(587) Possamai Bastos R., Sicard G., Kastensmidt F., Renaudin M., Reis R., Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies , 21st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Monte Cassino Abbey and Gaeta, Italy, 2010
 
(588) Rahmouni K., à venir, These de Doctorat, 2010
 
(589) Huang K., Stratigopoulos H., Mir S., Bayesian fault diagnosis of RF circuits using nonparametric density estimation, IEEE Asian Test Symposium (ATS’10), Shanghai, China, 2010
 
(590) Stratigopoulos H., Kelma C., Mir S., Abdallah L., Capteurs embarqués pour le test alternatif des circuits RF, Journées GDR SoC-SiP, Paris, France, 2010
 
(591) Rusu C., Anghel L., Checkpoint and rollback recovery in network-on-chip based systems, Asia and South Pacific Design Automation Conference (ASP-DAC’10), Taipei, Taiwan, 2010
 
(592) Nicolaidis M., Circuit-level Soft-Error Mitigation, Soft Errors in Modern Electronic Systems, Springer , 203-252, 2010
 
(593) Chagoya-Garzon A., Communication synthesis in a binary code generation flow targeting heterogeneous multi-tile architectures, These de Doctorat, 2010
 
(594) Defosseux M., Basrour S., Allain M., Comparison of different beam shapes for piezoelectric vibration energy harvesting , The 10th International Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS’10), Leuven, Belgium, 2010
 
(595) Chaillout J.J., Jean-Mistral C., Basrour S., Comparison of electroactive polymers for energy scavenging applications , Smart Materials and Structures, 19, Number 8 , page: 085012, 2010
 
(596) Civet Y., Casset F., Basrour S., Carpentier JF., Compensation de la fréquence des résonateurs MEMS par ajustement in-line, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’10), Montpellier, France, 2010
 
(597) Nicolaidis M., Kolonis E., Computational Opportunities and CAD for Nanotechnologies, Robust Computing with Nano-scale Devices, Springer , 137-173, 2010
 
(598) Nicolaidis M., Computational Space, Time and Quantum Mechanics, Thinking Machines and the Philosophy of Computer Science: Concepts and Principles, IGI Global, Hershey, PA 17033, USA, 253-279, 2010
 
(599) Benabdenbi M., Pasca V., Anghel L., Rusu C., Configurable Fault-Tolerant Link for Inter-die Communication in 3D on-Chip Networks, European Test Symposium (ETS'10), Prague, Czech Republic, 2010
 
(600) Anghel L., Rusu C., Benabdenbi M., Pasca V., Configurable Serial Fault-Tolerant Link for Communication in 3D Integrated Systems, International On-Line Test Symposium (IOLTS'10), Corfu, Greece, 2010
 
(601) Pétrot F., Guironnet de Massas P., De l’accès transparent et optimisé aux données dans les systèmes multiprocesseurs intégrés, 4ème école d’hiver francophone sur les systèmes hétérogènes (FETCH'10), Chamonix, France, 2010
 
(602) Morin-Allory K., Fesquet L., Ouchet F., Delay Insensitivity Does Not Mean Slope Insensitivity!, IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), Grenoble, France, 2010
 
(603) Mir S., Stratigopoulos H., Bounceur A., Density estimation for analog/RF test problem solving, 28th IEEE VLSI Test Symposium, Santa Cruz, USA, 2010
 
(604) Canivet G., Maistri P., Leveugle R., Valette F., Renaudin M., Clédière J., Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA, International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), Rennes, France, 2010
 
(605) Despesse G., Ghandour S., Basrour S., Design and Control of a Zero Voltage Switching MEMS DC-DC Power Converter, Nanotech Conference & Expo 2010, Anaheim, Ca., USA, 2010
 
(606) Elmrabti A., Rousseau F., Pétrot F., Martin J., Lemaire R., Vaumorin E., Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms, International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS X), Samos, Greece, 2010
 
(607) Lamraoui H., Designing a system of active implantable urethral occlusion for the treatment of severe urinary incontinence, These de Doctorat, 2010
 
(608) Ghandour S., Despesse G., Basrour S., Design of a new MEMS DC/DC voltage step-down converter, 8th IEEE International NEWCAS Conference (NEWCAS), Montréal, Canada, 2010
 
(609) Cenni F., Rufer L., Mir S., Cazalbou J., Design of a SAW-based chemical sensor with its microelectronics front-end interface , Microelectronics journal, 41, page: 723-732, 2010
 
(610) Mozer P., Moreau-Gaudry A., Combrisson H., Basrour S., Bonvilain A., Robain G., Cinquin Ph., Lamraoui H., Development of a Novel Artificial Urinary Sphincter: A Versatile Automated Device , IEEE/ASME Transaction on Mechatronics, 15, page: 916 - 924 , 2010
 
(611) Huang K., Stratigopoulos H., Mir S., Diagnostic de fautes de circuits analogiques basé sur l’apprentissage automatique, Journées GDR SoC-SiP, Paris, France, 2010
 
(612) Basrour S., Chaillout J.J., Sylvestre A., Jean-Mistral C., Dielectric properties of polyacrylate thick films used in sensors and actuators, Smart Materials and Structures, 19, Number 10, July, page: 075019, 2010
 
(613) Leveugle R., Early robustness evaluation of digital integrated systems, 13th Forum for Design Languages (FDL), Southampton, UK, 2010
 
(614) Velazco R., Effects of natural radiation on integrated circuits: origins, mitigation techniques and experiments in the natural environment , Congreso Nacional de Estudiantes de Ingenieria Mecanica, Electronica Electrica, y Ramas Afines (CONEIMERA'10), Trujillo, Pérou, 2010
 
(615) Boussetta H., Soudani A., Basrour S., Marzencki M., Efficient Physical Modeling of MEMS Energy Harvesting Devices With VHDL-AMS, Sensors Journal , 10, Number 09, September, page: 1427 - 1437 , 2010
 
(616) Allain M., Pouteau P., Basrour S., Berthier J., Electrically actuated sacrificial membranes for valving in microsystems , Journal of Micromechanics and Microengineering, Vol. 20, page: 035006, 2010
 
(617) Popovici K., Rousseau F., Jerraya A. A., Wolf M., Embedded Software Design and Programming of Multiprocessor System-on-Chip: Simulink and SystemC Case Studies, Springer , 290 p., 2010
 
(618) Simeu E., Embedded Test and Control of Analogue/RF Circuits Using Intelligent Resources, 11th Latin America Test Workshop, Invited embedded tutorial, Punta del Este, Uruguay, 2010
 
(619) Ferro L., Pierre L., Enhancing the assertion-based verification of TLM designs with reentrancy, 8th IEEE/ACM International Conference Formal Methods and Models for Codesign (MEMOCODE'10), Grenoble, France, 2010
 
(620) Velazco R., Error Rate Predictions for Programmable Circuits: Methodology, Tools and Studied Cases, 9th RASEDA : International Workshop on Radiation Effects on Semiconductor Devices for Space Applications), Takasaki, Japan, 2010
 
(621) Anghel L., Rusu C., Locatelli R., Coppola M., Pasca V., Error Resilience of Inter-Die and Intra-Die Communication with 3D Spidergon STNoC, Design Automation and Test in Europe Conference, (DATE'10), Dresden, Germany, 2010
 
(622) Possamai Bastos R., Sicard G., Renaudin M., Reis R., Kastensmidt F., Evaluating transient-fault effects on traditional C-element's implementations, 16th IEEE International On-Line Testing Symposium, (IOLTS’10), Corfu island, Greece, 2010
 
(623) Dubois M., Stratigopoulos H., Mir S., Evaluation des métriques de test pour des circuits analogiques/mixtes complexes, Journées GDR SoC-SiP, Paris, France, 2010
 
(624) Abdallah L., Tongbong J., Mir S., Stratigopoulos H., Evaluation of built-in sensors for RF LNA response measurement, 16th IEEE International Mixed-signals, Sensors and Systems Test Workshop (IMS3TW), La Grande Motte, France, 2010
 
(625) Mir S., Stratigopoulos H., Dubois M., Bounceur A., Evaluation of parametric test metrics for mixed-signal/RF DFT solutions using statistical techniques, Catrene European Nanoelectronics Design Technology Conference, Grenoble, 2010
 
(626) Guironnet de Massas P., Pétrot F., Evaluation of the implementation cost of cache coherence protocols using omniscient actions , Design Automation for Embedded Systems, 14, page: 21-42, 2010
 
(627) Bougerol A. , Miller F., Buard N., Carriere T., Guibbaud N., Leveugle R., Experimental demonstration of pattern influence on DRAM SEU & SEFI radiation sensitivities, European Conference on Radiation and its Effects on Components and Systems (RADECS'10), Längelfeld, Austria, 2010
 
(628) Gligor M., Fast Simulation Strategies and Adaptive DVFS Algorithm for Low Power MPSoCs, These de Doctorat, 2010
 
(629) Stratigopoulos H., Mir S., Huang K., Fault diagnosis of analog circuits based on machine learning, Design, Automation and Test in Europe Conference (DATE’10), Dresden, Germany, 2010
 
(630) Pasca V., Anghel L., Benabdenbi M., Fault Resilient Intra-die and Inter-die Communication in 3D Integrated Systems, PhD Research in Microelectronics and Electronics Conference (PRIME'10), Berlin, Germany, 2010
 
(631) Pasca V., Anghel L., Benabdenbi M., Fault Tolerant Communication in 3D Integrated Systems, DSN Workshop on Dependable Systems and Networks (WDSN'10), Chicago, USA, 2010
 
(632) Chaix F., Avresky D., Zergainoh N.-E., Nicolaidis M., Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-Cores Systems, IEEE International Symposium on Network Computing and Applications (NCA'10), Cambridge, Ma., USA, 2010
 
(633) Ferro L., Pierre L., Formal Semantics for PSL Modeling Layer and Application to the Verification of Transactional Models , Design, Automation and Test in Europe (DATE'10), Dresden (Germany), 2010
 
(634) Casset F., Arcamone J., Niel A., Lorent E., Marcoux C., Civet Y., Durand C., Ollier E., Renaux Ph., Carpentier JF., Ancey P., Robert P., Frequency shift of MEMS electromechanical resonators induced by process variation, 21st Micromechanics and Microsystems Europe Workshop (MME’10), Enschede, The Netherlands, 2010
 
(635) Garcia-Valderas M., Nicolaidis M., Entrena L., Lopez-Ongil C., Portela-Garcia M., Hardware Fault Injection, Soft Errors in Modern Electronic Systems, Springer , 141-166, 2010
 
(636) Pétrot F., Roch J.-L., Meunier Q., Hardware/software support for adaptive work-stealing in on-chip multiprocessor, Journal of Systems Architecture (JSA), 56, page: 392-406, 2010
 
(637) Fesquet L., Bidegaray-Fesquet B., IIR digital filtering of non-uniformly sampled signals via state representation, International Journal of Signal Processing, 90, page: 2811-2821, 2010
 
(638) Hamon J., Fristot V., Rolland R., Implementation of a real time multi-resolution edge detection video filter, 8th European Workshop on Microelectronics Education (EWME’10), Darmstadt, Germany, 2010
 
(639) Helmy A., Implementation of automatic demonstration techniques for formal verification of NoCs, These de Doctorat, 2010
 
(640) Rahmouni K., Pétrot F., Improving the tests coverage of a medium voltage protection device using system simulation approaches, Proceedings of the IEEE Symposium on Industrial Embedded Systems (SIES’10), Trente, Italie, 2010
 
(641) Ben Jrad M., Leveugle R., Injection de fautes par reconfiguration partielle - Application à un FPGA Virtex II Pro, 13èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'10), Montpellier, France, 2010
 
(642) Marchand N., Fesquet L., Zakaria H., Durand S., Integrated Asynchronous Regulation for Nanometric Technologies, 1st IEEE European workshop on CMOS Variability (VARI'10), Montpellier, France, 2010
 
(643) Zimouche H., Sicard G., Integrated temperature compensation scheme for a standard linear CMOS vision sensor, 6th IEEE Conference on Ph.D. Research in Microelectronics & Electronics (PRIME 2010), Berlin, Germany, 2010
 
(644) Pasca V., Nicolaidis M., Anghel L., Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems, IEEE International On-Line Testing Symposium (IOLTS’10), Corfu, Greece, 2010
 
(645) Pierre L., Ferro L., ISIS: Runtime Verification of TLM Platforms, Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's (Selected Contributions from FDL'09), Springer , 213-226, 2010
 
(646) Pétrot F., Meunier Q., Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies, Journal of Parallel and Distributed Computing (JPDC), 70, page: 1024-1041, 2010
 
(647) Benech P., Ferrari P., Rehder G.P., Ligne de transmission haute fréquence accordable, Demande de brevet No 10/52067, 2010
 
(648) Ferro L., Pierre L., Logiciel, FR.001.500008.000.S.P.2010.000.31500, 2010
 
(649) Rehder G.P., Mir S., Rufer L., Simeu E., Nguyen H.N., Low Frequency Test for RF MEMS Switches, IEEE International Symposium on Electronic Design, Test and Applications (DELTA’10), Ho Chi Minh City, Vietnam, 2010
 
(650) Tounsi F., MEMS Electrodynamic Microphone in CMOS technology: design, modeling and realization, These de Doctorat, 2010
 
(651) Civet Y., Casset F., Carpentier JF., Decossas S., Haccart T., Basrour S., MEMS resonator frequency compensation by “in-line” trimming”, 11th International Symposium on RF MEMS and RF Microsystems (Memswave’10), Otranto, Italy, 2010
 
(652) Casset F., Durand C., Civet Y., Ollier E., Carpentier JF., Ancey P., Robert P., MEMS resonator temperature compensation, 11th International Conference on Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE 2010), Bordeaux, France, 2010
 
(653) Elmrabti A., Methods and tools for code generation for multi-core platforms based on high-level description of applications and architectures, These de Doctorat, 2010
 
(654) Rufer L., Vittoz S., Modélisation et caractérisation de capteurs mécaniques à base d’hétérostructures AlGaN/GaN pour environnements en conditions sévères, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'10), Montpellier, France, 2010
 
(655) Yang W., Bonvilain A., Basrour S., Modélisations et Expérimentations d’une Aiguille Médicale Instrumentée pour le Guidage de son Insertion , Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’10), Montpellier, France, 2010
 
(656) Bonvilain A., Alonso T., Moreau-Gaudry A., Basrour S., Yang W., Modelling and Characterization of an Instrumented Medical Needle in Sight of New Microsensor Design for its Insertion Guidance , 32nd Annual International Conference of the IEEE Engineering in Medicine and Biology (EMBC’10), Buenos Aires, Argentina, 2010
 
(657) Boussetta H., Modelling and global simulation of self powered microsystems, These de Doctorat, 2010
 
(658) Edwards M.J., Vittoz S., Amen R., Rufer L., Johander P., Bowen C.R., Allsopp D.W.E., Modelling and optimisation of a sapphire/GaN-based diaphragm structure for pressure sensing in harsh environments, 8th International Conference on Advanced Semiconductor Devices Microsystem (ASDAM'10), Smolenice, Slovakia, 2010
 
(659) Jean-Mistral C., Basrour S., Chaillout J.J., Modelling of dielectric polymers for energy scavenging applications , Smart Materials and Structures, 19, Number 10, October, page: 105006, 2010
 
(660) Rusu C., Multi-Level Fault-Tolerance in Networks-on-Chip, These de Doctorat, 2010
 
(661) Pasca V., Anghel L., Rusu C., Benabdenbi M., Non-regular 3D mesh Networks-on-Chip, DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10), Anaheim, USA, 2010
 
(662) Bergaoui S., Leveugle R., Nouvelle méthode de vérification de flot de contrôle avec signatures disjointes, 13èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'10), Montpellier, France, 2010
 
(663) Stratigopoulos H., On-Line monitoring for analog and sensor-based systems, 16th IEEE International On-Line Testing Symposium (IOLTS'10), Corfy, Greece, 2010
 
(664) Guérin X., Pétrot F., Operating System Support for Applications targeting Heterogeneous Multi-Core System-on-Chips, Multi-Core Embedded Systems , CRC Press, chapter 9, 24 p., 2010
 
(665) Rieubon S., Fesquet L., Yahya E., Elissati O., Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Springer , 137–149, 2010
 
(666) Elissati O., Yahya E., Rieubon S., Fesquet L., Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case , International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2010), Grenoble, France, 2010
 
(667) Akkouche N., Mir S., Simeu E., Ordering of analog specification tests based on parametric defect level estimation, 28th IEEE VLSI Test Symposium, Santa Cruz, USA, 2010
 
(668) Baghdadi A., Jézéquel M., Muller O., Parallelism Efficiency in Convolutional Turbo Decoding, Eurasip Advances in Signal Processing, vol. 2010, Article ID 927920, page: 11 pages, 2010
 
(669) Basrour S., Waltisperger G., Condemine C., Photovoltaic energy harvester for micro-scale applications, 8th IEEE International NEWCAS conference. Montréal, Canada, 2010
 
(670) Foucard G., Radiation error rate for applications implemented in SRAM-based FPGA: prediction versus measures, These de Doctorat, 2010
 
(671) Robain G., Mozer P., Moreau-Gaudry A., Cinquin Ph., Gumery P.-Y., Basrour S., Lamraoui H., Bonvilain A., Rectus Abdominis Electromyography and Mechanomyography Comparison for the Detection of Cough, 32nd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Buenos Aires, Argentina, 2010
 
(672) Frank T., Chappaz C., Leduc P., Arnaud L., Moreau S., El Farhane R., Anghel L., Thuaire A., Reliability approach of high density Through Silicon Via (TSV), 12th Electronics Packaging Technology Conference (EPTC’10), Singapore, 2010
 
(673) Slamani M., Drineas P., Makris Y., Stratigopoulos H., RF Specification Test Compaction Using Learning Machines, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, page: 998 - 1002 , 2010
 
(674) Anghel L., Avresky D., Rusu C., RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip, International On-Line Test Symposium (IOLTS’10), Corfu, Greece, 2010
 
(675) Valette F., Clédière J., Renaudin M., Canivet G., Maistri P., Leveugle R., Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA, IEEE European Test Symposium, Prague, Czech Republic, 2010
 
(676) Dettenborn R., RTL Analysis Based on Signal Reliability , IVième Colloque national du GDR SoC-SiP, Paris-Cergy, France, 2010
 
(677) Abdallah L., Stratigopoulos H., Kelma C., Mir S., Sensors for built-in alternate RF test, IEEE European Test Symposium (ETS’10), Prague, Czech Republic, 2010
 
(678) Nicolaidis M., Simulating Time with Computers, North American Computing And Philosophy Conference (NACAP’10), Carnegie Mellon University, Pittsburgh, Pennsylvania, 2010
 
(679) Nicolaidis M., Kolonis E., Simulating Time with Computers: implementation and experimentations, 8th European Conference on Computing and Philosophy (ECAP’10), Munich, Germany, 2010
 
(680) Velazco R., Single Events on Digital Integrated Circuits , Bolivian Engineering and Technology Congress (BETCON'10), La Paz, Bolivia, 2010
 
(681) Sicard G., Zimouche H., Standard Linear CMOS Image Sensor Insensitive to Temperature Variations, The 8th IEEE International NEWCAS 2010 Conference, Montreal, Canada, 2010
 
(682) Barbut L., Serbutoviez C., Coppard R., Chartier I., Gwoziecki R., Sicard G., Frere P., Tallal J., Heitzman M., Bablet J., Bory C., Jacob S., Seiler A.-L., Benwadih M., Verilhac J.-M., Step toward robust and reliable amorphous polymer field-effect transistors and logic functions made by the use of roll to roll compatible printing processes , Organic Electronics, 11, page: 456-462 , 2010
 
(683) Arthaud Y., Rufer L., Mir S., Study of a 3D MEMS-based tactile vibration sensor for the use in the middle ear surgery, International Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP’10), Sevilla, Spain, 2010
 
(684) Meunier Q., Study of two solutions for parallel programming support in integrated multiprocessors: work-stealing and transactional memories , These de Doctorat, 2010
 
(685) Abouzeid F., Subthreshold architecture and digital circuits study in submicronic CMOS technology , These de Doctorat, 2010
 
(686) Morin-Allory K., Fesquet L., Porcher A., Synthesis of asynchronous monitors for critical electronic systems, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’10), Vienna, Austria, 2010
 
(687) Alsayeg K., Synthesis of low power QDI sequential controllers proved correct, These de Doctorat, 2010
 
(688) Fesquet L., Sicard G., Bidegaray-Fesquet B., Targeting ultra-low power consumption with non-uniform sampling and filtering, IEEE International Symposium on Circuits and Systems (ISCAS’10), Paris, France, 2010
 
(689) Zimouche H., Sicard G., Temperature Compensation Method for Logarithmic CMOS Vision Sensor Using CMOS Voltage Reference Bandgap Technique, 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2010), Athens, Greece, 2010
 
(690) Zhou Z., Wong M., Rufer L., The Design, Fabrication and Characterization of a Piezoresistive Tactile Sensor for Fingerprint Sensing, 9th Annual IEEE Conference on Sensors, Waikoloa, HI, USA, 2010
 
(691) Jantsch A., Pierre L., Helmy A., Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing, Symposium on Design and Diagnostics of Electronic Systems (DDECS'10), Vienna (Austria), 2010
 
(692) Mir S., The role of test in the evolution and maturation of emerging technologies, 16th IEEE International Mixed-signals, Sensors and Systems Test Workshop (IMS3TW), La Grande Motte, France, 2010
 
(693) Possamai Bastos R., Transient-Fault Robust Systems Exploiting Quasi-Delay Insensitive Asynchronous Circuits, These de Doctorat, 2010
 
(694) Boulé M., Zilic Z., Borrione D., Morin-Allory K., Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 29, page: 1436 - 1448 , 2010
 
(695) Amhaz H., Sicard G., X-axis Spatial Redundancy Supression : Contribution to the Integration of Smart Reading Techniques in a Standard CMOS Vision Sensor , 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS'10), Athens, Greece, 2010
 
(696) Firmin F., Renaudin M., Sicard G., Clerc S., Abouzeid F., A 45nm CMOS 0.35V-Optimized Standard Cell Library for Ultra-Low Power Applications , International Symposium on Low Power Electronics and Design (ISLPED’09), San Francisco, USA, 2009
 
(697) Sheibanyrad H., Pétrot F., Lemaire R., Martin J., Rousseau F., Elmrabti A., Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation, 12th Euromicro Conference on Digital System Design (DSD’09), Patras, Greece, 2009
 
(698) Pierre L., Clavel R., Leveugle R., ACL2 for the Verification of Fault-Tolerance Properties: First Results, International Workshop on The ACL2 Theorem Prover and Its Applications (EPTCS'09), Boston, MA., USA, 2009
 
(699) Thabuis T., Villard P., Belleville M., Sicard G., Pistone F., Maillart P., Decaens G., A comparative study of on chip decorrelation schemes for low power, high resolution Infrared sensors, Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), Toulouse, France, 2009
 
(700) Qaisar S.-M., Fesquet L., Renaudin M., Adaptative Rate Sampling and Filtering based on level crossing sampling, Eurasip Advances in Signal Processing, 2009, Article ID 971656, page: 12 pages, 2009
 
(701) Gligor M., Fournel N., Pétrot F., Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture , EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD’09), Patras, Greece, 2009
 
(702) Briand R., Terrasson G., Basrour S., A Design Technique for Power Constrained CMOS Low-Noise Amplifier Dedicated to Wireless Sensor Networks, Journal of Low Power Electronics (JOLPE), 5, page: 196-205, 2009
 
(703) Wong M., Rufer L., Zhou Z., Aero-Acoustic Microphone with Layer-Transferred Single-Crystal Silicon Piezoresistors, 15th Int. Conf. on Solid-State Sensors, Actuators and Microsystems (Transducers’09), Denver,Colorado, USA, 2009
 
(704) Schmaltz J., Pierre L., Helmy A., Borrione D., A Formal Approach to the Verification of Networks on Chip, EURASIP Journal on Embedded Systems, Volume 2009, Article ID 548324, page: 14, 2009
 
(705) Bidegaray-Fesquet B., Fesquet L., A fully nonuniform approach to FIR filtering, Sampling Theory and Applications (SampTA’09), Marseille, France, 2009
 
(706) Hubert G., Velazco R., Peronnard P., A generic platform for remote accelerated tests and high altitude SEU experiments on advanced ICs: Correlation with MUSCA SEP3 calculations, International On-Line Test Symposium (IOLTS’09), Sesimbra, Portugal, 2009
 
(707) Abdallah L., Stratigopoulos H., Tongbong J., Mir S., Alternate LNA testing using an envelope detector, Journées GDR SoC-SiP, Paris, France, 2009
 
(708) Nguyen H.N., Alternative test technique for RF MEMS switch, These de Doctorat, 2009
 
(709) Ferron J.B., Miller F., Anghel L., Mantelet G., Leveugle R., Bocquillon A., A methodology and tool for predictive analysis of configuration bit criticality in SRAM-based FPGAs: experimental results, 3rd International Conference on Signals, Circuits & Systems (SCS'09), Djerba, Tunisia, 2009
 
(710) Renaudin M., Reis R., Monnet Y., Sicard G., Kastensmidt F., Possamai Bastos R., A Methodology to Evaluate Transient-Fault Effects on Asynchronous and Synchronous Circuits, 14th IEEE European Test Symposium (ETS'09), Sevilla, Spain, 2009
 
(711) Hedde D., Horrein P.-H, Pétrot F., Rolland R., Rousseau Fra., A MPSoC prototyping platform for flexible radio applications, 12th Euromicro Conference on Digital System Design: Architecture, Methods and Tools (DSD’09), Patras, Greece, 2009
 
(712) Canivet G., Analysis of faulted-based attack effects and secure design on a reconfigurable platform, These de Doctorat, 2009
 
(713) Yu H., Nicolaidis M., Anghel L., An Effective Approach to Detect Logic Soft Errors in Digital Circuits Based on GRAAL , International Symposium on Quality of Electronic Design (ISQED’09), San Jose, CA, USA, 2009
 
(714) Terrasson G., Briand R., Basrour S., Dupé V., Arrijuria O., An Energy Model for the Design of Ultra-Low Power Nodes for Wireless Sensor Networks , The Eurosensors XXIII Conference, Procedia Chemistry, Volume: 1, Issue: 1, Lausanne, Switzerland, Sept. 6 - 9, 2009
 
(715) Renaudin M., André E., Goulier J., A new analystical approach of the impact of jitter of the continuous time delta sigma converters, VLSI-SoC: Advanced Topics on Systems on a Chip, Springer , 1-16, Volume 291, 2009
 
(716) Ferreyra P., Velazco R., Marques C.A., Brac E., A New Automatic VHDL Fault Injection Tool: A case studied, IBERCHIP Workshop, Buenos Aires,Argentina, 2009
 
(717) Bergaoui S., Vanhauwaert P., Leveugle R., A new critical variable analysis in processor-based systems, European Conference on Radiation Effects on Components and Systems (RADECS'09), Bruges, Belgium, 2009
 
(718) Aboulhamid E.M., Dubois Ma., Rousseau F., An Introduction to Cosimulation and Compilation Methods, System Level Design with .NET Technology, CRC Press, 177-202, 2009
 
(719) Pétrot F., Gligor M., Fournel N., A Power Aware Transactional Level Multi-processor SoC Simulation Environment, MEDEA+/CATRENE Design Technology Conference, Dresden, Allemagne, 2009
 
(720) Pétrot F., Sheibanyrad H., Architecture de communication à base de sérialiseur asynchrone entre circuits déposés sur des substrats de silicium empilés, 09/53637, 2009
 
(721) Beyrouthy T., Fesquet L., A secure asynchronous FPGA for an embedded system, PhD Forum DATE, Nice, 2009
 
(722) Fesquet L., Renaudin M., Qaisar S.-M., A Signal Driven Adaptive Resolution Short-Time Fourier Transform, International Journal of Signal Processing, Vol. 5, page: 180-188, 2009
 
(723) Yahya E., Fesquet L., Asynchronous Design: A Promising Paradigm for Electronic Circuits and Systems, IEEE International Conference on Electronics and Systems (ICECS’09), Hammamet, Tunisia, 2009
 
(724) Hamon J., Asynchronous oscillators and architectures for UWB impulse radio signal processing, These de Doctorat, 2009
 
(725) Beyrouthy T., Asynchronous programmable logic for secured embedded systems, These de Doctorat, 2009
 
(726) Pétrot F., Guérin X., A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-Core SoCs, 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP’09), Boston (Ma), USA, 2009
 
(727) Briand R., Basrour S., Dupé V., Terrasson G., A top-down approach for the design of low-power microsensor nodes for wireless sensor network, Forum on specification & Design Languages (FDL’09), Sophia Antipolis, France, Sept. 22-24, 2009
 
(728) Bouchhima A., Gerin P., Pétrot F., Automatic instrumentation of embedded software for high level hardware/software co-simulation, Asia and South Pacific Design Automation Conference (ASP-DAC’09), Yokohama, Japan, 2009
 
(729) Cenni F., Rufer L., Mir S., Behavioral modeling and simulation of a chemical sensor with its microelectronics front-end interface, 3rd IEEE International Workshop on Advances in Sensors and Interfaces (IWASI’09), Trani, Italy, 2009
 
(730) Ben Hassine N., Bulk Acoustic Wave devices reliability for Radio Frequency applications, These de Doctorat, 2009
 
(731) Zimouche H., Sicard G., Capteur de vision CMOS à réponse insensible à la température, Journées Nationales du RÉseau Doctoral en Microélectronique (JNRDM’09), Lyon, France, 2009
 
(732) Canivet G., Valette F., Renaudin M., Leveugle R., Clédière J., Characterization of effective laser spots during attacks in the configuration of a Virtex-II FPGA, IEEE VLSI Test Symposium (VTS'09), Santa Cruz, California, USA, 2009
 
(733) Stratigopoulos H., Checkers for on-line monitoring of analog circuits, Emerging Technologies Workshop, Vancouver, Canada, 2009
 
(734) Possamai Bastos R., Monnet Y., Sicard G., Kastensmidt F., Renaudin M., Reis R., Comparing Transient-Fault Effects on Synchronous and on Asynchronous Circuits, 15th IEEE International On-Line Testing Symposium (IOLTS'09), Sesimbra-Lisbon, Portugal, 2009
 
(735) Clavel R., Encrenaz E., Ilié J.-M., Leveugle R., Mounier I., Pierre L., Baarir S., Braunstein C., Poitrenaud D., Complementary formal approaches for dependability analysis, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), Chicago, Illinois, USA, 2009
 
(736) Alexandrescu D., Wen S.J., Nicolaidis M., Complex Electronic Systems Soft Error Rate (SER) Management , IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009
 
(737) Nicolaidis M., Computational Space, Time and Quantum Mechanics, European Computing and Philosophy Conference, (ECAP’09), Barcelona, Spain, 2009
 
(738) Hamon J., Fesquet L., Renaudin M., Miscopein B., Constrained Asynchronous Ring Structures for Robust Digital Oscillators, IEEE Transactions on VLSI Systems, 17, page: 907-919, 2009
 
(739) Shen H., Contribution to a modeling approach and an exploration flow targeted to heterogeneous MPSoC architectures based on configurable processors, These de Doctorat, 2009
 
(740) Zakaria H., Fesquet L., Controlling Energy and Process Variability in System-on-Chips: needs for control theory, 3rd IEEE Multi-conference on Systems and Control (MSC’09), Saint Petersburg, Russia, 2009
 
(741) Alexandrescu D., Wen S.J., Nicolaidis M., Dealing with Soft Errors in Complex Electronic Systems , Annual Single Event Effects Symposium (SEE’09), San Diego, CA., USA, 2009
 
(742) Stratigopoulos H., Mir S., Acar E., Ozev S., Defect filter for alternate RF test, European Test Symposium (ETS’09), Sevilla, Spain, 2009
 
(743) Tongbong J., Design and evaluation of a bist technique for RF LNA, These de Doctorat, 2009
 
(744) Raslan Z. , Basrour S., Le Poche H., Design and Fabrication of Electromechanical Tweezers based on CNT Ropes, Nanotech 2009 Conference, Houston, TX, USA, 2009
 
(745) Pétrot F., Meunier Q., Design and Use of Transactional Memory in MPSoCs, 9th International Seminar on Application Specific Multiprocessor SoC, Savanah, Georgia, USA, 2009
 
(746) Raslan Z. , Design, fabrication and characterization of microactuators based on carbon nanotubes, These de Doctorat, 2009
 
(747) Kastensmidt F., Reis R., Possamai Bastos R., Design of a soft-error robust microprocessor, Microelectronics journal, 40, July, page: 1062-1068, 2009
 
(748) Asquini A., Bounceur A., Mir S., Badets F., Carbonero J.L., Bouzaida L., DFT technique for RF PLLs using built-in monitors , Design and Technology of Integrated Systems (DTIS’09), Cairo, Egypt, 2009
 
(749) Ben Hassine N., Blonkowski S., Ancey P., Mercier D., Renaux Ph., Parat G., Basrour S., Waltz P., Chappaz C., Dielectrical properties of Metal-Insulator-Metal Aluminium Nitride structures: measurement and modeling, Journal of Applied Physics, 105, page: 044111-044111-10 , 2009
 
(750) Fesquet L., Sicard G., Rios D., Renaudin M., Alsayeg K., Direct mapping of sequential QDI controllers, Design, Automation and Test In Europe (DATE'09), Nice, France, 2009
 
(751) Beyrouthy T., Fesquet L., DPA robust S-BOX implementation on a secure asynchronous FPGA, Cryptarchi Conference, Prague, Czech republic, 2009
 
(752) Maistri P., Leveugle R., Early pruning of soft errors and transient faults with Petri netS, Electronic Symposium Digest of European Test Symposium (ETS'09), Sevilla, Spain, 2009
 
(753) Qaisar S.-M., Fesquet L., Renaudin M., Effective Resolution of an Adaptive Rate ADC, 8th International Conference on Sampling Theory and Applications (SampTA’09), Marseille, France, 2009
 
(754) Vanhauwaert P., Leveugle R., Efficiency of probabilistic testability analysis for soft error effect analysis: a case study, International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS’09), Cairo, Egypt, 2009
 
(755) Masmoudi M., Tounsi F., Mezghani B., Mir S., Rufer L., Electromagnetic Investigation of a CMOS MEMS Inductive Microphone, Sensors & Transducers Journal (ISSN 1726- 5479), 108, page: 40-53, 2009
 
(756) Tounsi F., Mezghani B., Rufer L., Mir S., Masmoudi M., Electromagnetic modelling of an integrated micromachined inductive microphone, Design and Technology of Integrated Systems (DTIS’09), Cairo, Egypt, 2009
 
(757) Nicolaidis M., Emergence of Relativistic Space-Time in a Computational Universe, European Computing and Philosophy Conference, (ECAP’09), Barcelona, Spain, 2009
 
(758) Kolonis E., Nicolaidis M., Gizopoulos D., Psarakis M., Collet J.H., Zajac P., Enhanced self-configurability and yield in multicore grids, IEEE International On-Line Testing Symposium (IOLT’09), Sesimbra-Lisbon, Portugal, 2009
 
(759) Makris Y., Stratigopoulos H., Mir S., Enrichment of limited training sets in machine-learning-based analog/RF Test, Design, Automation and Test in Europe Conference (DATE’09), Nice, France, 2009
 
(760) Di Natale G., Flottes M.-L., Leveugle R., Rouzeyre B., Maistri P., Ensuring High Testability without Degrading Security, European Test Symposium (ETS’09), Seville, Spain, 2009
 
(761) Pétrot F., Gerin P., Estimation de performance du logiciel embarqué utilisant une technique d’annotation du code natif, 3ème école d’hiver francophone sur les systèmes hétérogènes, Chexbres, Suisse, 2009
 
(762) Mir S., Bounceur A., Stratigopoulos H., Evaluation of analog/RF test measurements at the design stage, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, page: 582-590, 2009
 
(763) Peronnard P., Velazco R., Cabanillas E., Al Falou W., Ziade H., Evaluation of the soft error rate of a space application executed by a real time operating system, MESM 2009, Beyrouth, Liban, 2009
 
(764) Mir S., Sicard G., Lizarraga L., Experimental validation of a BIST technique for CMOS active pixel sensors, 27th IEEE VLSI Test Symposium (VTS’09), Santa Cruz, USA, 2009
 
(765) Pétrot F., Bouchhima A., Elmrabti A., Extending IP-XACT to support an MDE based approach for SoC design, Design Automation and Test in Europe (DATE’09), Nice, France, 2009
 
(766) Popovici K., Jerraya A. A., Flexible and Abstract Communication and Interconnect Modeling for MPSoC, Asia and South Pacific Design Automation Conference (ASP-DAC’09), Yokohama, Japan, 2009
 
(767) Kouadri Mostéfaoui A., Flexible Architectures for Networks-On-Chip Validation and Exploration, These de Doctorat, 2009
 
(768) Helmy A., Borrione D., Schmaltz J., Pierre L., Formal Verification of Communications in Networks-on-Chip, Networks-on-Chips: Theory and Practice, taylor & francis group, 250 p., 2009
 
(769) Yan X., Han Sang-Il, Carro L., Chae Soo-Ik, Brisolara L., Guérin X., Huang K., Popovici K., Jerraya A. A., Gradual Refinement for Application Specific MPSoC Design from Simulink Model to RTL Implementation, Journal of Zhejiang University SCIENCE A (JZUS-A), 10, Number 2, February , page: 151-164, 2009
 
(770) Popovici K., Jerraya A. A., Hardware Abstraction Layer – Introduction and Overview, Hardware dependent Software, Concept, Tools and Applications, Springer , 67- 94, 2009
 
(771) Dubois M., Stratigopoulos H., Mir S., Hierarchical parametric test metrics estimation: A sigma-delta converter BIST case-study, 27th IEEE International Conference on Computer Design (ICCD’09), Lake Tahoe, California, USA, 2009
 
(772) Velazco R., Peronnard P., Silva Cardenas C., Fernandez S., High altitude experiments to evaluate SEU sensitivity of advanced SRAMs, IBERCHIP Workshop, Buenos Aires, Argentina, 2009
 
(773) Ouchet F., Borrione D., Morin-Allory K., Pierre L., High-level symbolic simulation for automatic model extraction, Proc. IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS’09), Liberec (Czech Republic), 2009
 
(774) Tounsi F., Rufer L., Mezghani B., Masmoudi M., Mir S., Highly Flexible Membrane Systems for Micromachined Microphones – Modeling and Simulation, 3rd IEEE International Conference on Signals, Circuits and Systems, (SCS'09), DJerba, Tunisia, 2009
 
(775) Leveugle R., Bergaoui S., IDSM: An improved control flow checking approach with disjoint signature monitoring, Conference on Design of Circuits and Integrated Systems (DCIS'09), Zaragoza, Spain, 2009
 
(776) Maingot V., Leveugle R., Influence of error detecting or correcting codes on the sensitivity to DPA of an AES S-Box, International Conference on Signals, Circuits & Systems (SCS'09), Djerba, Tunisia, 2009
 
(777) Vachon J., Aboulhamid E.M., Metzger M., Anane A., Rousseau F., Introspection Mechanisms for Runtime Verification in a System-Level Design Environment, Microelectronics journal, 40, page: 1124-1134, 2009
 
(778) Ferro L., Pierre L., ISIS: Runtime Verification of TLM Platforms, Forum on specification & Design Languages (FDL'09), Sophia-Antipolis (France), 2009
 
(779) Meunier Q., Pétrot F., LightTM : Une Mémoire Transactionnelle conçue pour les MPSoCs , Symposium en Architecture de machines (SympA'13), Toulouse, France, 2009
 
(780) Meunier Q., Pétrot F., Lightweight Transactional Memory Systems for Large Scale Shared Memory MPSoCs , Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), Toulouse, France, 2009
 
(781) Nicolaidis M., Logic circuit protected against transient disturbances, 7380192 : Application 20090259897, 2009
 
(782) Borrione D., Ferro L., Fesquet L., Morin-Allory K., Oddos Y., Pierre L., Logiciel , FR.001.220016.000.S.P.2009.000.31500, 2009
 
(783) Cenni F., Simeu E., Mir S., Macro-modeling of analog blocks for SystemC-AMS simulation: A chemical sensor case-study, 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC’09), Florianapolis, Brazil, 2009
 
(784) Marzencki M., Defosseux M., Basrour S., MEMS Vibration Energy Harvesting Devices With Passive Resonance Frequency Adaptation Capability, Journal of Microelectromechanical Systems, 18, page: 1444-1453, 2009
 
(785) Rusu C., Avresky D., Anghel L., Message routing in 3D networks-on-chip, NORCHIP Conference 2009, Trondheim, Norway, 2009
 
(786) Peronnard P., Methods and tools for the evaluation of the sensitivity to natural radiations of advanced integrated circuits , These de Doctorat, 2009
 
(787) Pétrot F., Guironnet de Massas P., Migration de données dans les MPSoC : une solution matérielle, 3ème Symposium en Architecture de machines (SympA'13), Toulouse, France, 2009
 
(788) Koch-Hofer C., Modeling, Validation and Presynthesis of Asynchronous Circuits in SystemC, These de Doctorat, 2009
 
(789) Rahmouni K., Gerin P., Chabanet S., Pétrot F., Pianu P., Modelling and architecture exploration of a medium voltage protection device, IEEE Symposium on Industrial Embedded Systems (SIES’09), Lausanne, Suisse, 2009
 
(790) Velazco R., Ayoubi R., Idriss T., Ziade H., MSI: A Multiple SEU Injection Method for FPGAs, International Conference on Information Science, Technology and Applications (ISTA’09), Kuwait, 2009
 
(791) Boulé M., Morin-Allory K., Zilic Z., Oddos Y., Borrione D., MYGEN: Automata-based On-line Test Generator for Assertion-based Verification, Proc. 19th Great Lakes Symposium on VLSI (GLSVLSI'09), Boston (MA), USA, 2009
 
(792) Hamayun M.M., Pétrot F., Gerin P., Native MPSoC co-simulation environment for software performance estimation, 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis (CODES+ISSS'09), 2009
 
(793) Shen H., Pétrot F., Novel Task Migration Framework on Configurable Heterogeneous MPSoC Platforms, 14th Asia and South Pacific Design Automation Conference (ASP-DAC’09), Yokohama, Japan, 2009
 
(794) Bocquillon A., On the evaluation of the sensitivity of SRAM-Based FPGA to errors due to natural radiation environment, These de Doctorat, 2009
 
(795) Nicolaidis M., On the State of Superposition and the Parallel Nature of Quantum Computing, ISRN: TIMA-RR--09/09--01-FR, 2009
 
(796) Pétrot F., Guironnet de Massas P., Optimized and Transparent Data Accesses in Homogeneous MPSoC, Visionary scientific seminar, « The future of Computing : Massively Parallel Computing », IP-Embedded Systems Conference, Grenoble, France, 2009
 
(797) Fesquet L., Sicard G., Renaudin M., Alsayeg K., Rios D., Optimizing speed and consumption of QDI controllers using direct mapping synthesis, Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), Toulouse, France, 2009
 
(798) Elissati O., Yahya E., Fesquet L., Rieubon S., Oscillation Period and Power Consumption in Configurable Self-Timed Rings Oscillators, Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), Toulouse, France, 2009
 
(799) Chagoya-Garzon A., Guérin X., Rousseau F., Outils de Génération du Logiciel pour les Systèmes sur Puce Multi-Processeur Hétérogènes, Journées Nationales du RÉseau Doctoral en Microélectronique (JNRDM’09), Bordeaux, France, 2009
 
(800) Khereddine R., Simeu E., Mir S., Parameter identification of RF transceiver blocks using regressive models, Workshop on Programmable Devices and Embedded Systems (PDeS’09), Roznov pod Radhostem, Czech Republic, 2009
 
(801) Yahya E., Performance Modeling, Analysis and Optimization of Multi-Protocol Asynchronous Circuits, These de Doctorat, 2009
 
(802) Carlioz L., Piezoelectric generator thermo-magnetically triggered, These de Doctorat, 2009
 
(803) Defosseux M., Marzencki M., Basrour S., Piezoelectric vibration harvesting device with automatic resonance frequency tracking capability, Material Research Society - Fall MEETING, Boston, USA, 2009
 
(804) Basrour S., Waltisperger G., Condemine C., Power path optimization for autonomous microsystems, Joint IEEE North-East Workshop On Circuits And Systems And Taisa Conference, Toulouse, France, 2009
 
(805) Coppola M., Teninge Ph., Pétrot F., Colas-Bigey F., Fouillard A.-M., Gligor M., Fournel N., Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform, Power and Timing Modeling, Optimization and Simulation (PATMOS’09), Delft, Netherlands, 2009
 
(806) Maistri P., Leveugle R., Calvez A., Vanhauwaert P., Precisely Controlling the Duration of Fault Injection Campaigns: a Statistical View , International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS’09), Cairo, Egypt, 2009
 
(807) Ferron J.B., Predictive Analysis of Configuration Bit Criticality in SRAM-Based FPGAs. Methodology, tool, and results, RADECS thematic day for Ph.D. students (RADFAC’09), Grenoble, France, 2009
 
(808) Ferron J.B., Anghel L., Leveugle R., Predictive analysis of configuration bit criticality in SRAM-based FPGAs – Methodology, tools, and results, 3ème Colloque du GdR SoC-SiP, Paris, France, 2009
 
(809) Elissati O., Zakaria H., Yahya E., Fesquet L., Renaudin M., Programmable/Stoppable Oscillator Based on Self-Timed Rings, Asynchronous Circuits and Systems, 2009. ASYNC '09. 15th IEEE Symposium on, 2009
 
(810) Maistri P., Pruning Single Event Upset Faults with Petri Nets , Latin-American Test Workshop (LATW’09), Armacao de Buzios, Brazil, 2009
 
(811) Maistri P., Pruning Single Event Upset Faults with Petri Nets , ISRN: TIMA-RR--09/03-02-FR, 2009
 
(812) Rufer L., Dhayni A., Mir S., Bounceur A., Simeu E., Pseudorandom BIST for test and characterization of linear and nonlinear MEMS, Microelectronics journal, 40, page: 1054-1061, 2009
 
(813) Alsayeg K., Morin-Allory K., Fesquet L., RAT-based formal verification of QDI asynchronous controllers, Forum on specifications and Design Languages (FDL’09), Sophia Antipolis, France, 2009
 
(814) Velazco R., Peronnard P., Hubert G., Real-Life SEU Experiments on 90 nm SRAMs in Atmospheric Environment: Measures Versus Predictions Done by Means of MUSCA SEP3 Platform, IEEE Transactions on Nuclear Science, 56, page: 3450 - 3455 , 2009
 
(815) Sahnine C., Reconfigurable, high throughput and low power VLSI architecture for advanced OFDM digital processing, These de Doctorat, 2009
 
(816) Boutobza S., Nicolaidis M., Runtime Programmable BIST for Testing a Multi-Port Memory Device, 8,042,011, 2009
 
(817) Allain M., Berthier J., Basrour S., Pouteau P., Sacrificial membranes for serial valving in Microsystems, Nanotech 2009 Conference, Houston, TX, 2009
 
(818) Maingot V., Secure Design against fault attacks and side-channel attacks, These de Doctorat, 2009
 
(819) Ben Hassine N., Mercier P., Renaux Ph., Bloch D., Parat G., Ivira B., Chappaz C., Basrour S., Fillit R., Waltz P., Self heating under RF power in BAW SMR and its predictive 1D thermal model, Joint Meeting of the 23rd European Frequency and Time Forum/IEEE International Frequency Control Symposium, Besançon, France, 2009
 
(820) Oddos Y., Semi-Formal Verification and Automatic Synthesis from PSL to VHDL, These de Doctorat, 2009
 
(821) Qaisar S.-M., Renaudin M., Fesquet L., Signal Driven Sampling and Filtering : A Promising Approach for Time Varying Signals Processing, International Journal of Signal Processing, 5, page: 189-197, 2009
 
(822) Qaisar S.-M., Signal Driven Sampling and Processing : A Promising Approach for Adaptive Rate Computationally Efficient Solutions, These de Doctorat, 2009
 
(823) Nicolaidis M., Simulating Time , Computing and Philosophy Symposium, AISB 2009 Convention (Adaptive & Emergent Behaviour & Complex Systems), Edinburgh, UK , 2009
 
(824) Gerin P., Pétrot F., Simulation at Cycle Accurate and Transaction Accurate Levels, System Level Design with .NET Technology, CRC Press, 155-175, 2009
 
(825) Gerin P., Simulation models for software validation and architecture exploration of Multi-Processors System On Chip, These de Doctorat, 2009
 
(826) Guérin X., Yan X., Li L., Huang K., Jerraya A. A., Han Sang-Il, Chae Soo-Ik, Brisolara L., Carro L., Popovici K., Simulink(R) based Heterogeneous Multiprocessor SoC Design Flow for Mixed Hardware/Software refinement and simulation, Integration, the VLSI Journal, 42, page: 227-245, 2009
 
(827) Ben Hassine N., Mercier P., Renaux Ph., SMR Under High Power Study For Reliability, 5th International Conference on Ph.D. Research in Microelectronics & Electronics (PRIME'09), Cork, Ireland, 2009
 
(828) Pierre L., Maistri P., Clavel R., Leveugle R., Soft Error Effect and Register Criticality Evaluations: Past, Present and Future, Workshop on Silicon Errors in Logic - System Effects (SELSE’09), Stanford (CA), 2009
 
(829) Mercier D., Ben Hassine N., Renaux Ph., Solidly mounted resonators under high power study for reliability assessment, Ph.D.Research in Microelectronics and Electronics (PRIME’09), 2009
 
(830) Leveugle R., Calvez A., Maistri P., Vanhauwaert P., Statistical Fault Injection: Quantified Error and Confidence , Design, Automation and Test in Europe (DATE '09), Nice, France, 2009
 
(831) Guironnet de Massas P., Study of methods and mechanisms for software-seamless data accesses in a multiprocessor system-on-chip, These de Doctorat, 2009
 
(832) Rufer L., Ryger I., Tomaska M., Mozolova Z., Hascik S., Vanko G., Lalinsky T., Vincze A., Surface Acoustic Wave Excitation on SF6 plasma treated AlGaN/GaN heterostructure, Vacuum Journal , 84, page: 231-234 , 2009
 
(833) Chagoya-Garzon A., Guérin X., Rousseau F., Pétrot F., Rossetti D., Lonardo A., Vicini P., Paolucci P.S., Synthesis of communication mechanisms for multi-tile systemsbased on heterogeneous Multi-processor System-on-Chips, 20th IEEE/IFIP International Symposium on Rapid System Prototyping(RSP'09), Paris, France, 2009
 
(834) Oddos Y., Morin-Allory K., Borrione D., Synthorus: Highly Efficient Automatic Synthesis from PSL to HDL, International Conference On Very Large Scale Integration (VLSI-SoC'09), Florianopolis, Brazil, 2009
 
(835) Rousseau F., Aboulhamid E.M., System Level Design with .NET Technology, CRC Press, 328 p., 2009
 
(836) Carlioz L., Delamare J., Basrour S., Temperature threshold tuning of a thermal harvesting switch, The 15th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers’09), Denver Colorado, 2009
 
(837) Ferreyra P., Marques C.A., Velazco R., Brac E., Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications, Latin American Test Workshop (LATW’09), Buzios, Brazil, 2009
 
(838) Ghandour S., Despesse G., Basrour S., Theoretical Analysis Of A New Mems Approach To Build A High Efficiency Fully Integrated DC-DC Converter, 20th Micromechanics Europe Workshop (MME’09), Toulouse, France, 2009
 
(839) Basrour S., Delamare J., Jean-Mistral C., Cugat O., Carlioz L., Defosseux M., Marzencki M., Thermo-Magnetic, Piezo-Electric and Electroactive Energy Harvesting Devices, Material Research Society - Fall Meeting, Boston, USA, 2009
 
(840) Leveugle R., Maistri P., Toward automated fault pruning with Petri nets, International on-line Testing Symposium (IOLTS’09), Sesimbra-Lisbon, Portugal, 2009
 
(841) Amhaz H., Labonne E., Rolland R., Sicard G., Traitement de bas niveau intégré : Mise en oeuvre d’une adaptation aux conditions lumineuses dans un capteur d’images CMOS, 22ème colloque GRETSI, Dijon, France, 2009
 
(842) Abouzeid F., Clerc S., Renaudin M., Sicard G., Ultra-Low Voltage from 65nm to 32nm, 8èmes Journées Faible Tension Faible Consommation (FTFC’09), Neuchatel, Switzerland, 2009
 
(843) Guilley S., Chaudhuri S., Sauvage L., Beyrouthy T., Danger J.-L., Fesquet L., Updates on the Potential of Clock-Less Logics to Strengthen Cryptographic Circuits against Side-Channel Attacks, IEEE International Conference on Electronics and Systems (ICECS’09), Hammamet, Tunisia, 2009
 
(844) Gligor M., Fournel N., Pétrot F., Using Binary Translation in Event Driven Simulation for Fast and Flexible MPSoC Simulation, International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS’09), Grenoble, France, 2009
 
(845) Allain M., Basrour S., Berthier J., Pouteau P., Vanne microfluidique à usinage unique, FR2945097, 2009
 
(846) Marzencki M., Muralt P., Calame F., Belgacem B., Basrour S., Vibration Energy Harvesting with PZT Micro Device, PowerMems 2009, Washington DC, USA, 2009
 
(847) Muralt P., Belgacem B., Calame F., Basrour S., Marzencki M., Vibration Energy Harvesting with PZT Micro Device , The Eurosensors XXIII Conference, Procedia Chemistry, Volume: 1, Issue: 1, Lausanne, , 2009
 
(848) Maistri P., AES Secured Architecture and Auto-Test Capabilities, PAca Security Trends In embedded Security (PASTIS’08), Gardanne, France, 2008
 
(849) Ivanov A., Saleh S., Pande P.P., Nuca V., Anghel L., Grecu C., Rusu C., A flexible network-on-chip simulator for early design space exploration , 1st Microsystems and Nanoelectronics Research Conference (MNRC 2008), Ottawa, Canada, October 15, 2008
 
(850) Borrione D., Schmaltz J., A functional formalization of on chip communications, Formal Aspects of Computing, Vol.20, page: 241-258, 2008
 
(851) Stratigopoulos H., Mir S., Tongbong J., A general method to evaluate RF BIST techniques based on non-parametric density estimation , Design Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008
 
(852) Velazco R., Peronnard P., Pechiar J., Foucard G., Fernandez S., A generic platform for SEE high altitude experiments, Conference RADSOL “Electronique et rayonnements naturels au niveau du sol », CNRS, Paris, France, June 11-12, 2008
 
(853) Renaudin M., Yahya E., AHMOSE: Towards a Circuit Level Solution for Process Variability, Design, Automation and Test in Europe Conference (DATE’08), Munich, Germany, March 10-14, 2008
 
(854) Vincze A., Lalinsky T., Rufer L., Vanko G., Mir S., Hascik S., Uherek F., Mozolova Z., AlGaN/GaN heterostructure based surface acoustic wave structures for chemical sensors, Applied Surface Science, Volume 255, Issue 3, 30 November , page: 712-714, 2008
 
(855) Fesquet L., Renaudin M., Qaisar S.-M., An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform, Research Letters in Signal Processing, Vol. 2008, Article ID 932068, , page: 5 pp., 2008
 
(856) Qaisar S.-M., Fesquet L., Renaudin M., An Improved Quality Adaptative Rate Filtering Technique Based on the Level Crossing Sampling, Computer Vision, Image and Signal Processing (CVISP’08), Prague, Czech Republic, July 25-27, 2008
 
(857) Fesquet L., Renaudin M., Qaisar S.-M., An improved quality filtering technique for time varying signals based on the level crossing sampling, International Conference of Signals and Electronic Systems 2008 (ICSES’08), Krakow, Poland, September 14-17, 2008
 
(858) Fesquet L., Beyrouthy T., A secure asynchronous configurable cell: an embedded programmable logic for smartcards, Workshop on Cryptographic Architectures embedded in reconfigurable devices (CryptArchi’08), Tregastel, France, June 1-4 (Comm. sans actes), 2008
 
(859) Beyrouthy T., Fesquet L., Chaudhuri S., Guilley S., Hoogvorst P., Renaudin M., Razafindraibe A., Danger J.-L., A Secure Programmable Architecture with a Dedicated Tech-mapping Algorithm: Application to a Crypto-Processor, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, November 12-14, 2008
 
(860) Nicolaidis M., Assembly of electronic circuits comprising means for decontaminating error-contaminated parts, 7380165, 2008
 
(861) Morin-Allory K., Borrione D., Oddos Y., Assertion-Based Design with Horus, International Conference on Formal Methods and Models for Codesign (MEMOCODE'2008), Anaheim,CA, USA, June 5-7, 2008 , 2008
 
(862) Borrione D., Assertion Based Test, Forum on specification & Design Languages (FDL'08), Stuttgart, Germany, September 23-25, 2008
 
(863) Oddos Y., Morin-Allory K., Borrione D., Assertion-Based Verification and On-line Testing in Horus, Proc. IEEE International Design and Test Workshop (IDT'08), Monastir (Tunisia), December 20-21, 2008
 
(864) Labonne E., Rolland R., Sicard G., A Standard 3.5T CMOS Imager including a Light Adaptive System for Integration Time Optimisation, Conference on Design and Architectures for Signal and Image Processing (DASIP’08), Bruxelles, Belgium November 24 -26, 2008
 
(865) Stratigopoulos H., Stern E., Reed M., Makris Y., Dardig J., A Statistical Approach to Characterizing and Testing Functionalized Nanowires, IEEE VLSI Test Symposium (VTS’08), San Diego, California, USA, April 27-May 1st , 2008
 
(866) Fesquet L., Asynchronous integrated systems and non-uniformly sampled signal processing, HDR, 2008
 
(867) Yahya E., Renaudin M., Asynchronous Linear Pipelines: An Efficient-Optimal Pipelining Algorithm, 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS’08), Malta, August 31- September 03, 2008
 
(868) Yahya E., Renaudin M., Asynchronous Linear-Pipeline with Time Variable Delays: PerformanceModeling, Analysis and Slack Optimization, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, November 12-14, 2008
 
(869) Morin-Allory K., Borrione D., Roustan B., Fesquet L., Asynchronous online monitoring of logical and temporal assertions, Embedded Systems Specification and Design Languages, Springer , 278 p, 2008
 
(870) Ferro L., Pierre L., A Tractable and Fast Method for Monitoring SystemC TLM Specifications , IEEE Transactions on Computers, Vol. 57, page: 1346-1356, 2008
 
(871) Zergainoh N.-E., Atat Y., Automatic Code Generation for MPSoC Platform Starting From Simulink/Matlab : New Approach to Bridge the Gap between Algorithm and Architecture Design, 3rd International Conference on Information and Communication Technologies: From Theory to Applications (ICTTA’08), Damascus, Syria, 7-11 April , 2008
 
(872) Pétrot F., Gerin P., Bouchhima A., Automatic timing annotation of native software for MPSoC simulation, 8th International Forum on Application-Specific Multi-Processor SoC (MPSoC), Aachen, Germany, 23-27 June , 2008
 
(873) Lizarraga L., BIST technique for CMOS imagers, These de Doctorat, 2008
 
(874) Rusu C., Grecu C., Anghel L., Blocking and Non-blocking Checkpointing for Networks-on-Chip, 2nd IEEE Workshop on Dependable and Secure Nanocomputing (WDSN’08), Anchorage, Alaska, USA, June 27, 2008
 
(875) Dubois M., Mansouri I., Chouba N., Mir S., Calibrage automatique d’un convertisseur Sigma-Delta utilisant un BIST, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, France, Mai 14-16, 2008
 
(876) Arthaud Y., Rufer L., Mir S., Capteur MEMS faible impédance mécanique haute sensibilité pour la chirurgie de l’oreille moyenne, Journées GDR MNS, Montpellier, France, 03-05 December, 2008
 
(877) Dang T., CNTFET-based logic gates - characteristic dispersions and defect tolerance, These de Doctorat, 2008
 
(878) Anghel L., Grecu C., Rusu C., Communication Aware Recovery Configurations for Networks-on-Chip, 14th IEEE International Symposium On-Line Testing (IOLT’08), July 7-9, 2008
 
(879) Guironnet de Massas P., Pétrot F., Comparison of memory write policies for NoC based Multicore Cache Coherent Systems, Proceedings of Design Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008, 2008
 
(880) Callonnec D., Pétrot F., Sahnine C., Zergainoh N.-E., Composant de traitement d'un signal numérique, dispositif de modulation et/ou de démodulation multiporteuse, procédé de modulation et/ou de démodulation et programme d'ordinateur correspondants , WO/2008/145915 / PCT/FR2008/050703, 2008
 
(881) Qaisar S.-M., Fesquet L., Renaudin M., Computationally Efficient Adaptive Rate Sampling and Adaptive Resolution Analysis, Computer Vision, Image and Signal Processing (CVISP’08), Prague, Czech Republic, July 25-27, 2008
 
(882) Shen H., Gerin P., Pétrot F., Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels, Rapid System Prototyping Symposium (RSP’08), Monterey, Cal, USA, June 2-5, 2008
 
(883) Goulier J., Contribution to the design of continuous time delta sigma converters, from specifications to silicon. Application to a wide band wireless standard., These de Doctorat, 2008
 
(884) Rusu C., Grecu C., Anghel L., Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip based Systems, 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA’08), Hong Kong, January 23-25, 2008
 
(885) Nicolaidis M., Dealing with soft errors in nanometric CMOS, Reliability and Design (Zuverlässigkeit und Entwurf - ZuE 2008), Ingolstadt, Germany, September 29 – October 1, 2008
 
(886) Chureau A., Definition of a Service-Based Intermediate Representation for Virtual Prototyping of Systems-on-Chip, These de Doctorat, 2008
 
(887) Pétrot F., Kouadri Mostéfaoui A., De l’émulation des « NoC » à la synthèse des « NiP », 2ème école d’hiver francophone sur les systèmes hétérogènes, Montebello, Québec, janvier , 2008
 
(888) Robain G., Bonvilain A., Cinquin Ph., Basrour S., Lamraoui H., Mozer P., Design and Implementation of an Automated Artificial Urinary Sphincter, International Workshop on Wearable Micro and Nanosystems for Personalised Health (Phealth'08),Valencia, Spain, May 21-23, 2008
 
(889) Lamraoui H., Cinquin Ph., Mozer P., Basrour S., Robain G., Bonvilain A., Design and Implementation of an Automated Artificial Urinary Sphincter ?, Symposium: Endoskopie Euro (EUS'08), Orlando, USA, May 1st, 2008
 
(890) Sicard G., Design of Concurent Integrated Systems : Cmos Image Sensors & Clockless Integrated Systems , HDR, 2008
 
(891) Terrasson G., Design under power constraint of a transceiver for autonomous microsensors, These de Doctorat, 2008
 
(892) Clédière J., Ferron J.B., Valette F., Renaudin M., Leveugle R., Canivet G., Detailed analyses of single laser shot effects in the configuration of a Virtex-II FPGA, 14th IEEE International On-Line Testing symposium, Rhodes, Greece, 2008
 
(893) Jean-Mistral C., Chaillout J.J., Basrour S., Dielectric polymer: scavenging energy from human motion, Electroactive Polymer Actuators and Devices (EAPAD'08), San Diego, USA, March 9-13, 2008
 
(894) Bonvilain A., Moreau-Gaudry A., Dispositif d’intervention chirurgicale comprenant un instrument susceptible de se déformer, FR0855617, 2008
 
(895) Leveugle R., Maistri P., Double-Data-Rate computation as a countermeasure against fault analysis, IEEE Transactions on Computers, Vol. 57, no. 11, November , page: 1528-1539, 2008
 
(896) Pouget V., Douin A., Foucard G., Peronnard P., Lewis D., Fouillat P., Velazco R., Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection, 14th IEEE International Symposium On-Line Testing (IOLT’08), Rhodes, Greece, July 7-9, 2008
 
(897) Rusu C., Grecu C., Anghel L., Efficient Coordinated Checkpointing Recovery Schemes for Network-on-Chip based Systems, 2nd International Workshop on Dependable Circuit Design (DECIDE’08), Playa del Carmen, Mexico, November 27-29, 2008
 
(898) Pétrot F., Guérin X., Gerin P., Efficient implementation of native software simulation for MPSoC , Proceedings of Design Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008 , 2008
 
(899) Courtois B., Charlot B., Di Pendina G., Rufer L., Electronics manufacturing infrastructures for education and commercialization, 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBS’08), Vancouver, Canada, August 20-25, 2008
 
(900) Nicolaidis M., Emergence of relativistic space-time in a simulated universe: the formal proofs , ISRN: TIMA- RR--08/12--01-FR, 2008
 
(901) Carlioz L., Delamare J., Basrour S., Energy scavenging using hybrid thermo-magnetic/PZT structure, Joint European Magnetics Symposia (JEMS'08), Dublin, Ireland, September 14, 2008
 
(902) Makris Y., Stratigopoulos H., Error moderation in low-cost machine-learning-based analog/RF testing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(2), page: 339-351, 2008
 
(903) Gobert J., Mehrez H., Abril A., Miro C., Pétrot F., Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle, Technique et Science Informatiques (TSI), 27, n ̊ 1-2, page: 203-233, 2008
 
(904) Mir S., Bounceur A., Estimation of test metrics for AMS/RF BIST using Copulas, 14th IEEE International Mixed-Signals, Sensors and Systems Test Workhop (IMS3TW’08), Vancouver, Canada, June 18-20, 2008
 
(905) Mir S., Evaluation of mixed-signal/RF DFT solutions for SiP devices using statistical techniques, Workshop on Reliability & DfX engineering for System-in-Package Technologies, Invited Talk, Pallanza, Italy, May , 2008
 
(906) Borrione D., Helmy A., Pierre L., Schmaltz J., Executable Formal Specification and Validation of NoC Communication Infrastructures, Proc. of 21st Symposium on Integrated Circuits and Systems Design (SBCCI’08), Gramado (Brazil), September 1-4, 2008
 
(907) Brac E., Ferreyra P., Velazco R., Marques C.A., Naguil J., Ferreyra R., Gastaldi R., Extending the Use of Failure Maps for FPGA Based Applications: A Case Studied, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, November 12-14, 2008
 
(908) Senouci B., Fast MPSoC prototyping methodology on reconfigurable hardware platforms , These de Doctorat, 2008
 
(909) Vanhauwaert P., FAULT-INJECTION BASED DEPENDABILITY ANALYSIS IN A FPGA-BASED ENVIRONMENT, These de Doctorat, 2008
 
(910) Nicolaidis M., Fault Tolerant Architectures for Mitigating Variability Issues, Workshop: Impact of Process Variability on Design and Test, Design Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008
 
(911) Helmy A., Pierre L., Formal Verification of the Communications in Networks on Chips, 2ème Colloque du GdR SoC-SiP, Paris, France, June 4-6, 2008
 
(912) Ferro L., Ledru Y., Pierre L., Du Bousquet L., Generation of Test Programs for the Assertion-Based Verification of TLM Models, Proc. IEEE International Design and Test Workshop (IDT'08), Monastir (Tunisia), December 20-21, 2008
 
(913) Hamon J., Renaudin M., Fesquet L., Miscopein B., High-level time-accurate model for the design of self-timed ring oscillators, Proceedings of 14th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’08), Newcastle upon Tyne, UK, 7th – 11th April , 2008
 
(914) Borrione D., HORUS: proven correct support for on-line property verification, FETCH'08, Ecole d'Hiver Francophone sur les Technologies de Conception des systèmes embarqués Hétérogènes, Montebello, Québec, Canada, January 7-9, 2008
 
(915) Poulin G., Carlioz L., Delamare J., Bonvilain A., Basrour S., Hybridization of Magnetism and Piezoelectricity for an Energy Scavenger based on Temporal , Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP’08), Nice, France, April 9-11, 2008
 
(916) Foucard G., Peronnard P., Velazco R., Impact of the Software optimization on the Soft Error Rate: a case study, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, November 12-14, 2008
 
(917) Hamon J., Miscopein B., Schwoerer J., Fesquet L., Renaudin M., Implémentation en logique asynchrone d’un algorithme de synchronisation de signaux radio impulsionnelle, 7ème journées d'études Faible Tension Faible Consommation, (FTFC’08),Université Catholique de Louvain, Belgique, May 26-28, 2008
 
(918) Grecu C., Anghel L., Rusu C., Improving the Scalability of Checkpoint Recovery for Networks-on-Chip, IEEE International Symposium on Circuits and Systems (ISCAS’08), Seattle, Washington, USA, May 18-21, 2008
 
(919) Courtois B., Charlot B., Di Pendina G., Rufer L., Infrastructures for education, research and industry: CMOS and MEMS for BioMed, 12th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI’08) Orlando, USA, June, 2008
 
(920) Courtois B., Charlot B., Di Pendina G., Rufer L., Infrastructures for mixed signals in biology and medicine, 14th IEEE Int. Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW’08), Vancouver, Canada, June 18-20, 2008
 
(921) Fesquet L., Anghel L., Morin-Allory K., Initiation à la conception de VLSI numériques, 10èmes journées pédagogiques CNFM, Saint-Malo, France, November 26-28, 2008
 
(922) Canivet G., Renaudin M., Valette F., Leveugle R., Clédière J., Injection de fautes sur composant Virtex-II XC2V1000, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, France, Mai 14-16, 2008
 
(923) Albea-Sanchez C., Durand S., Canudas de Wit C., Fesquet L., Thonnard Y., Zakaria H., Marchand N., Integrated Asynchronous Regulation for Nanometric Technologies: Application to an Embedded Parallel System, MINATEC CROSSROADS'08, June 23-27, 2008, Grenoble, 2008
 
(924) Ammar Y., Basrour S., Marzencki M., Integrated power harvesting system including a MEMS generator and a power management circuit, Sensors and Actuators A : Physical, 145-146, July-August, page: 363-370, 2008
 
(925) Moreno E., Popovici K., Calazans N., Jerraya A. A., Integrating abstract NoC models within MPSoC design, Rapid System Prototyping Symposium (RSP’08), Monterey, Cal, USA, June 2-5, 2008
 
(926) Canivet G., Clédière J., Valette F., Renaudin M., Leveugle R., Intentional Attacks on SRAM-based FPGAs, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, November 12-14, 2008
 
(927) Kouadri Mostéfaoui A., Senouci B., Pétrot F., Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform, 11th EUROMICRO Conference on Digital System Design Architectures Methods and Tools (DSD’08), Parma, Italy, September 3-5, 2008
 
(928) Basrour S., Renaux Ph., Mercier D., Defay E., Chappaz C., Ben Hassine N., Linear variation of Aluminum Nitride capacitance versus voltage induced by a piezoelectric-electrostrictive coupling, Journal of Applied Physics, 104, page: 034110-034110-4, 2008
 
(929) Nicolaidis M., Alexandrescu D., Perez Ribas R., Low-Cost Highly-Robust Hardened Storage Cells Using Blocking Feedback Transistors, IEEE VLSI Test Symposium (VTS’08), San Diego, California, USA, April 27-Mai 01, 2008
 
(930) Rios D., Low power asynchronous systems, These de Doctorat, 2008
 
(931) Velazco R., Managing transient effects of radiation on complex microelectronic systems, ANDESCON 2008, Cusco (Peru), October 15-17, , 2008
 
(932) Cinquin Ph., Basrour S., Bonvilain A., Moreau-Gaudry A., Medical Needles Deformation Tracking, MICCAI Workshop « Needle Steering », New York, USA, September , 2008
 
(933) Foucard G., Douin A., Pouget V., Bocquillon A., Miller F., Berger G., Ferron J.B., Charlier F., Boldrin F., Velazco R., Perronnard P., Methodologies and Tools for the Evaluation of the Sensitivity to Radiation of SRAM-based FPGAs, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, 2008
 
(934) Shen H., Pétrot F., MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method, Proceedings of the 21st International Conference on VLSI Design, Hyderabad, India, January 4-8, 2008
 
(935) Senouci B., Kouadri Mostéfaoui A., Rousseau F., Pétrot F., Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor prototyping: New Challenges for Embedded Software Designers , Rapid System Prototyping Symposium (RSP’08), Monterey, Cal, USA, June 2-5, 2008
 
(936) Popovici K., Jerraya A. A., Multilevel Communication Modeling for Multiprocessor System-on-Chip, International Symposium on VLSI Design Automation and Test (VLSI-DAT’08), 23-25 April 2008, Hsinchu, Taiwan, 2008
 
(937) Popovici K., Multilevel programming environment for heterogeneous MPSOC architectures, These de Doctorat, 2008
 
(938) Miro-Panades I., Greiner A., Sheibanyrad H., Multisynchronous and Fully Asynchronous NoCs for GALS Architectures, IEEE Design and Test of Computers, 25, page: 572-580, 2008
 
(939) Baron T., NEMS inertial sensor Development on thin SOI and its integration with industrial process, These de Doctorat, 2008
 
(940) Rusu C., Grecu C., Anghel L., Network-on-Chip Fault Tolerance through Checkpoint and Rollback Recovery, National Symposium on System-on-Chip - System-in-Package (GdR SoC-SiP’08), Paris, France, June 4-6, 2008
 
(941) Kouadri Mostéfaoui A., Senouci B., Pétrot F., Networks-In-Package: Performances management and design methodology, IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT’08), Hsinchu, Taiwan, April 23-25, 2008
 
(942) Nicolaidis M., On the state of superposition and the parallel or not parallel nature of quantum computing: a controversy raising view point, European Computing and Philosophy Conference (E-CAP'08), Montpellier, France, June 16-18, 2008
 
(943) Yahya E., Renaudin M., Optimal Asynchronous Linear-Pipelines, The fourth conference on Ph.D. Research in Microelectronics and Electronics (PRIME’08), Istanbul, Turkey, 2008
 
(944) Buhrig A., Optimization of the energy consumption in wireless sensor network nodes, These de Doctorat, 2008
 
(945) Chagoya-Garzon A., Rousseau F., Guérin X., Outils de génération de logiciel pour les systèmes sur puce multi-processeur hétérogènes, 11th Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, France, May 14-16, 2008
 
(946) Schmerber S., Arthaud Y., Mir S., Rufer L., Outils de monitoring per-opératoire de la biomécanique ossiculaire par micro-capteur en chirurgie otologique - Etude de faisabilité, 115eme Congres de la SFORL, Paris, France, 12-14 Oct., 2008
 
(947) Bouchhima A., Pétrot F., Fouillard A.-M., Gligor M., Kriaa L., Jerraya A. A., Parallel Programming of Multi-Processor SoC : A HW-SW Interface perspective, Journal of Parallel Programming, Vol. 36, page: 68-92, 2008
 
(948) Mir S., Carbonero J.L., Bouzaida L., Asquini A., Badets F., PFD output monitoring for RF PLL BIST, 14th IEEE International Mixed-Signals, Sensors and Systems Test Workhop (IMS3TW’08), Vancouver, Canada, June 18-20, 2008
 
(949) Chaudhuri S., Renaudin M., Fesquet L., Razafindraibe A., Beyrouthy T., Danger J.-L., Hoogvorst P., Guilley S., Physical Design of FPGA Interconnect to Prevent Information Leakage, Reconfigurable Computing: Architecture, Tools, and Applications, Springer , 87-98, 2008
 
(950) Paolucci P.S., Jerraya A. A., Popovici K., Rousseau F., Guérin X., Platform based software design flow for heterogeneous MPSoC, Journal on Transactions on Embedded Computing Systems (TECS), Vol.7, page: 27-50, 2008
 
(951) Peronnard P., Pignol M., Bellin D., Velazco R., Foucard G., Ecoffet R., Predicting the SEU Error Rate through Fault Injection for a Complex Microprocessor, IEEE International Symposium on Industrial Electronics (ISIE'2008), Cambridge,UK, June 30 -July 2nd, 2008
 
(952) Clavel R., Pierre L., Leveugle R., Premiers résultats sur l'utilisation d'ACL2 pour l'évaluation de la conséquence des erreurs logiques, 2ème Colloque du GdR SoC-SiP, Paris, France, June 4-6, 2008
 
(953) Bortolin-Argenton E., Feuillebois C., Lefebvre A., Simeu E., Procédé de détection de défaillance d'un capteur analogique et dispositif de détection pour mettre en œuvre le dit procédé, 08/03.420, 2008
 
(954) Borrione D., Zilic Z., Boulé M., Morin-Allory K., Proving and Disproving Assertion Rewrite Rules by Automated Theorem Proving, Proc. of IEEE International High Level Design Validation and Test Workshop (HLDVT'2008), Lake Tahoe, Nevada, USA, November 19-21, 2008
 
(955) Mir S., Simeu E., Stratigopoulos H., Akkouche N., Réduction de tests fonctionnels en utilisant des techniques d'estimation non paramétrique, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, France, Mai 14-16, 2008
 
(956) Boldrin F., Pouget V., Velazco R., Foucard G., Peronnard P., Charlier F., Berger G., Remote SEE Testing Capabilities with Heavy Ions and Laser Beams at CYCLONE-HIF and ATLAS Facilities, Radiation Effects Data Workshop, Tucson, AZ, USA, 14-18 July , 2008
 
(957) Khereddine R., Simeu E., Mir S., RF transceiver parameter identification using regressive models, Conference on Design and Technology of Integrated Systems (DTIS’08), Tozeur, Tunisie, March 25-27, 2008
 
(958) Jean-Mistral C., Scavenging energy with electroactive polymer for wireless autonomus sensor, These de Doctorat, 2008
 
(959) Miscopein B., Schwoerer J., Fesquet L., Renaudin M., Hamon J., Self-Timed Implementation of an Impulse Radio Synchronisation Acquisition Algorithm, Conference on Design and Architectures for Signal and Image Processing (DASIP’08), Bruxelles, Belgium November 24 -26, 2008
 
(960) Mir S., Kupka R., Simeu E., Stratigopoulos H., Rufer L., Tumova O., Signature analysis for MEMS pseudorandom testing using neural networks, 12th IMEKO TC1 & TC7 Joint Symposium on Man Science & Measurement, Annecy, France, September, 3–5, 2008
 
(961) Fouillard A.-M., Pétrot F., Simulation based hardware/software power management exploration for SMP MPSoC, MEDEA+ Desgin Automation Conference, Leuven, Belgique, May , 2008
 
(962) Velazco R., Single Event Effects on digital integrated circuits: origins and mitigation techniques, IEEE International Symposium on Industrial Electronics (ISIE'07), Vigo (Spain), June 4-7, 2008
 
(963) Gauthier D., Bellin D., Peronnard P., Pignol M., Velazco R., Alexandrescu D., Ecoffet R., Single-Event Upset and Soft Error Rate in Power ArchitectureTM microprocessors, Proceedings of Components for Military and Space Electronics (CMSE’08), San Diego (USA), February 11-14, 2008
 
(964) Excoffon C., Maistri P., Leveugle R., Software-based BIST capabilities of the Advanced Encryption Standard, Electronic Symposium Digest of 13th IEEE European Test Symposium, Verbania, Italy, May 25-29, 2008
 
(965) Leveugle R., Maistri P., Excoffon C., Software BIST capabilities of a symmetric cipher, International Conference on Electronics, Circuits and Systems (ICECS), Saint Julians, Malta, September 1-3, 2008
 
(966) Bonaciu M., Amblard P., Demontes L., Software for Multi Processor System on Chip: moving from generic RISC platforms to CELL, Rapid System Prototyping Symposium (RSP’08), Monterey, Cal, USA, June 2-5, 2008
 
(967) Maistri P., Excoffon C., Leveugle R., Software self-testing of a symmetric cipher with error detection capability, 14th IEEE International On-Line Testing symposium, Rhodes, Greece, July 6-9, 2008
 
(968) Nicolaidis M., Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force?, 14th IEEE International Symposium On-Line Testing (IOLT’08), July 7-9, 2008
 
(969) Yahya E., Renaudin M., Lopin G., Standard-Logic Quasi Delay Insensitive Registers, Proc. of 16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC’08), Rhodes Island, Greece, 2008
 
(970) Dang T., Anghel L., Leveugle R., Structures robustes pour circuits logiques à base de CNTFET, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, France, Mai 14-16, 2008
 
(971) Rufer L., Tomaska M., Lalinsky T., Vanko G., Ryger I., Hascik S., Vincze A., Mozolova Z., Surface acoustic wave excitation on SF6 plasma treated AlGaN/GaN heterostructure, The 7th Inter. Conf. Advanced Semicond. Devices Microsyst (ASDAM’08), Smolenice Castle, Slovakia, October 12-16, 2008
 
(972) Mozolova Z., Vincze A., Lalinsky T., Ryger I., Rufer L., Vanko G., Hascik S., Tomaska M., Surface Acoustic Wave Excitation on SF6 plasma treated AlGaN/GaN heterostructure, 12th Joint Vacuum Conference, 10th European Vacuum Conference, 7th Annual Meeting of the German Vacuum Society, Balatonalmádi, Lake Balaton - Hungary, September 22 - 26 , 2008
 
(973) Renaudin M., Fesquet L., Alsayeg K., Rios D., Sicard G., Synthesis of asynchronous QDI FSM based on optimized sequencers, 34th European Conference on Solid-States Circuits (ESSCIRC’08), ESS Fringe Poster Session, Edinburgh, Scotland, 2008
 
(974) Lechuga Y., Bracho S., Mir S., Bounceur A., Mozuelos R., Martinez M., Test limit evaluation for an ADC Design-for-Test approach by using a CAT platform, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, November 12-14, 2008
 
(975) Basrour S., Boussetta H., Marzencki M., Top-Down Behavioral Modeling Methodology of a Piezoelectric Microgenerator For Integrated Power Harvesting Systems , Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'08), Nice, French Riveria, France, 9-11 April , 2008
 
(976) Kolonis E., Nicolaidis M., Towards a Holistic CAD Platform for Nanotechnologies, Microelectronics journal, Volume 39, page: 1032-1040, 2008
 
(977) Rolland R., Hedde D., Horrein P.-H, Pétrot F., Rousseau Fra., Une plate-forme d'expérimentation multiprocesseur pour les réseaux sans fil , 10èmes Journées Pédagogiques du CNFM, 26-28 Novembre 2008, Saint-Malo, France , 2008
 
(978) Leveugle R., Portolan M., Roche P., Vanhauwaert P., Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Saint Julians, Malta, September 1-3, 2008
 
(979) Pétrot F., Augé I., User Guided High Level Synthesis, High Level Synthesis, from Algorithm to Digital Circuit, Springer , 171-196 , 2008
 
(980) Mir S., Rufer L., Khereddine R., Simeu E., Nguyen H.N., Cauvet P., Using signal envelope detection for online and offline RF MEMS switch testing, VLSI Design, Vol. 2008, Article ID 294014, page: 10 pages, 2008
 
(981) Velazco R., Peronnard P., Rhod E., Carro L., Lisboa C.A., Validation by Fault Injection of a Hardening Technique for Matrix Multiplication Algorithms , European Workshop on Radiation Effects on Components and Systems (RADECS’08), Jyväskylä, Finland, September 10-12, 2008
 
(982) Rolindez L., A BIST technique for Sigma-Delta ADCs, These de Doctorat, 2007
 
(983) Anghel L., Lazzari C., Reis R., A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis, JETTA - Journal of Electronic Testing: Theory and Application, 23 (6), page: 625-633, 2007
 
(984) Rousseau F., Aboulhamid E.M., Dubois Ma., Accelerations for Heterogeneous Systems Cosimulation, Proceedings of International Conference on Electronics, Circuits and Systems (ICECS’07), Marrakech, Morocco, December 11-14, 2007
 
(985) Jean-Mistral C., Basrour S., Chaillout J.J., Bonvilain A., A complete study of electroactive polymers for energy scavenging: modelling and experiments, Proceedings of Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2007, Stresa, lago Maggiore, Italy, 2007
 
(986) Qaisar S.-M., Fesquet L., Renaudin M., Adaptive Rate Filtering for a Signal Driven Sampling Scheme, 32nd IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’07), Honolulu, Hawaï, USA, 15-20 April , 2007
 
(987) Qaisar S.-M., Fesquet L., Renaudin M., Adaptive Rate Sampling and Filtering for Low Power Embedded Systems, Sampling Theory and Applications (SampTA’07), Thessaloniki, Greece, 1 - 5 June , 2007
 
(988) Galy N., Courtois B., Charlot B., A full fingerprint verification system for a single-line sweep sensor, Sensors Journal , Volume: 7, page: 1054-1065 , 2007
 
(989) Pierre L., Schmaltz J., Borrione D., Helmy A., A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study, ACM/IEEE International Symposium on Networks-on-Chips (NOCS'2007), Princeton (New Jersey), May 7-9, 2007
 
(990) Labonne E., Renaudin M., Sicard G., A High Dynamic Range CMOS Imager with a Light Adaptive System and Digital Outputs, Workshop on "Image Sensors analog and digital on-chip processing", Toulouse, France, November 21-22, 2007
 
(991) Lalinsky T., Rufer L., Mir S., Vanko G., AlGaN/GaN heterostructure based surface acoustic wave structures for chemical sensors, 11th Int. Conf. on the Formation of Semiconductor Interfaces (ICFSI’07), Manaus, Brazil, August 19-24, 2007
 
(992) Pierre L., A Model for Assertion-Based Verification of TLM Designs, ISRN: TIMA-RR--07/09-01--FR, 2007
 
(993) Maingot V., Leveugle R., Analysis of Laser-Based Attack Effects on a Synchronous Circuit, International Design and Test Workshop (IDT’07), Cairo, Egypt, December 16-18, 2007
 
(994) André E., Renaudin M., Goulier J., A new analytical approach of the impact of jitter on continuous time delta sigma converters , International Conference on Very Large Scale Integration (VLSI-SoC'07), Atlanta, October 15-17, 2007
 
(995) Wong M., Zohar Y., Rufer L., Zhu R., Ma W., An integrated floating-electrode electric micro-generator, Journal of Microelectromechanical Systems, 16, page: 29-37, 2007
 
(996) Labonne E., Sicard G., Renaudin M., An on-pixel FPN reduction method for a high dynamic range CMOS imager, 33rd European Solid-State Circuits Conference (ESSCIRC’07), Munich, Germany, September 11-13, 2007
 
(997) Koren I., Maistri P., Breveglieri L., An operation-centered approach to fault detection in symmetric cryptography ciphers, IEEE Transactions on Computers, Vol. 56, page: 635-649, 2007
 
(998) Beyrouthy T., Razafindraibe A., Renaudin M., Hoogvorst P., Guilley S., Danger J.-L., Fesquet L., Chaudhuri S., A novel asynchronous e-FPGA architecture for security applications, International Conference on Field-Programmable Technology (ICFPT'07), Kokurakita, Kitakyushu, Japan, December 12th - 14th, 2007
 
(999) Maistri P., Vanhauwaert P., Leveugle R., A novel double-data-rate AES architecture resistant against fault injection, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC’07), Vienna, Austria, September 10, 2007
 
(1000) Nicolaidis M., A Numerical Philosophy of the Universe and the Fundamental Nature of Computer Science, Asia-Pacific Computing and Philosophy Conference (AP-CAP’07), Bangkok, Thailand, November 2-4, 2007
 
(1001) Nicolaidis M., A Numerical Philosophy of the Universe and the Fundamental Nature of Computer Science , ISRN: TIMA-RR--07/10-02--FR, 2007
 
(1002) Velazco R., Franco F., A Portable Low-Cost SEU Evaluation Board for SRAMs, Proceedings of Spanish Conference on Electron Devices (SCED’07), Madrid, Spain, January 31-February 2, 2007
 
(1003) Beyrouthy T., Fesquet L., Razafindraibe A., Hoogvorst P., Guilley S., A Reconfigurable Cell for a Multi-Style Asynchronous FPGA, Reconfigurable Communication-centric SoC (RecoSoC’07), Montpellier, 18-20 juin, 2007
 
(1004) Vivet P., Koch-Hofer C., Renaudin M., Thonnard Y., ASC, a SystemC extension for Modeling Asynchronous Systems, and its application to an Asynchronous NoC, ACM/IEEE International Symposium on Networks on Chip (NOCs’07), Princeton, New Jersey, USA, May 7-9, 2007
 
(1005) Rolindez L., Mir S., Carbonero J.L., Goguet D., Chouba N., A Stereo Audio ΣΔ ADC Architecture with Embedded SNDR Self-Test, International Test Conference (ITC’07), Santa Clara, USA, October 23-25, 2007
 
(1006) Bouesse G.F., Ninon N., Sicard G., Renaudin M., Boyer A., Sicard E., Asynchronous logic Vs Synchronouos logic: Concrete results on electromagnetic emissions and conducted susceptibility, 6th International workshop on electromagnetic compatibility of integrated circuits (EMC Compo'07), Torino, Italy, November 28-30, 2007
 
(1007) Morin-Allory K., Fesquet L., Borrione D., Asynchronous online monitoring of logical and temporal assertions, 10th Forum on Specification and Design Languages (FDL'07), Barcelona, Spain, 18-20 September, 2007
 
(1008) Lazzari C., Reis R., Anghel L., A Transistor Placement Technique Using Genetic Algorithm And Analytical Programming , VLSI-SOC: From Systems to Silicon, (selected contributions from VLSI-SoC’05) , Springer , 331-344, Vol.240, 2007
 
(1009) Bregier V., Automatic synthesis of optimised proven quasi delay insensitive asynchronous circuits, These de Doctorat, 2007
 
(1010) Cho Y., Jerraya A. A., Zergainoh N.-E., Choi K., Buffer Size Reduction through Control-Flow Decomposition, Proceedings of IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'07), Daegu, Korea, August 21-23, 2007
 
(1011) Simeu E., Rolindez L., Bounceur A., Mir S., CAT platform for analogue and mixed-signal test evaluation and optimization, VLSI-SoC: Research trends in VLSI and Systems on Chip, Springer , 280-300, 2007
 
(1012) Bounceur A., CAT platform for mixed signal testing, These de Doctorat, 2007
 
(1013) Nicolaidis M., Cellule de mémorisation durcie / Resistant Memory Cell , WO/2007/006909 International Application No.: PCT/FR2006/001590 , 2007
 
(1014) Renaudin M., Circuits et Systèmes Electronique sans Horloge, Invited Talk on 9ème Rencontres Electronique de Dijon, Dijon, France, June 4-8, 2007
 
(1015) Renaudin M., Clockless circuits and systems , Rencontres Electronique du CNRS, Dijon, France, 4 -8 juin , 2007
 
(1016) Anghel L., CMOS and post CMOS Robust Design, HDR, 2007
 
(1017) Pasca V., Leveugle R., Dang T., Anghel L., CNTFET-based CMOS-like gates and dispersion of characteristics, International Design and Test Workshop (IDT’07), Cairo, Egypt, December 16-18, 2007
 
(1018) Dang T., Anghel L., Leveugle R., CNTFET-based logic gates and characteristics, IEEE Silicon Nanoelectronics Workshop (SNW’07), Kyoto, Japan, June 10-11, 2007
 
(1019) Pregaldiny F., Lallement C., Goguet J., Dang T., Leveugle R., Anghel L., Zimmer T., O'Connor I., Liu J., Fregonese S., Gaffiot F., Manneux C., CNTFET modeling and reconfigurable logic circuit design, JETTA - Journal of Electronic Testing: Theory and Application, Vol. 54, No. 11, November, page: 2365-2379, 2007
 
(1020) Marzencki M., Basrour S., Belgacem B., Muralt P., Colin M., Comparison of piezoelectric MEMS mechanical vibration energy scavengers, Nanotech 2007, Santa Clara, California, USA, 2007
 
(1021) Qaisar S.-M., Fesquet L., Renaudin M., Computationally Efficient Adaptive Rate Sampling and Filtering, 15th European Signal Processing Conference (EUSIPCO’07),Poznan, Poland, September 3-7, 2007
 
(1022) Nicolaidis M., Computational Opportunities and CAD for Nanotechnologies, Invited presentation, Computer-Aided Network DEsign Workshop (CANDE’07), Long Beach, CA, USA, September 6-8 , 2007
 
(1023) Nicolaidis M., Kolonis E., Computational Opportunities and CAD for Nanotechnologies, Design Automation and Test in Europe Conference (DATE’07), Acropolis – Nice, France, 2007
 
(1024) Ferron J.B., Maingot V., Douin A., Pouget V., Leveugle R., Configuration errors analysis in SRAM-based FPGAs: software tool and practical results , Microelectronics Reliability, Volume 47, Issues 9-11, September-November , page: pp. 1836-1840, , 2007
 
(1025) Folco B., Contribution to the Synthesis of Quasi Delay Insensitive Asynchronous Circuits, Application to Secured Systems., These de Doctorat, 2007
 
(1026) Nicolaidis M., Anghel L., Cost Reduction and Evaluation of a Temporary Faults Detecting Technique, Design, Automation, and Test in Europe (DATE) “The Most Influential Papers of 10 Years”, Springer , 423-438 , 2007
 
(1027) Nicolaidis M., Dealing with soft errors in nanometric CMOS, Invited presentation in IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH’07), San-Jose (CA), USA, October 21-22 , 2007
 
(1028) Dragulinescu A., Lizarraga L., Mir S., Sicard G., Defect and fault modelling of CMOS active pixel sensors, IEEE Latin American Test Workshop (LATW’07), Cuzco, Peru, March 11 - 14, 2007
 
(1029) Nicolaidis M., Anghel L., Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies, Computational and Ambient Intelligence , Springer , 422-429, 2007
 
(1030) Anghel L., Nicolaidis M., Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies, Special Session of International Work-Conference on Artificial Neural Networks (IWANN’07), San Sebastian, Spain, June, 2007
 
(1031) Nicolaidis M., Anghel L., Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies, International Conference on Artificial Neural Networks (IWANN), June 20-22, San Sebastian, Spain , 2007
 
(1032) Fiandino M., Definition of a new method in order to implement a network of thousand heterogenous processors on a chip, These de Doctorat, 2007
 
(1033) Renaudin M., Delay Insensitivity: a key property for future designs and technologies, 6ème journées d'études Faible Tension Faible Consommation (FTFC'07), Paris, France, May 21-23, 2007
 
(1034) Marzencki M., Ammar Y., Basrour S., Design, fabrication and characterization of a piezoelectric MEMS, vibration energy scavenging, Proceedings of Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP’07), Stresa Italy, April 25-27, 2007
 
(1035) Marzencki M., Design of MEMS micro power generators for autonomous systems on chip, These de Doctorat, 2007
 
(1036) Ammar Y., Design of power management system for autonomous microsystems, These de Doctorat, 2007
 
(1037) Bonacini S., Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS, These de Doctorat, 2007
 
(1038) Rufer L., Simeu E., Khereddine R., Nguyen H.N., Mir S., DFT for MEMS, Invited Talk, RF-MEMS Workshop on Industry Applications: “RF power MEMS: reliability and applications”, Barcelona, Spain, June 28, 2007
 
(1039) Bonvilain A., Cinquin Ph., Lamraoui H., Mozer P., Robain G., Dispositif de prévention des fuites urinaires , FR0757159 / W02009/027196, 2007
 
(1040) Leveugle R., Early analysis of fault-based attack effects in secure circuits, IEEE Transactions on Computers, Vol.56, page: 1431-1434, 2007
 
(1041) Portolan M., Leveugle R., Effective checkpoint and rollback using hardware/OS collaboration, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), Rome, Italy, September 26-28, 2007
 
(1042) Pétrot F., Sahnine C., Zergainoh N.-E., Callonnec D., Efficient Design Approach and Advanced Architectures for Universal OFDM Systems, PhD research in Microelectronics and Electronics (PRIME’07), Bordeaux, France, July, 2007
 
(1043) Rousseau F., Paolucci P.S., Jerraya A. A., Popovici K., Guérin X., Efficient software development platforms for multimedia applications at different abstraction levels , IEEE/IFIP International Workshop on Rapid System Prototyping (RSP’07), Porto Alegre, RS, Brazil, 28-30 May , 2007
 
(1044) Rufer L., ELECTROACOUSTIC AND ULTRASOUND TRANSDUCERS: FROM MACRO- TO MICRO-SYSTEMS, HDR, 2007
 
(1045) Nicolaidis M., Electronic circuitry protected against transient disturbances and method for simulating disturbances, 7274235 , 2007
 
(1046) Nicolaidis M., Emergence of Relativistic Space-Time in a Computational Universe, ISRN: TIMA-RR--07/10-03--FR, 2007
 
(1047) Nicolaidis M., Emergence of Relativistic Space-Time in a Computational Universe, Asia-Pacific Computing and Philosophy Conference (AP-CAP’07), Bangkok, Thailand, November 2-4, 2007
 
(1048) Khereddine R., Nguyen H.N., Simeu E., Mir S., Envelope detection based transition time supervision for online testing of RF MEMS switches, IEEE International On-Line Test Symposium (IOLT’07), Crete, Greece, July 8-11, 2007
 
(1049) Bezerra F., Ecoffet R., Ferrer A., Velazco R., Error rate issued from a multiple upset injection method with realistic time distribution: A case study, 8th Latin-American Test Workshop (LATW’07), Cuzco, Peru, March 12-14, 2007
 
(1050) Velazco R., Faure F., Error rate prediction for digital architectures: test methodology and tools, Radiation effects on embedded systems, Springer , 233-258, 2007
 
(1051) Grecu C., Anghel L., Pande P.P., Ivanov A., Saleh R., Essential Fault-Tolerance Metrics for NoC Infrastructures, IEEE International On-Line Test Symposium (IOLT’07), Crete, Greece, July 8-11, 2007
 
(1052) Simeu E., Mir S., Bounceur A., Rolindez L., Estimation of test metrics for the optimisation of analogue circuit testing, JETTA - Journal of Electronic Testing: Theory and Application, 23 (6), page: 471-484, 2007
 
(1053) Renaudin M., Sicard G., Fragoso J., Estimation rapide du couple énergie/délai des circuits asynchrones QDI, Technique et Science Informatiques (TSI), 26, page: 535-565, 2007
 
(1054) Guironnet de Massas P., Etude des problèmes de cohérence mémoire dans des systèmes multiprocesseurs à mémoire partagée intégrés sur une même puce, Journées GDR SoC-SiP, Session Posters P2, 2.15, Paris, France, June 13-15 , 2007
 
(1055) Lizarraga L., Sicard G., Mir S., Evaluation of a BIST technique for CMOS imagers, Asian Test Symposium (ATS’07), Beijing, China, October 8-11, 2007 , 2007
 
(1056) Maistri P., Vanhauwaert P., Leveugle R., Evaluation of register-level protection techniques for the Advanced Encryption Standard by multi-level fault injections, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07), Rome, Italy, September 26-28, 2007
 
(1057) Carbonero J.L., Tongbong J., Mir S., Evaluation of test measures for LNA production testing using a multinormal statistical model, Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07, 2007
 
(1058) Mourtel C., Feyt N., Rigaud J.B., Leveugle R., Ammari A., Moitrel P., Tria A., Maingot V., Teyssou E, Experimental Evaluation of Protections Against Laser-induced Faults and Consequences on Fault Modeling, Design, Automation & Test in Europe Conference & Exhibition (DATE '07),Nice, France, 16-20 April, 2007
 
(1059) Velazco R., Marques C.A., Viganotti G., Ferreyra P., Ferreyra R., Failure and coverage factors based Markoff models: a new approach for improving the dependability estimation in complex fault tolerant systems exposed to SEUs, IEEE Transactions on Nuclear Science, Vol. 54, page: 912-91, 2007
 
(1060) Jerraya A. A., Gerin P., Shen H., Chureau A., Bouchhima A., Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC, 12th Asia and South Pacific Design Automation Conference ASP-DAC 2007, Yokohama, Japan, January 23-26 , 2007
 
(1061) Guérin X., Popovici K., Rousseau F., Jerraya A. A., Youssef W., Flexible Application Software Generation for Heterogeneous Multi-Processor System-on-Chip, Computer Software and Application Conference (COMPSAC’07), Beijing, Chine, July 23-27, 2007
 
(1062) Monnet Y., Leveugle R., Renaudin M., Formal analysis of quasi delay insensitive circuits behavior in the presence of SEUs, 13th IEEE International On-Line Testing symposium (IOLT’07), Hersonissos-Heraklion, Crete, Greece, July 8-11, 2007
 
(1063) Akkouche N., Bounceur A., Mir S., Simeu E., Functional test compaction by statistical modelling of analogue circuits, 13th IEEE International Mixed-Signals Testing Workhop (IMSTW’07), Porto, Portugal, June 18-20, 2007
 
(1064) Nicolescu G., Jerraya A. A., Global Specification and Validation of Embedded Systems: Integrating Heterogeneous Components, Springer , , 2007
 
(1065) Nicolaidis M., GRAAL: A Fault Tolerant Architecture for Enabling Nanometric Technologies , 13th IEEE International On-Line Testing symposium (IOLT’07), Hersonissos-Heraklion, Crete, Greece, July 8-11, 2007
 
(1066) Nicolaidis M., GRAAL: A New Fault-tolerant Design Paradigm for Mitigating the Flaws of Deep-Nanometric Technologies, Proceedings of IEEE International TEST Conference (ITC’07), Santa Clara, Ca., USA, October 23-25, 2007
 
(1067) Marchioro G.F., Romdhani M., Ben Ismail T., Zergainoh N.-E., Gauthier L., Baghdadi A., Le Marrec Ph., Coste P., Hessel F., Jerraya A. A., Daveau J.- M., Valderrama C., Hardware/Software Codesign , Design of Systems on Chip, Design and test, Springer , 133-158, 2007
 
(1068) Labonne E., High dynamic range CMOS imager design, These de Doctorat, 2007
 
(1069) Bocquillon A., Foucard G., Miller F., Leveugle R., Daniel C., Rakers S., Pouget V., Velazco R., Buard N., Carriere T., Highlights of laser testing capabilities regarding the understanding of SEE in SRAM Based FPGAs, 9th European Conference on Radiation and its Effects on Components and Systems (RADECS’07), Deauville, France, September 10-14, 2007 , 2007
 
(1070) Bouesse G.F., Renaudin M., Sicard G., Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals, VLSI-SOC: From Systems to Silicon, Springer , 11-24, Vol. 240, 2007
 
(1071) Kriaa L., Pétrot F., Low power hardware dependent software for Multiprocessor System on Chip , MEDEA+ Desgin Automation Conference (DAC’07), Grenoble, France, May , 2007
 
(1072) Houari A., Gligor M., Bouchhima A., Pétrot F., Kriaa L., Low Power oriented Hardware dependent Software Implementation in MPSoC Architectures, Proceedings of North-East Workshop on Circuirs and Systems (NEWCAS’07), Montreal, Canada, August 5-8, 2007
 
(1073) Cho Y., Zergainoh N.-E., Jerraya A. A., Choi K., Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes, Proceedings of IEEE/IFIP International Workshop on Rapid System Prototyping (RSP’07), Porto Alegre, Brazil, May 28-30, 2007
 
(1074) Carro L., Jerraya A. A., Guérin X., Reis R., Brisolara L., Chae Soo-Ik, Han Sang-Il, Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC, Design Automation for Embedded Systems, 11, page: 249-283, 2007
 
(1075) Renaudin M., Julien N., Méthodes et outils pour la conception de SoC faible consommation, Technique et Science Informatiques (TSI), 26, page: 505-508, 2007
 
(1076) Mir S., Simeu E., Akkouche N., Bounceur A., Minimization of functional tests by statistical modelling of analogue circuits, Conference on Design and Technology of Integrated Systems (DTIS’07), Rabat, Morocco,September 2-5, 2007
 
(1077) Guérin X., Brisolara L., Jerraya A. A., Popovici K., Mixed hardware software multilevel modeling and simulation for multithreaded heterogeneous MPSoC, International Symposium on VLSI Design, Automation and Test (VLSI-DAT’07), Hsinchu, Taiwan, April 25-27, 2007
 
(1078) Jerraya A. A., Pétrot F., Chureau A., Gerin P., Bouchhima A., Shen H., Modélisation des interfaces matériel/logiciel, 1ère école d’hiver francophone sur les systèmes hétérogènes, Villard-de-Lans, France, 10-12 janvier , 2007
 
(1079) Zenati A., Modelling and simulation of the mixed signal and multi domain Microsystems : toward virtual prototyping of an autonomous microsystem, These de Doctorat, 2007
 
(1080) Quartana J., Fesquet L., Renaudin M., Modular asynchronous Network-on-Chip: application to GALS systems rapid prototyping, VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005), Springer , 195-207, 2007
 
(1081) Leveugle R., Maistri P., Multi-cycle Fault Injections in Error Detecting Implementations of the Advanced Encryption Standard, International Design and Test Workshop (IDT’07), Cairo, Egypt, December 16-18, 2007
 
(1082) Violante M., Sonza Reorda M., Rebaudengo M., Anghel L., Multilevel Fault Effects Evaluation, Radiation Effects on Embedded Systems, Springer , 69-88, 2007
 
(1083) Basrour S., Boussetta H., Marzencki M., Multilevel Modeling of Integrated Power Harvesting System using VHDL-AMS and SPICE, Proceedings of Behavioral Modeling and Simulation Workshop (BMAS’07)2007, IEEE International, 2007
 
(1084) Rusu C., Bougerol A. , Anghel L., Weulerse C., Buard N., Benhammadi S., Renaud N., Wrobel F. , Carriere T., Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells , IEEE International On-Line Testing symposium (IOLTS’07), Hersonissos-Heraklion, Crete, Greece, 2007
 
(1085) Slamani M., Stratigopoulos H., Drineas P., Makris Y., Non-RF to RF test correlation using learning machines: a case-study, 25th IEEE VLSI Test Symposium, (VTS’07), Berkeley USA, May 6-10, 2007
 
(1086) Basrour S., Terrasson G., Briand R., Nouvelle approche pour la conception d'un émetteur-récepteur très faible consommation, Journées GDR SOC-SIP'07, Paris, France, 13-15 June , 2007
 
(1087) Bastien F., Metzger M., Aboulhamid E.M., Vachon J., Rousseau F., Observer-based verification using introspection: a system-level verification implementation, Advances in Design and Specification Languages for Embedded Systems – Selected Contributions from FDL’06, Springer , 209-224, 2007
 
(1088) Dhayni A., Mir S., Rufer L., On-Chip pseudorandom testing for linear and non-linear MEMS, VLSI-SOC: From Systems to Silicon, Springer , 245-266, Vol. 240, 2007
 
(1089) Smekens C., Leveugle R., On deratings to refine system-level failure rate estimations, International Conference on Electronics, Circuits and Systems (ICECS’07), Marrakech, Morocco, December 11-14, 2007
 
(1090) Borrione D., Morin-Allory K., On-line monitoring of properties built on regular expressions sequences, Advances in Design and Specification Languages for Embedded Systems (Selected Contributions from FDL'06), Springer , 197-207, 2007
 
(1091) Guironnet de Massas P., Pétrot F., Amblard P., On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration, VLSI Design, 2007, page: 10 p., 2007
 
(1092) Maingot V., Leveugle R., On the use of error correcting and detecting codes in secured circuits , Proceedings of the 2007 PH.D Research in Microelectronics and Electronics conference nics (PRIME’07), Bordeaux, France, July 2-5, 2007
 
(1093) Maingot V., Leveugle R., On the use of error correcting codes in secured circuits, 8th Latin-American Test Workshop (LATW’07), March 12-14, 2007
 
(1094) Buhrig A., Renaudin M., On the use of real-time specifications for reducing power consumption in wireless sensor network, 6èmes journées d'études Faible Tension Faible Consommation (FTFC’07), Paris, France, 21-23 May, 2007
 
(1095) Noury N., Rufer L., Arthaud Y., Mir S., Dauvé S., Schmerber S., Outils de monitoring per-opératoire dans la chirurgie de l'oreille moyenne, Journées GDR MNS, Toulouse, France, 21-23 Novembre, 2007
 
(1096) Mamalet F., Renaudin M., Coulon P.Y., Galilee B., Parallel asynchronous watershed algorithm-architecture, IEEE Transactions on Parallel and Distributed Systems, 18, page: 44-56, 2007
 
(1097) Renaudin M., Yahya E., Performance Modeling and Analysis of Asynchronous Linear-Pipeline, Journées GDR SOC-SIP'07, Paris, France, 13-15 June , 2007
 
(1098) Yahya E., Renaudin M., Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays, 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS’07), Marrakech, Morocco, December 11-14, 2007
 
(1099) Folco B., Rios D., Renaudin M., Monnet Y., Power consumption profile analysis of asynchronous QDI circuits , 6ème journées d'études Faible Tension Faible Consommation (FTFC’07), ISEP – Paris, France, 21-23 May, 2007
 
(1100) Rousseau F., Senouci B., Kouadri Mostéfaoui A., Pétrot F., Prototypage d'Applications POSIX sur une architecture Multiprocesseur, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’07), Lilles, France, May 14-16, 2007
 
(1101) Oddos Y., Morin-Allory K., Borrione D., Prototyping Generators for On-line Test Vector Generation Based on PSL Properties, Proc. of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), Krakow, April 11-13, 2007
 
(1102) Jerraya A. A., Senouci B., Rousseau F., Bouchhima A., Prototyping Multiprocessor System-on-Chip Applications: A Platform-Based Approach, IEEE Distrubuted Systems Online, Volume: 8, page: 2-2, 2007
 
(1103) Reis R., Fouillat P., Velazco R., Radiation effects on embedded systems, Springer , 269 p., 2007
 
(1104) Akkouche N., Mir S., Bounceur A., Réduction de tests fonctionnels par modélisation statistique des circuits analogiques, 10th Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’07), Lille, France, May 14-16, 2007
 
(1105) Nguyen H.N., Rufer L., Simeu E., Mir S., RF MEMS series capacitive switch: test and diagnosis, Journées GDR SoC-SiP’07, Paris, France, June , 2007
 
(1106) Kouadri Mostéfaoui A., Pétrot F., Senouci B., Scalable Multi-FPGA Platform for Networks-On-Chip Emulation, 18thInternational Conference Application-specific Systems, Architectures and Processors (ASAP’07), Montréal, Canada, July 9 -11, 2007
 
(1107) Jerraya A. A., Choi K., Cho Y., Zergainoh N.-E., Yoo S., Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip , Design Automation for Embedded Systems, 11, page: No. 2-3, pp. 167-191, 2007
 
(1108) Razafindraibe A., Fesquet L., Renaudin M., Beyrouthy T., Secure Asynchronous FPGA for Embedded Systems (SAFE), Colloque Journées GDR SOC-SIP'07, Paris, France, June 13-15, 2007
 
(1109) Santos M.B., Oliveira A. L., Teixeira J.P., Velazco R., Fernandes J. M., Sensitivity to SEUs evaluation using probabilistic testability analysis at RTL, 8th Latin-American Test Workshop (LATW’07), Cuzco, Peru, March 12-14, 2007
 
(1110) Rousseau F., Nicolescu G., Aboulhamid E.M., Lapalme J., Separating modeling and simulation aspects in hardware/software framework-based modeling languages , The Arabian Journal for Science and Engineering, 32, Number 2C, December , page: 41 - 60, 2007
 
(1111) Pétrot F., Shen H., Service Dependency Graph for HW/SW Interfaces Modeling: The Motion-JPEG Case Study, Proc. of The 7th International Conference on ASIC (Asicon’07), Guilin, China, October 26-29, 2007
 
(1112) Ammari A., Anghel L., Leveugle R., Lazzari C., Reis R., SET fault injection methods in analog circuits: case study, 8th Latin-American Test Workshop (LATW’07), March 12-14, 2007
 
(1113) Alexandrescu D., Simulation Tools for Transient Faults, These de Doctorat, 2007
 
(1114) Popovici K., Jerraya A. A., Simulink based Hardware-Software Codesign Flow for Heterogeneous MPSoC, Summer Computer Simulation Conference (SCSC'07), San Diego, California, USA, 2007
 
(1115) Atat Y., Simulink-based MPSoC Design: Bridge between Algorithm and Architecture Design, These de Doctorat, 2007
 
(1116) Popovici K., Yan X., Huang K., Han Sang-Il, Brisolara L., Guérin X., Li L., Chae Soo-Ik, Carro L., Jerraya A. A., Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264, Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007
 
(1117) Atat Y., Zergainoh N.-E., Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design, Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), Porto Alegre, Brazil, 2007
 
(1118) Huertas J.L., Espinosa-Duran J.- M., Velazco R., Velasco-Medina J., Huertas G., Single event transient injection on an operational amplifier: a case study, 8th Latin-American Test Workshop (LATW’07), Cuzco, Peru, March 12-14, 2007
 
(1119) Oyamada M., Software performance estimation in MPSoC design, These de Doctorat, 2007
 
(1120) Bonaciu M., Oyamada M., Wagner F.R., Cesario W., Jerraya A. A., Software Performance Estimation in MPSoC Design, 12th Asia and South Pacific Design Automation Conference (ASP-DAC’07), Yokohama, Japan, January 23-26 , 2007
 
(1121) Mozer P., Lamraoui H., Robain G., Cinquin Ph., Bonvilain A., Sphincter urinaire électronique dynamique , 3ème Conférence Internationale SURGETICA, Chambery, France, September 19-21, 2007
 
(1122) Monnet Y., Study and modelling of secure circuits against non invasive fault injection attacks, These de Doctorat, 2007
 
(1123) Gascard E., Borrione D., Morin-Allory K., Synthesis of property monitors for online fault detection, Journal of Circuits, Systems, and Computers (JCSC) , 16, page: 943 - 960 , 2007
 
(1124) Renaudin M., Fesquet L., Bregier V., Folco B., Technology mapping for area optimized quasi delay insensitive circuits, VLSI-SOC: From Systems to Silicon, Springer , 55-69, Vol. 240, 2007
 
(1125) Asquini A., Mir S., Carbonero J.L., Test measurements evaluation for VCO and charge pump blocks in RF PLLs, SPIE International Symposium on Microtechnologies for the New Millenium, VLSI Circuits and Systems Conference, Gran Canaria, Spain, 10 May , 2007
 
(1126) Aubert S., Heusse M., Barthel D., Valois F., Paugnat F., Dohler M., Renaudin M., Buhrig A., Maraninchi F., Dugas C., Mounier L., Duda A., The ARESA Project: Facilitating Research, Development and Commercialization of WSNs, Fourth Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks, SECON 2007, June 18-21, San Diego, California, USA, 2007
 
(1127) Renaudin M., Koch-Hofer C., Timed Asynchronous Circuits Modeling using SystemC, 10th Forum on Specification and Design Languages (FDL'07), Barcelona, Spain, September 18-20, 2007
 
(1128) Ferron J.B., Maingot V., Douin A., Peronnard P., Velazco R., Pouget V., Foucard G., Fouillat P., Lewis D., Leveugle R., Anghel L., Tools and methodology development for pulsed laser fault injection in SRAM-based FPGAs, 8th Latin-American Test Workshop (LATW’07), Cuzco, Peru, 2007
 
(1129) Sahnine C., Pétrot F., Zergainoh N.-E., Callonnec D., Towards a High-Throughput and Low Power Reconfigurable Architecture of Advanced OFDM Modulator for Software-Defined Radio Systems, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’07), Montréal, Canada, August 5-8, 2007
 
(1130) Rufer L., Petrini V., Domingues C., Mir S., Jeannot J.C., Transducteur ultrasonore microusiné compatible CMOS, Ecole MEMS & Acoustique: IEMN - Villeneuve d’Ascq, 3-4 avril , 2007
 
(1131) Lazzari C., Transistor Level Automatic Generation of Radiation-Hardened Circuits , These de Doctorat, 2007
 
(1132) Bezerra F., Ecoffet R., Velazco R., Faure F., Garcia-Valderas M., Peronnard P., Two complementary approaches for studying the effects of SEUs on digital processors, IEEE Transactions on Nuclear Science, Vol. 54, page: 924-928, 2007
 
(1133) Amblard P., Un nouveau regard sur la machine logique de Jevons, Technique et Science Informatiques (TSI), 26, page: 1207-1225 , 2007
 
(1134) Mir S., Cauvet P., Nguyen H.N., Rufer L., Simeu E., Khereddine R., Using signal envelope detection for RF MEMS switch testing, 13th IEEE International Mixed-Signals Testing Workhop (IMSTW’07), Porto, Portugal, June 18-20, 2007
 
(1135) Simeu E., Mir S., Khereddine R., Utilisation des techniques de regression pour le test et le diagnostic des composantes RF , Journées GDR SoC-SiP’07, Paris, France, 13 Juin , 2007
 
(1136) De Micheli G., Reis R., Mir S., VLSI-SoC: Research Trends in VLSI and Systems on Chip, Springer , 410 p, 2007
 
(1137) Simeu E., Reis R., De Micheli G., Mir S., 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October 2006, IFIP, 83 p, 2006
 
(1138) Renaudin M., Labonne E., Berger P.-D., Sicard G., A 100dB dynamic range CMOS image sensor with global shutter, 13th IEEE International Conference on Electronics, Circuits and Systems (ICECS’06), Nice, France, December 10-13, 2006
 
(1139) Labonne E., Renaudin M., Sicard G., A 120dB CMOS imager with a light adaptive system and digital outputs, 2nd Conference on Ph.D. Research in Microelectronics and Electronics (PRIME’06), Otranto, Italy, June 12-15, 2006
 
(1140) Mir S., Carbonero J.L., Rolindez L., Bounceur A., A BIST scheme for SNDR testin g of sigma delta ADCs using sine-wave fitting, JETTA - Journal of Electronic Testing: Theory and Application, Volume 22, Numbers 4-6 / December, page: 325-335, 2006
 
(1141) Simeu E., Rolindez L., Bounceur A., Mir S., A CAT platform for analogue and mixed-signal test evaluation and optimization , Digest of Papers of the European Test Symposium (ETS’06), Southampton, UK, 2006
 
(1142) Dubois Ma., Rousseau F., Aboulhamid E.M., Acceleration for a Compiled Transaction Level Modeling Simulation, IEEE International Conference on Electronics, Circuits and Systems (ICECS 2006), pp. 1176-1179, Nice, France, December 10-13, 2006
 
(1143) Pierre L., Helmy A., Borrione D., ACL2-based verification of the communications in the hermes network on chip, Proc. International Workshop on Symbolic Methods and Applications to Circuit Design (SMACD'06), Firenze, Italy, October 12-13, 2006
 
(1144) Jeannot J.C., Rufer L., Domingues C., Mir S., Petrini V., Delobelle P., A CMOS compatible ultrasonic transducer fabricated with deep reactive ion etching, Journal of Microelectromechanical Systems, Vol. 15, page: 1766-1776, 2006
 
(1145) Roche P., Vanhauwaert P., Leveugle R., A flexible SoPC-based fault injection environment, 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Prague, Czech, 2006
 
(1146) Labonne E., Renaudin M., Sicard G., A high dynamic range CMOS image sensor with on-chip FPN reduction method, XXI Conference on Design of Circuits and Integrated Systems (DCIS’06), Barcelona, Spain, November 22-24, 2006
 
(1147) Portolan M., Leveugle R., A highly flexible hardened RTL processor core based on LEON2, IEEE Transactions on Nuclear Science, Volume 53, Part 1, Aug., page: 2069 - 2075, 2006
 
(1148) Nicolaidis M., A low-cost single-event latchup mitigation scheme, 12th IEEE International On-Line Testing symposium (IOLT’06), Como, Italy, July 10-12, 2006
 
(1149) Nicolaidis M., A Numerical Philosophy of the Universe, Radiation Effects on Components and Systems (RADECS 2006), Athens, Greece, September 27-29, 2006
 
(1150) Nicolaidis M., A reconfiguration device for a faulty memory, 7073102, 2006
 
(1151) Mir S., Carbonero J.L., Bounceur A., Rolindez L., A SNDR BIST for SigmaDelta Analogue-to-Digital Converters, VLSI Test Symposium, 2006. Proceedings. 24th IEEE, 30-04 April. Berkeley, California, US, 2006
 
(1152) Fesquet L., Borrione D., Morin-Allory K., Asynchronous Assertion Monitors for multi-Clock Domain System Verification, Proc. 17th IEEE Symposium on Rapid System Prototyping, Chania, Greece, 14-16 June, 2006
 
(1153) Renaudin M., Yahya E., Asynchronous Buffers: Characteristics, Modeling and Design, ISRN: TIMA-RR--06/03-01--FR, 2006
 
(1154) Monnet Y., Renaudin M., Asynchronous design: fault robustness and security characteristics, 12th IEEE International On-Line Testing symposium (IOLT’06), Como, Italy, July 10-12, 2006
 
(1155) Borrione D., Morin-Allory K., Fesquet L., Asynchronous on-line monitoring of PSL assertions, Proc. 17th IEEE Symposium on Rapid System Prototyping, Chania, Greece, 14-16 June , 2006
 
(1156) Caucheteux D., Crochon E., Renaudin M., Beigné E., AsyncRFID: fully asynchronous contactless systems, providing high data rates, low power and dynamic adaptation, 12th IEEE International Symposium on Asynchronous Circuits and Systems, March 13-15., 2006
 
(1157) Lamara K.M., Nicolaidis M., Costa A., Boutobza S., A Transparent based Programmable Memory BIST, Test Symposium, 2006. ETS '06. Eleventh IEEE European , 2006
 
(1158) Pétrot F., Bouchhima A., Youssef W., Gerin P., Jerraya A. A., Kriaa L., A Unified HW/SW Interface Refinement Approach for MPSoC Design, ISRN: TIMA-RR--06/06-01--FR, 2006
 
(1159) Chen X., Pétrot F., Bouchhima A., Youssef W., Jerraya A. A., Kriaa L., A Unified HW/SW Interface Refinement Approach for MPSoC Design, The 4th International IEEE-NEWCAS Conference (NEWCAS’06), Gatineau, Canada, June 18-21, 2006
 
(1160) Zergainoh N.-E., Jerraya A. A., Tambour L., Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 14, page: 349- 360, 2006
 
(1161) Morin-Allory K., Borrione D., Automatic generation of a provable circuit model: from VHDL to PVS, 8ème International Mathematica Symposium (IMS'06), Avignon, France, 21-23 June, 2006
 
(1162) Aboulhamid E.M., David J.P., Brassard O., Kastle M., Rousseau F., Automatic generation of embedded systems with .NET framework based tools, 4th International NorthEast Workshop on Circuits and Systems (IEEE NEWCAS 2006), 2006
 
(1163) Dhayni A., Mir S., Rufer L., Bounceur A., BIST pour les microsystèmes nonlinéaires, Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM'06), Rennes, France, May 10-12 , 2006
 
(1164) Guérin X., Jerraya A. A., Han Sang-Il, Chae Soo-Ik, Buffer memory optimization for video codec application modeled in Simulink, 43rd Design Automation Conference DAC'06, San Francisco, USA, 24-28 July, 2006
 
(1165) Mir S., Rufer L., Dhayni A., Built-in-self-test techniques for MEMS, Microelectronics journal, Vol. 37, page: 1591-1597 , 2006
 
(1166) Moitrel P., Monnet Y., Clavier C., Leveugle R., Renaudin M., Case Study of a Fault Attack on Asynchronous DES Crypto-Processors, 3rd Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 06), Yokohama, Japan, October 10th, 2006
 
(1167) Simeu E., Rolindez L., Bounceur A., Mir S., CAT platform for analogue and mixed-signal test evaluation and optimization , 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October , 2006
 
(1168) Bounceur A., Rufer L., Mir S., Dhayni A., Characterization and testing of MEMS nonlinearities, International Design and Test (IDT’06), Dubai, UAE, November 19-20, 2006
 
(1169) Courtois B., Poppe A., Szabo P., Rencz M., Nemeth B., Characterization of the etching quality in micro-electro-mechanical systems by thermal transient methodology, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP’06), Stresa, Italy, 26-28 April, 2006
 
(1170) Leveugle R., Dang T., Anghel L., CNTFET-based logic gates and simulation, IEEE International Design and Test Workshop (IDT’06), Dubai, UAE, November 19-20, 2006
 
(1171) Leveugle R., Anghel L., Dang T., CNTFET basics and simulation, Design and Test of Integrated Systems (DTIS'06), Tunis, Tunisia, September 5-7, 2006
 
(1172) Quartana J., Renaudin M., Vivet P., Communication node architecture in a globally asynchronous network on chip system, FR2883117, 2006
 
(1173) Kolonis E., Complex Systems, CAD Tools and Nanotechnologies, These de Doctorat, 2006
 
(1174) Beigné E., Caucheteux D., Crochon E., Renaudin M., CONTACTLESS COMMUNICATIONS METHOD BASED ON ASYNCHRONOUS MODULATIONS AND DEMODULATIONS, WO2006108986, 2006
 
(1175) Nicolaidis M., Data storage method with error correction, 7124348 B2, 2006
 
(1176) Dragulinescu A., Lizarraga L., Sicard G., Mir S., Defect and fault modelling of a CMOS n-diffusion photodiode, 3rd International Conference on Advanced Topics in Optoelectronics, Microelectronics and Nanotechnologies (ATOM-N’06), Bucharest, Romania, November 24-26, 2006
 
(1177) Ammari A., Dependability analysis of complex circuits described in a high level language, These de Doctorat, 2006
 
(1178) Roche P., Vanhauwaert P., Leveugle R., Dependability analysis : performance evaluation of environment configurations, International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS'06), Tunis, Tunisia, September 5-7, 2006
 
(1179) Portolan M., Dependable and secure design of an embedded system, These de Doctorat, 2006
 
(1180) Roman C., Design and Modeling of Carbon Nanotube-based Devices for Biosensing Applications, These de Doctorat, 2006
 
(1181) Lemaire R., Design and modelling of a control system for telecommunication applications with a Network-on-Chip (NoC) architecture, These de Doctorat, 2006
 
(1182) Cachera D., Quinton P., Risset T., Morin-Allory K., Designing parallel programs and integrated circuits, 8ème International Mathematica Symposium (IMS'06), Avignon, France, 21-23 June , 2006
 
(1183) Renaudin M., Monnet Y., Leveugle R., Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic, IEEE Transactions on Computers, Volume: 55, page: 1104 - 1115, 2006
 
(1184) Carbonero J.L., Rolindez L., Mir S., Design of a 96-dB Audio SD ADC including a BIST Technique for SNDR Testing , ISRN: TIMA-RR--06/10-02--FR, 2006
 
(1185) Carbonero J.L., Mir S., Rolindez L., Design of a 96-dB audio Sigma-Delta ADC including a BIST technique for SNDR testing, 21st Conference on Design of Circuits and Integrated Systems (DCIS’06), Barcelona, Spain, November , 2006
 
(1186) Petkov I., DESIGN OF MULTIPROCESSOR SYSTEM ON CHIP: LINK BETWEEN SIMULATION AND REALIZATION, These de Doctorat, 2006
 
(1187) Michel B., Courtois B., Design, Test, Integration of MEMS/MOEMS (DTIP 2005): special issue of Journal on Microsystem Technologies, Microsystem Technologies, Vol. 12, page: special issue, 2006
 
(1188) Besbes K., Faiedh H., Torki K., Souani C., Digital hardware implementation of a neural system used for nonlinear adaptive prediction, Journal of Computer Science, Vol.2, page: 355-362, 2006
 
(1189) Wong M., Mir S., Rufer L., Domingues C., Dong J., Electroacoustic and ultrasonic microtransducers, 8th French Acoustical Congress, Tours, France, 24-27 April , 2006
 
(1190) Bouchhima A., Embedded software modeling at different abstraction levels for validation and synthesis of system-on-chips, These de Doctorat, 2006
 
(1191) Nicolaidis M., Emulation/simulation d'un circuit logique, FR2882601 (B1); WO2006090089 (A1) , 2006
 
(1192) Marzencki M., Basrour S., Enhanced models for power output prediction from resonant piezoelectric micro power generators, 20th Eurosensors Conference, Göteborg, Sweden, September 17-20, 2006
 
(1193) Leveugle R., Vanhauwaert P., Environnement d’analyse de sûreté sur SoPC, 9èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, France, May 10-12, 2006
 
(1194) Leveugle R., Maingot V., Error detection code efficiency for secure chips, International Conference on Electronics, Circuits and Systems (ICECS’06) Nice, France, December 10-13, 2006
 
(1195) Mir S., Bounceur A., Simeu E., Rolindez L., Estimation of test metrics for multiple analogue parametric deviations, International Conference on Design and Technology of Integrated Systems (DTIS'06), Tunis, Tunisia, September 5-7, 2006
 
(1196) Rolindez L., Mir S., Simeu E., Bounceur A., Estimation of test metrics for the optimisation of analogue circuit testing , ISRN: TIMA-RR--06/10-03--FR, 2006
 
(1197) Renaudin M., Sicard G., Fragoso J., Estimation rapide du couple énergie/délai des circuits asynchrones QDI, ISRN: TIMA-RR--06/10-01--FR, 2006
 
(1198) Savaria B.Y., Leveugle R., Nicolescu B., Ammari A., Evaluation of a software-based error detection technique by RT-level fault injection, Proceedings - 3rd IEEE International Workshop on Electronic Design, Test & Applications (DELTA’06), Kuala Lumpur, Malaysia, January 17-19, 2006
 
(1199) Bounceur A., Carbonero J.L., Mir S., Tongbong J., Evaluation of test measures for low-cost LNA production testing, PhD Forum at 14th IFIP International Conference on Very Large Scale Integraation (VLSI-SoC’06), Nice, France, October 16-18, 2006
 
(1200) Nicolaidis M., Evaluation of the characteristics of electronic pulses, 7126320, 2006
 
(1201) Amblard P., Guironnet de Massas P., Experiments around SPARC LEON-2 for MPEG encoding, International Conference Mixed Design of Integrated Circuits and Systems (MIXDES’06), Gdynia, Poland, June 22-24, 2006
 
(1202) Ferreyra P., Velazco R., Marques C.A., Viganotti G., Ferreyra R., Failure and coverage factors based Markoff models: a new approach for improving the dependability estimation in complex fault tolerant systems exposed to SEUs, Radiation and its Effects on Components and Systems (RADECS' 06), Athens, Greece, September 16-19, 2006
 
(1203) Bouchhima A., Pétrot F., Rousseau T., Senouci B., Jerraya A. A., Fast Prototyping of POSIX based applications on a Multiprocessor SoC Architecture: “Hardware-dependent Software oriented approach” , Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), Chania, Greece, June, 2006
 
(1204) Amblard P., Finite state evaluation of logical formulas : Jevons' Approach (1870) and contemporary description , Acta Cybernetica, Vol 17, page: 665-684, 2006
 
(1205) Gerin P., Shen H., Chureau A., Bouchhima A., Jerraya A. A., Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC, ISRN: TIMA-RR--06/11-01--FR, 2006
 
(1206) Bonaciu M., Flexible and Scalable Algorithm/Architecture Platform for MP-SoC Design of High Definition Video Compression Algorithms, These de Doctorat, 2006
 
(1207) Fouillard A.-M., Bouchhima A., Sarmento A., Youssef W., Jerraya A. A., Pétrot F., Kriaa L., Flexible hardware/software interface modeling using high level service based component model, The 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'06), April 3-4. Nagoya, JP, 2006
 
(1208) Dumitrascu F., Bonaciu M., Pieralisi L., Bacivarov I., Jerraya A. A., Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application, Design Automation and Test Conference in Europe (DATE'06), Munich, Germany, March 6-10, 2006
 
(1209) Borrione D., Schmaltz J., Formalizing on chip communication in a functional style, Trustworthy Software Workshop, Dagstuhl on-line proceedings, Saarbrücken, Germany, May 15-18, 2006
 
(1210) Schmaltz J., Formalizing On Chip Communications in a Functional Style, These de Doctorat, 2006
 
(1211) Toma D., Formal verification of digital systems using theorem proving: application for cryptographic designs, These de Doctorat, 2006
 
(1212) Han Sang-Il, Chae Soo-Ik, Jerraya A. A., Functional modeling techniques for efficient SW code generation of video codec applications, 11th Asia and South Pacific Design Automation Conference ASP-DAC'06, 24-27 Jan.Yokohama, JP, 2006
 
(1213) Rufer L., Oszi Z., Grobelny D., Mozolova Z., Lalinsky T., Gregus J., Vanko G., Mir S., GaAs and GaN based SAW chemical sensors: acoustic part design and technology , 6th International Conference on Advanced Semiconductor Devices and Microsystems (ASDAM’06), Smolenice, Slovakia, October, 2006
 
(1214) Hunsinger F., Global validation method for system on chip, These de Doctorat, 2006
 
(1215) Youssef W., Hardware/Software interfaces study in the scope of multiprocessor system-on-chip and parallel programming models, These de Doctorat, 2006
 
(1216) Bouchhima A., Chen X., Jerraya A. A., Youssef W., Bonaciu M., Cesario W., High-level architecture exploration for MPEG4 encoder with custom parameters, Design Automation, 2006. Asia and South Pacific Conference on. Yokohama, JP, 2006
 
(1217) Renaudin M., Bouesse G.F., Sicard G., Improving DPA resistance of Quasi Delay Insensitive Circuits using randomly time-shifted Acknowledgement Signals , ISRN: ISRN: TIMA-RR--06/02-01--FR, 2006
 
(1218) Blampey A., Interoperability between hardware emulators and hardware prototyping platforms , These de Doctorat, 2006
 
(1219) Rousseau F., Metzger M., Vachon J., Aboulhamid E.M., Bastien F., Introspection mechanisms for Semi-Formal Verification in a System-Level Design environment, Workshop on Rapid System Prototyping (IEEE RSP’06), Chania, Greece, June 14-16, 2006
 
(1220) Urard P., Zergainoh N.-E., Tambour L., Jerraya A. A., Macrocell builder: IP block-based design Environment for high-throughput VLSI dedicated digital signal processing systems, Journal on Applied Signal Processing, 2006, page: Article ID 28636, 1-11, 2006
 
(1221) Velazco R., Managing transient effects of radiation on complex microelectronic systems, Design of Circuits and Integrated Systems (DCIS’06), Barcelone, Spain, November, 2006
 
(1222) Benabdenbi M., Chotin-Avot R., Pétrot F., Carrier M., Labayrade R., Greiner A., Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip, Intelligent Vehicles Symposium, 2006 IEEE, 13-15 June, 2006
 
(1223) Perez R., Nicolaidis M., Alexandrescu D., Leroy D., Pignol M., Bertrand J., Belhaddad H., Measurement of Single Event Transient Pulse Width Induced by Ionizing Radiations in CMOS Combinational Logic, Radiation Effects on Components and Systems: RADECS 2006 Workshop, September 27-29, 2006
 
(1224) Pieralisi L., Modeling flexible Networks On-Chip, These de Doctorat, 2006
 
(1225) Basrour S., Terrasson G., Briand R., Modélisation sous MATLAB-Simulink d'un émetteur-récepteur pour microcapteurs, 9ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, France, May 10-12, 2006
 
(1226) Ammar Y., Basrour S., Marzencki M., Matou K., Zenati A., Multi-domain and mixed-signal simulation of System-on-Chip embedding MEMS, Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2006. EuroSime 2006. 7th International Conference on, 2006
 
(1227) Grasset A., Network interface synthesis for system-on-chip: from specification to automatic generation, These de Doctorat, 2006
 
(1228) Ammar Y., Basrour S., Non-linear techniques for increasing harvesting energy from piezoelectric and electromagnetic micro-power-generators, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP’06), Stresa, Italy, 26-28 April , 2006
 
(1229) Ammar Y., Basrour S., Non-linear techniques for increasing harvesting energy from piezoelectric and electromagnetic micro-power-generators, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP’06), Stresa, Italy, 26-28 April, 2006
 
(1230) Aeschlimann F., Non uniformly sampled signal processing : algorithm and architecture, These de Doctorat, 2006
 
(1231) Pétrot F., Gomez P., Greiner A., On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures, 10th Euromicro conference on Digital System Design (DSD’06), Dubrovnik, Croatia, August, 2006
 
(1232) Dhayni A., Bounceur A., Mir S., Rufer L., On-chip Pseudorandom Testing for Linear and Nonlinear MEMS, ISRN: TIMA-RR--06/10-04--FR, 2006
 
(1233) Borrione D., Morin-Allory K., On-line monitoring of properties built on regular expressions, Proc. Forum on Specification and Design Languages (FDL'06), Darmstadt, Germany, September 19-22, 2006
 
(1234) Oddos Y., Morin-Allory K., Borrione D., On-line test vector generation from temporal constraints written in PSL, Proc. 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October 16-18, 2006
 
(1235) Borrione D., Oddos Y., Morin-Allory K., On-line test vector generation from temporal regular expressions, Intensive Workshop on Service Oriented Computing (IWSOC'06), Le Caire, Egypte, December 16-17, 2006
 
(1236) Simeu E., Mir S., Rolindez L., Bounceur A., On the accurate estimation of test metrics for multiple analogue parametric deviations, 12th International Mixed-Signals Testing Workshop (IMSTW’06), Edinburgh, UK, June 21-23, 2006
 
(1237) Renaudin M., Rios D., Sicard G., Buhrig A., On the use of feedback control to dynamically control the supply voltage of low-power circuits, Journal of Low Power Electronics (JOLPE), 2, page: 45–55, 2006
 
(1238) Leveugle R., Maingot V., On the use of information redundancy when designing secure chips, 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’06), Prague, Czech Republic, April 18-21, 2006
 
(1239) Sicard G., Renaudin M., Bouesse G.F., Path swapping method to improve DPA resistance of QDI asynchronous circuits, 8th International Workshop on Cryptographic Hardware and Embedded Systems (CHES’06),Yokohama, Japan, October , 2006
 
(1240) Bacivarov I., Performance evaluation for heterogeneous MPSoC design, These de Doctorat, 2006
 
(1241) Bacivarov I., Jerraya A. A., Performance evaluation methods for MPSoC Design, EDA for IC System Design, Verification, and Testing, CRC Press, Chapter 6, 2006
 
(1242) Reis R., Lazzari C., Anghel L., Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study , 12th IEEE International On-Line Testing Symposium (IOLT’06), Como, Italy, July 10-12, 2006
 
(1243) Leveugle R., M'Buwa Nzenguet F., Renaudin M., Moitrel P., Monnet Y., Feyt N., Practical evaluation of fault countermeasures on an asynchronous DES cryptoprocessor, 12th IEEE International On-Line Testing Symposium (IOLT’06), Como, Italy, July 10-12, 2006
 
(1244) Buard N., Hubert G., Bougerol A. , Gaillard R., Wrobel F. , Miller F., Carriere T., Anghel L., Prediction of transients induced by neutrons/protons in CMOS combinational logic cells, On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International, 2006
 
(1245) Reis R., Simeu E., De Micheli G., Mir S., Proceedings on 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), IFIP, 416 p., 2006
 
(1246) Boutobza S., Nicolaidis M., Programmable test for memories, 7093176, 2006
 
(1247) Pétrot F., Jerraya A. A., Bouchhima A., Programming models and HW-SW Interfaces Abstraction for Multi-Processor SoC, Design Automation Conference, 2006 43rd ACM/IEEE, 24-28 July, 2006
 
(1248) Jerraya A. A., Bouchhima A., Pétrot F., Programming models and HW-SW Interfaces Abstraction for Multi-Processor SoC, ISRN: TIMA-RR--06/06-02--FR, 2006
 
(1249) Borrione D., Morin-Allory K., Proven correct monitors from PSL specifications, Proceedings of the conference on Design, automation and test in Europe. Munich, DE, 2006
 
(1250) Dhayni A., Pseudorandom Built-In Self-Test for microsystems, These de Doctorat, 2006
 
(1251) Mir S., Bounceur A., Rufer L., Dhayni A., Pseudorandom Functional BIST for Linear and Nonlinear MEMS, Design, Automation and Test in Europe, 2006. DATE '06. Proceedings, 2006
 
(1252) Mir S., Dhayni A., Rufer L., Pseudorandom functional BIST for MEMS, 12th International Mixed-Signals Testing Workshop (IMSTW’06), Edinburgh, UK, June 21-23, 2006
 
(1253) Borrione D., Ostier P., Fesquet L., Liu M., PSL-based online monitoring of digital systems, in Advances in Design and Specification Languages for SoCs, Springer , 5-22, 2006
 
(1254) Yahya E., Renaudin M., QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’06), Montpellier, France, September 13-15, 2006
 
(1255) Yahya E., Renaudin M., QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer , 583-592 , 2006
 
(1256) Yahya E., Renaudin M., QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis, ISRN: TIMA-RR--06/06-03--FR, 2006
 
(1257) Amblard P., Recognition and evaluation of Jevons' language by composing 2-state automata, ETAPS Workshop : Synchronous Language Applications Programming (SLAP'06), March 25. Vienna, AT, 2006
 
(1258) Leveugle R., Maingot V., Redondance d’information : une sécurité suffisante ?, 9ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, France, May 10-12, 2006
 
(1259) Roche P., Leveugle R., Vanhauwaert P., Reduced instrumentation and optimized fault injection control for dependability analysis, Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC’06), Nice, France, October 16-18, 2006
 
(1260) Chan Y.C., Rufer L., Alam M.O., Wu B.Y., Reliability of BGA Solder Joints on the Au/Ni/Cu Bond Pad – Effect of Thicknesses of Au and Ni layer, IEEE Transactions on Device and Materials Reliability, Vol.6, page: 421-428, 2006
 
(1261) Renaudin M., Robert M., Maurine P., Razafindraibe A., Security evaluation of dual rail logic against DPA attacks, Proc. 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October 16-18, 2006
 
(1262) Metzger M., Vachon J., Rousseau F., Aboulhamid E.M., Bastien F., Semi-formal verification tool implementation using introspection mechanisms in a System-Level Design environment, Forum on specification & Design Language (FDL’06), Darmstad, Germany, September 19-22, 2006
 
(1263) Rousseau F., Aboulhamid E.M., Lapalme J., Nicolescu G., Separating Modeling and Simulation Aspects in Hardware/Software System Design, International Conference on Microlectronics, Dhahran, Saudi Arabia, December16-19 , 2006
 
(1264) Jerraya A. A., Fouillard A.-M., Pétrot F., Youssef W., Bouchhima A., Kriaa L., Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling, Seventeenth IEEE International Workshop on Rapid System Prototyping, 2006
 
(1265) Anghel L., SET and SEU effects at multiple abstraction levels, Single Event Effects Symposium (SEE'06), Long Beach, CA, USA, March , 2006
 
(1266) Grobelny D., Rufer L., Simulation of SAW-based chemical sensor, WOFEX 2006, Ostrava, Czech Republic, September 21-22, 2006
 
(1267) Wu B.Y., Dan Y., Chan Y.C., Rufer L., Alam M.O., Solid State growth kinetics of complex intermetallics in the Pb-free Ball Grid Array (BGA) solder joint for MEMS Packaging, Electronics Packaging Technology Conference, 2006. EPTC '06. 8th, 2006
 
(1268) Fesquet L., Qaisar S.-M., Renaudin M., Spectral analysis of a signal driven sampling scheme, 14th European Signal Processing Conference (EUSIPCO’06), Florence, Italy, September 4-8, 2006
 
(1269) Lopin G., Renaudin M., Yahya E., Standard-Logic Quasi Delay Insensitive Latches, ISRN: TIMA-RR--06/06-04--FR, 2006
 
(1270) Renaudin M., Fesquet L., Steiner M., Folco B., State-holding in Look-Up Tables: application to asynchronous logic, 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October 16-18, 2006
 
(1271) Sicard G., Lizarraga L., Bounceur A., Mir S., Study of a BIST technique for CMOS active pixel sensors, 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October, 2006
 
(1272) Prario I., Alurralde M., Velazco R., Ferreyra P., Vertanessian A., Sager G.E., Filevich A., Palumbo F., TANDAR as a digital circuits test radiation facility, Proceedings of Latin American Test Workshop (LATW’06),Buenos Aires, Argentina, March 26-29, 2006
 
(1273) Farkas G., Courtois B., Poppe A., Szekely V., Rencz M., Szabo P., Thermal characterization and compact modeling of stacked die packages, International Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm’06), San Diego, California, USA, May 30 – June 2, 2006
 
(1274) Borrione D., Schmaltz J., Towards a formal theory of communication architecture in the ACL2 logic, Proceedings of the 6th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'06), Seattle, WA, USA, August 15-16, 2006
 
(1275) Schmaltz J., Borrione D., Towards a Formal Theory of On Chip Communications, ISRN: TIMA-RR--06/09-01--FR, 2006
 
(1276) Kolonis E., Nicolaidis M., Towards a Holistic CAD Platform for Nanotechnologies, Keynote at European Nano Systems Confernce (ENS'06), Paris, France, 2006
 
(1277) Aboulhamid E.M., Dubois Ma., Rousseau F., Towards an Efficient Simulation of Multi-Language Descriptions of Heterogeneous Systems, Asia Pacific Conference on Circuits and Systems (APCCAS’06), Singapour, December , 2006
 
(1278) Rousseau F., Aboulhamid E.M., Tsikhanovich A., Bois G., Transaction Level Modeling in hardware/software system design using net framework, Canadian Conference on Electrical and Computer Engineering (IEEE CCECE 2006), Ottawa, Canada, May 7-10 , 2006
 
(1279) Nguyen H.N., Simeu E., Mir S., Rufer L., Use of regressive method for RF MEMS test and diagnosis, Int. Conf. on Very Large Scale Integration, PhD Forum(VLSI-Soc'06), Nice, France, Oct. 16-18, 2006
 
(1280) Torrellas S., Savaria B.Y., Nicolescu B., Valderas M.G., Velazco R., Validation by fault injection of a software error detection technique dealing with critical Single Event Upsets, Proceedings of Latin American Test Workshop (LATW’06),Buenos Aires, Argentina, March 26-29, 2006
 
(1281) Renaudin M., Sirianni A., Borrione D., Boubekeur M., Mounier L., Validation of Asynchronous Circuit Specifications Using IF/CADP, VLSI-SOC: From Systems to Chips, Springer , 85-100, 2006
 
(1282) Lizarraga L., Mir S., Sicard G., Vers une technique d’auto test incorporé (BIST) pour des pixels actifs CMOS, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, France, May 10-12, 2006
 
(1283) Pierre L., VHDL, Software Specification Methods - An overview using a case study, International Scientific and Technical Encyclopedia (ISTE), chapter 10 - pp.179-196, 2006
 
(1284) Szekely V., Courtois B., Lasance C., Rencz M., 10thInternational Workshop on THERmal Investigations of ICs and Systems (THERMINIC’05), Belgirate, Lake Maggiore, Italy, September 27– 30, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, , 2005
 
(1285) Courtois B., 5B:Emerging technologies - reliable and fault-tolerant wireless sensor networks, 23rd-IEEE-VLSI-Test-Symposium., 2005
 
(1286) Allier E., Renaudin M., Sicard G., André E., Dezzani A., Goulier J., A 120nm low power asynchronous ADC, Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on, 2005
 
(1287) Allier E., Renaudin M., Dezzani A., Goulier J., André E., Sicard G., A 120nm Low Power Asynchronous ADC, ISRN: TIMA-RR--06/02-08--FR, 2005
 
(1288) Delobelle P., Rémiens D., Hirsinger L., Dogheche K., Charlot B., Cattan E., Marzencki M., Cavallier B., Ballandras S., Basrour S., A Bi-stable Micro-machined Piezoelectric Transducer for Mechanical to Electrical Energy Transformation, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'05), June 1-3, 2005
 
(1289) Mir S., Tsiatouhas Y., Matakias S., Prenat G., Arapoyanni A., Haniotakis Th., A built-in IDDQ testing circuit, Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European. Grenoble, FR, 2005
 
(1290) Renaudin M., Germain F., Bouesse G.F., Witon A., A clock-less low-voltage AES crypto-processor, Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European. Grenoble, FR, 2005
 
(1291) Mir S., Carbonero J.L., Bounceur A., Rolindez L., A digital bist for a 16-bit audio sigma-delta analogue-to-digital converter, 11th Annual International Mixed-Signals Testing Workshop (IMSTW'05), June 27-29. Cannes – Côte d'Azur, FR, 2005
 
(1292) Borrione D., Schmaltz J., A Generic Network on Chip Model, Lecture Notes in Computer Science, , page: 310-325, 2005
 
(1293) Borrione D., Schmaltz J., A Generic Network on Chip Model, Theorem Proving in Higher Order Logics: 18th International Conference, TPHOLs 2005, Proceedings. Lecture Notes in Computer Science, Volume 3603., 2005
 
(1294) Schmaltz J., Borrione D., A Generic Network on Chip Model, ISRN: TIMA-RR--05/03-06--FR, 2005
 
(1295) Mir S., Prenat G., Vazquez D., Rolindez L., A low-cost digital frequency testing approach for mixed-signal devices using Sigma Delta modulation, Microelectronics journal, Vol.36, December, page: 1080-1090, 2005
 
(1296) Charlot B., Basrour S., Colin M., Spirkovich S., Marzencki M., A MEMS piezoelectric vibration energy harvesting device, Fifth Int. Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS'05), , November 28-30. Tokyo, JP, 2005
 
(1297) Maurine P., Razafindraibe A., Renaudin M., Robert M., A Method to Design Compact Dual-rail Asynchronous Primitives, Integrated Circuit and System Design 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 20-23, 2005. Proceedings, 2005
 
(1298) Leveugle R., Renaudin M., Dumont S., Monnet Y., Bouesse G.F., An Asynchronous DES Crypto-Processor Secured against Fault Attacks, ISRN: TIMA-RR--06/02-04--FR, 2005
 
(1299) Renaudin M., Monnet Y., Bouesse G.F., Dumont S., Leveugle R., An Asynchronous DES Crypto-Processor Secured against Fault Attacks, 15th IFIP Int. Conf. on Very Large Scale Integration Systems, VLSI-SoC'05, October 17-19. Perth, AU, 2005
 
(1300) Renaudin M., Clouard A., Vivet P., Beigné E., Clermidy F., An asynchronous NOC architecture providing low latency service and its multi-level design framework, Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on, 2005
 
(1301) Papachristou C., Wolff F., Gill B., Nicolaidis M., Garverick S., An efficient BICS design for SEUs detection and correction in semiconductor memories, Proceedings.-Design,-Automation-and-Test-in-Europe, 2005
 
(1302) Leveugle R., A new approach for early dependability evaluation based on formal property checking and controlled mutations, 11th-IEEE-International-On-Line-Testing-Symposium., 2005
 
(1303) Beigné E., Caucheteux D., Crochon E., Renaudin M., A New Class of Asynchronous Inductive Contactless Devices Using Event Based Communications And Self-Timed Logic, International Conference on Very Large Scale Integration (VLSI-SoC'05),17-19 October. Perth, AU, 2005
 
(1304) Renaudin M., Fesquet L., A programmable logic architecture for prototyping clockless circuits, 15th Int. Conf. on Field Programmable Logic & Applications (FPL'05), Tampere, Finland, August 24-26, 2005
 
(1305) Fesquet L., Renaudin M., A PROGRAMMABLE LOGIC ARCHITECTURE FOR PROTOTYPING CLOCKLESS CIRCUITS , ISRN: TIMA-RR--06/02-16--FR, 2005
 
(1306) Morin-Allory K., Borrione D., A proof of correctness for the construction of property monitors, High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International. Nappa Valley, US, 2005
 
(1307) Gobert J., Pétrot F., Abril A., Miro C., Mehrez H., Architectural Energy Estimation of Embedded Systems using Cycle Accurate Simulation, Microtechnologies for the New Millennium 2005 : VLSI Circuits and Systems, Sevilla, Spain, May , 2005
 
(1308) Caucheteux D., Architecture study and design of mixed circuits using asynchronous logic: Application to very low power consumption and contactless systems, These de Doctorat, 2005
 
(1309) Pétrot F., A Service Based Component Model for Multi-Level HW/SW Specifications , 5th International Seminar on Application Specific Multiprocessor SoC, Margaux, France, July , 2005
 
(1310) Rios D., Buhrig A., Renaudin M., Asservissement de vitesse pour minimiser la puissance consommée par un processeur , ISRN: TIMA-RR--06/02-06--FR, 2005
 
(1311) Despesse G., A Study of the physical phenomena for supply wireless sensors nodes, These de Doctorat, 2005
 
(1312) Renaudin M., Buhrig A., Barthel D., Asynchronous Architecture for Sensor Network Nodes, MedHocNet, Porquerolles, France, June 20-22, 2005
 
(1313) Monnet Y., Renaudin M., Leveugle R., Asynchronous Circuits Sensitivity To Transient Faults, ISRN: TIMA-RR--05/04-02--FR, 2005
 
(1314) Monnet Y., Renaudin M., Leveugle R., Asynchronous circuits transient faults sensitivity evaluation, Proceedings 2005. 42nd Design Automation Conference , 2005
 
(1315) Leveugle R., Renaudin M., Monnet Y., Asynchronous circuits transient faults sensitivity evaluation, Annual ACM IEEE Design Automation Conference, Proceedings of the 42nd annual conference on Design automation. San Diego, California,, US, 2005
 
(1316) Renaudin M., Monnet Y., Leveugle R., Asynchronous Circuits Transient Faults Sensitivity Evaluation, ISRN: TIMA-RR--06/02-02--FR, 2005
 
(1317) Razafindraibe A., Renaudin M., Robert M., Maurine P., Asynchronous dual rail cells to secure cryptosystem against Side Channel Attacks, Sophia Antipolis MicroElectronic (SAME 2005 Forum), Sophia Antipolis, France, October 5-6, 2005
 
(1318) Renaudin M., Sicard G., Allier E., Fesquet L., Asynchronous level crossing analog to digital converters, Measurement, Volume 37 , page: 296-309, 2005
 
(1319) Zitouni A., Badrouchi S., Torki K., Tourki R., Asynchronous NoC Router Design, Journal of Computer Science, 1(3), page: 429-436, 2005
 
(1320) Renaudin M., Quartana J., Fesquet L., Asynchronous Systems on Programmable Logic, Reconfigurable Communication-centric SoCs (ReCoSoC'05), Montpellier, France, June 27-29, 2005
 
(1321) Renaudin M., Quartana J., Fesquet L., Asynchronous Systems on Programmable Logic, ISRN: TIMA-RR--06/02-12--FR, 2005
 
(1322) Bouchhima A., Jerraya A. A., Cesario W., Chen X., Pétrot F., A Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design, 5th ACM international conference on Embedded software (EMSOFT 2005), September 18-22. Jersey City NJ, US, 2005
 
(1323) Grasset A., Jerraya A. A., Rousseau F., Automatic generation of component wrappers by composition of hardware library elements starting from communication service specification, Proceedings. The 16th International Workshop on Rapid System Prototyping (RSP 2005), 2005
 
(1324) Rousseau F., Jerraya A. A., Grasset A., Automatic Generation of Component Wrappers from Communication Service Specification, ISRN: TIMA-RR--05/03-07--FR, 2005
 
(1325) Sarmento A., Automatic Generation of Simulation Models for the validation of heterogeneous systems-on-chip, These de Doctorat, 2005
 
(1326) Rufer L., Mir S., Dhayni A., Bounceur A., Autotest Intégré des Microsystèmes Nonlinéaires, 8ème Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM’05), Paris, France, May 10-12, 2005
 
(1327) Dzahini D., Torki K., Richer J.-P., Le Caer T., Herve C., BiCMOS amplifier–discriminator integrated circuit for gas-filled detector readout, Nuclear Instruments and Methods in Physics Research A, 540, page: 437-447, 2005
 
(1328) Mir S., Dhayni A., Rufer L., Built-In Self-Test techniques for MEMS, 1st International Workshop on Advances in Sensors and Interfaces (IWASI'05), Invited Talk, Bari, Italy, April 19-20, 2005
 
(1329) Sicard P., Renaudin M., Labonne E., Capteur de vision CMOS à grande dynamique et adapté aux conditions , ISRN: TIMA-RR--06/02-09--FR, 2005
 
(1330) Bouchhima A., Jerraya A. A., Yoo S., Bacivarov I., ChronoSym – a New Approach for Fast and Accurate SoC Cosimulation, IJES - International Journal of Embedded Systems , Volume: 1 -/2, page: 103-111, 2005
 
(1331) Renaudin M., Circuits Asynchrones et Consommation, 5ème Journées d'études Faible Tension, Faible Consommation (FTFC’05), Paris, France, May 18-19, 2005
 
(1332) Renaudin M., Circuits et systèmes asynchrones: une approche architecturale, École thématique «Architectures des systèmes matériels enfouis et méthodes de conception associées (ARCHI’05)», Autrans (Vercors), France, March 21-25, 2005
 
(1333) Torki K., Courtois B., CMP service for prototyping and low volume production, CEPA 2 Workshop – Digital Platforms for Defence, Brussels, Belgique, March 15-16, 2005
 
(1334) Hadjiat K., Leveugle R., Ammari A., Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation, Journal of Electronic Testing: Theory and Applications, Volume 21, Number 4, page: 365 - 376, 2005
 
(1335) Borrione D., Toma D., Al Sammane G., Combining several paradigms for circuit validation and verification, Construction and Analysis of Safe, Secure, and Interoperable Smart Devices. International Workshop, CASSIS 2004.Revised Selected Papers., Springer , 229-49, 2005
 
(1336) Toma D., Zimmermann Y., Component Reuse in B Using ACL2, 4th International Conference of B and Z Users (ZB’05), Guildford, UK, April 13-15, 2005
 
(1337) Rousseau F., Conception des Systèmes VLSI, Techniques de l'Ingénieur, E 2 455, ouvrage de base, page: , 2005
 
(1338) Simeu E., Mir S., Rufer L., Concurrent testing embedded systems: adapting automatic control techniques to microelectronics testing , 16th IFAC World Congress, Prague, Czech Republic, July 4-8, 2005
 
(1339) Bouesse G.F., Contribution to Secure Design of Integrated Circuits: the Asynchronous Alternative, These de Doctorat, 2005
 
(1340) Renaudin M., Rios D., Buhrig A., Controlling processors ’speed using dynamic voltage scaling, 5ème Journées d'études Faible Tension, Faible Consommation (FTFC’05), Paris, France, May 18-19, 2005
 
(1341) Borrione D., Paul W., Correct Hardware Design and Verification Methods, Springer , 412 p., 2005
 
(1342) Fragoso J., Data Paths Automatic Generation in QDI Asynchronous Logic, These de Doctorat, 2005
 
(1343) Jerraya A. A., Zergainoh N.-E., Tambour L., Michel H., Delay Correction in RTL Models of DSP SoC obtained by IP-based design approach, Technique et Science Informatiques (TSI), 24/10, page: 1227-1257, 2005
 
(1344) Basrour S., Despesse G., Chaillout J.J., Leger J.M., Jager T., Design and fabrication of a new system for vibration energy harvesting, Research in Microelectronics and Electronics, 2005 PhD. Lausanne, CH, 2005
 
(1345) Basrour S., Marzencki M., Valbin L., Grasso A., Colin M., Charlot B., Design and fabrication of piezoelectric micro power generators for autonomous microsystems, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'05), June 1-3, 2005
 
(1346) Schmaltz J., Borrione D., Al Sammane G., Design and Formal Verification of Networks On Chip, ISRN: TIMA-RR--05/12-01--FR, 2005
 
(1347) Ma W., Rufer L., Zohar Y., Wong M., Design and implementation of an integrated floating-gate electrostatic power micro-generator, TRANSDUCERS '05. The 13th International Conference on Solid State Sensors, Actuators and Microsystems. Digest of Technical Papers IEEE Cat. No. 05TH8791, 2005
 
(1348) Mir S., Design and Integrated Test of Analogue, Mixed-Signal and Microsystems Devices, HDR, 2005
 
(1349) Nicolaidis M., Design for mitigation of single event effects, 11th-IEEE-International-On-Line-Testing-Symposium., 2005
 
(1350) Nicolaidis M., Design for mitigation of Single Event Effects, IEEE International On-Line Testing Symposium (IOLTS 2005), ST Raphael, France, July 6-8, 2005
 
(1351) Nicolaidis M., Design for soft error mitigation, IEEE Transactions on Device and Materials Reliability, Vol.5, page: 405- 418, 2005
 
(1352) Monnet Y., Bouesse G.F., Renaudin M., Designing resistant asynchronous circuits against malicious fault injection, 3rd International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi’05), Saint-Etienne, France, June 8-11, 2005
 
(1353) Charlot B., Marzencki M., Basrour S., Design, Modelling and Optimisation of Integrated Piezoelectric Micro Power Generators, Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3, 2005
 
(1354) Prenat G., Design of a programmable analog and mixed-signal BIST architecture in deep submicron technology, These de Doctorat, 2005
 
(1355) Domingues C., Design of micromachined acoustic transducers, These de Doctorat, 2005
 
(1356) Nicolaidis M., Device for reconfiguring a faulty storage assembly, 6,946,985, 2005
 
(1357) Mir S., Simeu E., Diagnosis in Linear and Nonlinear Mixed-Signal Systems: a Parameter Identification Based Technique, ISRN: TIMA-RR--05/06-01--FR, 2005
 
(1358) Prenat G., Rolindez L., Mir S., Digital test of a ΣΔ modulator in a mixed-signal BIST architecture, SPIE Microtechnologies for the New Millennium, VLSI circuits and systems II. Sevilla, ES, 2005
 
(1359) Dumont S., Germain F., Renaudin M., Bouesse G.F., DPA on quasi delay insensitive asynchronous circuits: formalization and improvement, Design, Automation and Test in Europe, 2005. Proceedings, 2005
 
(1360) Rufer L., Wong M., Ma W., Dynamic simulation of an implemented electrostatic power micro-generator, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS,June 1-3. Montreux, CH, 2005
 
(1361) Rufer L., Ma W., Wong M., Dynamic simulation of an implemented electrostatic power micro-generator, ISRN: TIMA-RR--05/02-03--FR, 2005
 
(1362) Hadjiat K., Leveugle R., Early dependability evaluation: injection of multiple bit-flips, Proceedings of the 6th IEEE Latin-American Test Workshop (LATW'05), Salvador, Brazil, March 30 - April 2, 2005
 
(1363) Hadjiat K., Early prediction of dependability of complex digital circuits, These de Doctorat, 2005
 
(1364) Amblard P., Hristov M., Jerraya A. A., Petkov I., Effective Hardware Verification of ARM Based System on Chip Design, Proceedings of 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 05). Krakow, PL, 2005
 
(1365) Alam M.O., Rufer L., Chan Y.C., Effect of Au and Ni layer thicknesses on the reliability of BGA solder joints, International Symposium on Electronics Materials and Packaging, (EMAP'05), Tokyo, Japan, December 11-14, 2005
 
(1366) Abril A., Pétrot F., Mehrez H., Gobert J., Miro C., Energy Estimation and Optimisation of Embedded Systems using Cycle Accurate Simulation, Symposium on low power and high-speed chips, Yokohama, Japan, April 20 - 22, 2005
 
(1367) Miro C., Gobert J., Pétrot F., Mehrez H., Abril A., Energy estimation and optimization in architectural descriptions of complex embedded systems, Proceedings of Microtechnologies for the New Millennium 2005 : VLSI Circuits and Systems. Sevilla, ES, 2005
 
(1368) Fesquet L., Allier E., Aeschlimann F., Renaudin M., Etude Spectrale de l'’Échantillonnage par Traversée de Niveaux, ISRN: TIMA-RR--06/02-11--FR, 2005
 
(1369) Mir S., Rufer L., Dhayni A., Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities, Proceedings. European Test Symposium. ETS 2005, 2005
 
(1370) Vanhauwaert P., Leveugle R., Anghel L., Evaluation of SET and SEU effects at multiple abstraction levels, 11th-IEEE-International-On-Line-Testing-Symposium., 2005
 
(1371) Leger J.M., Vassilev A., Jager T., Despesse G., Basrour S., Charlot B., Chaillout J.J., Fabrication and characterization of high damping electrostatic micro devices for vibration energy scavenging, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2005), June 1-3, 2005
 
(1372) Fragoso J., Renaudin M., Sicard G., Fast Performance Comparison of Asynchronous Circuits , 5ème journées d'études Faible Tension, Faible Consommation (FTFC’05), Paris, France, May 18-19, 2005
 
(1373) Germain F., Bouesse G.F., Renaudin M., Dumont S., Formalizing and Improving DPA resistance, ISRN: TIMA-RR--06/02-18--FR, 2005
 
(1374) Toma D., Borrione D., Formal Verification of a SHA-1 Circuit Core Using ACL2, Theorem Proving in Higher Order Logics: 18th International Conference, TPHOLs 2005. , Springer , 326, 2005
 
(1375) Dubreuil H., Fesquet L., Huot N., Renaudin M., FPGA architecture for multi-style asynchronous logic, ISRN: TIMA-RR--06/02-10--FR, 2005
 
(1376) Renaudin M., Dubreuil H., Huot N., Fesquet L., FPGA architecture for multi-style asynchronous logic, Design Automation and Test in Europe Conference and Exhibition (DATE ’05), Munich,Germany, pp.32-33, March 7-11, 2005 , 2005
 
(1377) Huot N., Renaudin M., Fesquet L., Dubreuil H., FPGA architecture for multi-style asynchronous logic [full-adder example], Design, Automation and Test in Europe, 2005. Proceedings, 2005
 
(1378) Gascard E., From sequential extended regular expressions to deterministic finite automata, ISRN: TIMA-RR--05/07-01--FR, 2005
 
(1379) Gascard E., From Sequential Extended Regular Expressions to Determinstic Finite Automata, Information and Communications Technology, 2005. Enabling Technologies for the New Knowledge Society: ITI 3rd International Conference on. Cairo, EG, 2005
 
(1380) Quartana J., Renane S., Fesquet L., Baixas A., Renaudin M., GALS Systems Prototyping using Multiclock FPGAs , ISRN: TIMA-RR--06/02-15--FR, 2005
 
(1381) Quartana J., Renane S., Baixas A., Fesquet L., Renaudin M., GALS systems prototyping using multiclock fpgas and asynchronous network-on-chips, Field Programmable Logic and Applications, 2005. International Conference on, 2005
 
(1382) Rufer L., Dhayni A., Bounceur A., Mir S., Génération de vecteurs de test pour les MEMS non linéaires pour le calcul des noyaux de Volterra, 8ème Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM’05), Paris, France, May, 2005
 
(1383) Ammar Y., Cusinu P., Zenati A., Matou K., Basrour S., Global simulation and co-simulation of Self Powered Micro Systems, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'05), June 1-3, 2005
 
(1384) Courtois B., Guest Editorial, Analog Integrated Circuits and Signal Processing, August, Volume 44, Number 2, page: 107, 2005
 
(1385) Jerraya A. A., Wolf W., Tenhunen H., Guest Editors' Introduction: Multiprocessor Systems-on-Chips, Computer Review, Volume: 38, page: 36 - 40, 2005
 
(1386) Leveugle R., Monnet Y., Renaudin M., Hardening techniques against transient faults for asynchronous circuits, 11th-IEEE-International-On-Line-Testing-Symposium. 2005:, 2005
 
(1387) Monnet Y., Leveugle R., Renaudin M., Hardening Techniques against Transient Faults for Asynchronous Circuits , ISRN: TIMA-RR--06/02-05--FR, 2005
 
(1388) Baghdadi A., Jerraya A. A., Zergainoh N.-E., Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip, IJES - International Journal of Embedded Systems , 1/2, page: 112-124, 2005
 
(1389) Yoo S., Jerraya A. A., Hardware/Software cosimulation from interface perspective, IEE Proceedings Computers & Digital Techniques, Vol. 152, page: 369-379, 2005
 
(1390) Jerraya A. A., Wolf W., Hardware/software interface codesign for embedded systems, Computer Review, Volume: 38, page: 63- 69, 2005
 
(1391) Rousseau F., Gharsalli F., Jerraya A. A., Hardware/software interface design for global memory integration in System-On-Chip, Technique et Science Informatiques (TSI), Vol. 24/4, page: 369-394, 2005
 
(1392) Rousseau F., Hardware/Software system design : from Hardware/Software partitioning to prototyping onto reconfigurable platforms, HDR, 2005
 
(1393) Despesse G., Basrour S., Charlot B., Chaillout J.J., Vassilev A., Dekkaki I., Jager T., Leger J.M., High Damping Electrostatic System For Vibration Energy Scavenging, Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Anaheim, California, USA, May 8-12, 2005
 
(1394) Faure F., Velazco R., Ecoffet R., How to characterize the problem of SEU in processors & representative errors observed on flight, 11th-IEEE-International-On-Line-Testing-Symposium, 2005
 
(1395) Pétrot F., HW/SW Interfaces Abstraction and Design for SoC, MEDEA+ Desgin Automation Conference, Les Mesnuls, France, May , 2005
 
(1396) Cristoloveanu S., Fesquet L., Brillouet M., Kaiser A., IEEE European Solid-State Circuits Conference (ESSCIRC), IEEE Computer Society, , 2005
 
(1397) Bouesse G.F., Renaudin M., Improving DPA resistance of Quasi-delay Insensitive Asynchronous Circuits, 3rd International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi’05), Saint-Etienne, France, June 8-11, 2005
 
(1398) Renaudin M., Sicard G., Bouesse G.F., Improving DPA resistance of Quasi Delay Insensitive Circuits using randomly time-shifted Acknowledgement Signals, 15th IFIP Int. Conf. on Very Large Scale Integration Systems, VLSI-SoC'05, October 17-19. Perth, AU, 2005
 
(1399) Bounceur A., Initiation à la Programmation Objet avec Java : Partie 1, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, , 2005
 
(1400) Leveugle R., Hadjiat K., Ammari A., Injection of multiple bit-flips for counter measures validation, 2nd International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'05), Edinburg, UK, September 2, 2005
 
(1401) Kaminska B., Sunter S., Mir S., International Mixed-Signals Testing Workshop - IMSTW 2004: Special Issue of Microelectronics Journal, Elsevier, Vol. 36, N°12, December, 1063-1124, 2005
 
(1402) Yoo S., Jerraya A. A., Introduction to hardware abstraction layers for SoC, Computer, February 2005 (Vol. 38), page: 63-69, 2005
 
(1403) Leveugle R., Introduction to the special session on secure implementations, 11th-IEEE-International-On-Line-Testing-Symposium, 2005
 
(1404) Jerraya A. A., Popovici K., Zergainoh N.-E., Urard P., IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems, Proceedings of the ASP DAC 2005. Asia and South Pacific Design Automation Conference 2005 IEEE, 2005
 
(1405) Popovici K., Urard P., Jerraya A. A., Zergainoh N.-E., IP-Block-based design environment for high-throughput VLSI dedicated digital signal processing systems, Asia South Pacific Design Automation Conference (ASP-DAC 2005), Shangai, China, January 18-21, 2005
 
(1406) Jerraya A. A., Long term trends for embedded system design, CEPA 2 Workshop – Digital Platforms for Defence, Brussels, Belgique, March 15-16, 2005
 
(1407) Jerraya A. A., Long Term Trends for Embedded System Design, Proceedings of 12th Mixed Design of Integrated Circuits and Systems (MIXDES 2005) Conference. Krakow, PL, 2005
 
(1408) Anghel L., Nicolaidis M., Achouri N., Memory Defect Tolerance Architectures for Nanotechnologies, Journal of Electronic Testing: Theory and Applications, Vol. 21, page: 445 - 455, 2005
 
(1409) Allier E., Fesquet L., Renaudin M., Sicard G., Method and device for analog-digital conversion, comprises a comparator delivering a pair of control signals to an increment-decrement block for computing new digital value, FR2835365, 2005
 
(1410) Sunter S., Mir S., Kaminska B., Microelectronics Journal, Special Issue on IMSTW 2004 - International Mixed-Signals Testing Works, Volume 36, Issue 12, Elsevier, 1063-1124, 2005
 
(1411) Kriaa L., Modeling and validation of heterogeneous system : execution model definition, These de Doctorat, 2005
 
(1412) Zenati A., Basrour S., Courtois B., Modélisation et simulation au niveau système de Micro Système auto alimenté, SPMS, ISRN: TIMA-RR--05/01-01--FR, 2005
 
(1413) Fesquet L., Quartana J., Renaudin M., Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping, ISRN: TIMA-RR--06/02-14--FR, 2005
 
(1414) Fesquet L., Quartana J., Renaudin M., Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping, 15th IFIP Int. Conf. on Very Large Scale Integration Systems (VLSI-SoC'05), Perth, Australia, October 17-19, 2005
 
(1415) Saleh S., Multi levels soft errors simulation methods, These de Doctorat, 2005
 
(1416) Jerraya A. A., Wolf W., Tenhunen H., Multiprocessor Systems-on-Chips , Computer, DOI : 10.1109/MC.2005.231, Vol. 38, page: 36-40, 2005
 
(1417) Roman C., Ciontu F., Courtois B., Nanoscopic modeling of a carbon nanotube force-measuring biosensors, Molecular Simulations Journal, Vol.31, 15 February – 15 March, page: 123 -133 , 2005
 
(1418) Ciontu F., NANOSPRINT: an infrastructure for nanotechnology foresight, ISRN: TIMA-RR--05/03-05--FR, 2005
 
(1419) Ciontu F., NanoSPRINT: Intelligent Innovation Tools, Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show. Anaheim, California, US, 2005
 
(1420) Mir S., Bounceur A., Dhayni A., Rufer L., Nonlinearity effects on MEMS on-chip pseudorandum testing, 11th Annual International Mixed-Signals Testing Workshop (IMSTW’05),Cannes – Côte d’Azur, France, June 27-29, 2005
 
(1421) Simeu E., Off-Line and On-Line BIST for Embedded Systems, HDR, 2005
 
(1422) Rufer L., Domingues C., Simeu E., Mir S., On-chip pseudorandom MEMS testing, JETTA - Journal of Electronic Testing: Theory and Application, 21, page: 233-41, 2005
 
(1423) Dhayni A., Bounceur A., Mir S., Rufer L., On-chip pseudorandom testing for linear and nonlinear MEMS, Proc. IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’05), Perth, Western Australia, October , 2005
 
(1424) Anghel L., Reis R., Lazzari C., On implementing a soft error hardening technique by using an automatic layout generator: case study, 11th-IEEE-International-On-Line-Testing-Symposium., 2005
 
(1425) Ostier P., Morin-Allory K., Borrione D., Fesquet L., Liu Z.W., On-Line Assertion-Based Verification with Proven Correct Monitors, 3rd IEEE International Conference on Information and Communication Technology (ICICT'05), December 5-6, 2005. cairo, EG, 2005
 
(1426) Mir S., Simeu E., Rufer L., Online testing embedded systems: adapting automatic control techniques to microelectronics testing, 16th IFAC World Congress, Invited Talk, Prague, Czech Republic, July 2005 [DVD], 2005
 
(1427) Leveugle R., Breveglieri L., Rothbart K., Seifert J.-P., Nieuwland A., On-line testing for secure implementations: design and validation, 11th-IEEE-International-On-Line-Testing-Symposium., 2005
 
(1428) Leveugle R., Portolan M., On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors, IEEE International On-Line Testing Symposium (IOLT'05), Saint Raphael, France, July 6-8, 2005
 
(1429) Nicolescu B., Gorse N., Savaria B.Y., Aboulhamid E.M., Velazco R., On the Use of Model Checking for the Verification of a Dynamic Signature Monitoring Approach, IEEE Transactions on Nuclear Science, 52, page: 1555-1561, 2005
 
(1430) Guyot A., OPAR: combinatorial arithmetic operators, , , 2005
 
(1431) Guyot A., OPAR: Cours & exercises d'arithmétique en Java , , , 2005
 
(1432) Kheriji R., Danelon V., Carbonero J.L., Mir S., Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach, Design, Automation and Test in Europe (DATE'05), 2005
 
(1433) Renaudin M., Panel: Power Management Adaptive techniques: Where are we? Where are we going?, 5ème Journées d'études Faible Tension, Faible Consommation (FTFC’05), Paris, France, May 18-19, 2005
 
(1434) Simeu E., Mir S., Parameter identification based diagnosis in linear and non-linear mixed-signal systems , International Mixed-Signals Testing Workshop (IMSTW’'05) Cannes, Côte d’Azur, France, June 27-29, 2005
 
(1435) Lattard D., Durand Y., Jerraya A. A., Clermidy F., Lemaire R., Performance evaluation of a NoC-based design for MC-CDMA telecommunications using NS-2, Proceedings. The 16th International Workshop on Rapid System Prototyping (RSP 2005), 2005
 
(1436) Marzencki M., Rémiens D., Cattan E., Ballandras S., Dogheche K., Hirsinger L., Basrour S., Delobelle P., Cavallier B., Charlot B., Piezoelectric micro-machined ultrasonic transducer (pMUT) for energy harvesting, Ultrasonics Symposium, 18-21 Sept.Rotterdam, NL, 2005
 
(1437) Pétrot F., Donnet F., Gomez P., Augé I., Platform-based design from parallel C specifications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 24, page: 1811- 1826, 2005
 
(1438) Rios D., Buhrig A., Renaudin M., Power Consumption reduction using dynamic control of microprocessor performance, ISRN: TIMA-RR--06/02-17--FR, 2005
 
(1439) Rios D., Renaudin M., Buhrig A., Power Consumption reduction using dynamic control of Micro Processor performance, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, 2005
 
(1440) Anghel L., Nicolaidis M., Proceedings of 11th IEEE International On-Line Testing Symposium (IOLT 2005) Saint Raphael, French Riviera, France, July 6-8, 2005, IEEE Computer Society, 330 pages, 2005
 
(1441) Courtois B., Markus K., Proceedings of Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2005), Montreux,Switzerland, June 1-3, 2005, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 422 pages, 2005
 
(1442) Courtois B., Lasance C., Rencz M., Szekely V., Proceedings on 11th International Workshop on THERMAL INVESTIGATIONS of ICs and Systems (THERMINIC 2005), 27 - 30 September 2005, Belgirate, Lake Maggiore, Italy, TIMA EDITIONS, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 305 pages, 2005
 
(1443) Nicolaidis M., Costa A., Boutobza S., Lamara K.M., Programmable Memory BIST, Test Conference, 2005. Proceedings. ITC 2005. IEEE International , 2005
 
(1444) Cachera D., Morin-Allory K., Proving Parameterized Systems: the use of a widening operator and pseudo-pipelines in polyhedral logic, ISRN: TIMA-RR--05/04-01--FR, 2005
 
(1445) Morin-Allory K., Cachera D., Proving Parameterized Systems: the use of pseudo-pipelines in polyhedral logic, Lecture Notes in Computer Science, Volume 3725 , page: 376, 2005
 
(1446) Cachera D., Morin-Allory K., Proving Parameterized Systems: the use of pseudo-pipelines in polyhedral logic, in Correct Hardware Design and Verification Methods: 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, October 3-6, 2005, Proceedings. Saarbrücken, DE, 2005
 
(1447) Borrione D., Fesquet L., Ostier P., Liu M., PSL-based online monitoring of digital systems, Forum on specification and Design Languages (FDL'05), Lausanne, Switzerland, September 27-30, 2005
 
(1448) Pavageau S., Jerosolimski G., Charlot B., Tessier G., Dhilaire Stephan, Trannoy Nathalie, Gomes S., Vairac Pascal, Volz Sébastian, Cretin Bernard, Fournier D., Quantitative thermoreflectance imaging: calibration method and validation on a dedicated integrated circuit, Proceedings on 11th International Workshop on THERMAL INVESTIGATIONS OF ICs an Systems, 2005
 
(1449) Faure F., Radiation induced single event upset like fault injection, These de Doctorat, 2005
 
(1450) Nicolaidis M., Papachristou C., Gill B., Radiation induced single-word multiple-bit upsets correction in SRAM, 11th-IEEE-International-On-Line-Testing-Symposium., 2005
 
(1451) Mir S., Lalinsky T., Alam M.O., Torres A., Rufer L., Chan Y.C., SAW chemical sensors based on AlGaN/GaN piezoelectric material system: acoustic design and packaging considerations, Electronics Materials and Packaging, 2005. EMAP 2005. International Symposium on. Tokyo, CN, 2005
 
(1452) Yoo S., Choi K., Jerraya A. A., Cho Y., Zergainoh N.-E., Scheduler implementation in MPSoC Design, Asia South Pacific Design Automation Conference (ASP-DAC 2005), Shangai, China, January 18-21, 2005
 
(1453) Monnet Y., Fesquet L., Bouesse G.F., Renaudin M., Secure asynchronous circuits design and prototyping, at 3rd International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi’05), Saint-Etienne, France, June 8-11, 2005
 
(1454) Renaudin M., Monnet Y., Bouesse G.F., Secure asynchronous circuits for Smart-Card applications: Design and Methodologies, MEDEA+ DAC Conference, Les Mesnuls, France, May 24-26, 2005
 
(1455) Youssef W., Bouchhima A., Grasset A., Rousseau F., Cesario W., Jerraya A. A., Kriaa L., Sarmento A., Service Dependency Graph, an Efficient Model for Hardware/Software Interfaces Modeling and Generation for SoC Design, International Conference on Hardware - Software Codesign and System Synthesis CODES-ISSS 2005, New York Metropolitan Area, USA, September 18-21, 2005
 
(1456) Jerraya A. A., Sasongko A, Rousseau F., Shortening SoC Design Time with New Prototyping Flow on Reconfigurable Platform, ISRN: TIMA-RR--05/05-01--FR, 2005
 
(1457) Sasongko A, Jerraya A. A., Rousseau F., Shortening SoC Design Time with New Prototyping Flow on Reconfigurable Platform, IEEE-NEWCAS Conference, 2005. The 3rd International 19-22 June, 2005, 2005
 
(1458) Nicolaidis M., Anghel L., Simulation and mitigation of single event effects, 11th-IEEE-International-On-Line-Testing-Symposium, 2005
 
(1459) Faure F., Velazco R., Peronnard P., Single-event-upset-like fault injection: a comprehensive framework, IEEE Transactions on Nuclear Science, Dec. ; 52(6) , page: 2205-9, 2005
 
(1460) Reis R., Anghel L., Lazzari C., Soft error circuit hardening techniques implementation using an automatic layout generator , Proceedings of IEEE Latin American Test Workshop, Salvador Bahia, Bresil, March 30-April 2, 2005
 
(1461) Nicolaidis M., Soft Error: The Fifth Element, Innovative Practice Session: Soft Errors, IEEE VLSI Test Symposium (VTS 2005), Palm Springs, California, May 1 – 5, 2005
 
(1462) Allier E., Fesquet L., Aeschlimann F., Renaudin M., Spectral analysis of level crossing sampling scheme, International Workshop on Sampling theory and application (SAMPTA’'05), Samsun, Turkey, July 10-15, 2005
 
(1463) Renaudin M., Fesquet L., Allier E., Aeschlimann F., Spectral Analysis of Level-Crossing Sampling Scheme, ISRN: TIMA-RR--06/02-13--FR, 2005
 
(1464) Galy N., Study of a full fingerprint recognition system for a sweeping mode microsystem sensor, These de Doctorat, 2005
 
(1465) Koch-Hofer C., Subset of SystemC for Modeling Asynchronous Systems, ISRN: TIMA-RR--05/11-01--FR, 2005
 
(1466) Al Sammane G., Symbolic simulation of circuits described at the algorithmic level, These de Doctorat, 2005
 
(1467) Courtois B., Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2004), 12-14 May 2004, Montreux, Switzerland: Special Issue, Analog Integrated Circuits and Signal Processing, Springer , Volume 44, Number 2, 107-183, 2005
 
(1468) Courtois B., Markus K., Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2005), Montreux,Switzerland, June 1-3, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, , 2005
 
(1469) Jerraya A. A., Hristov M., Amblard P., Petkov I., Systematic design flow for fast hardware/software prototype generation from bus functional model for MPSoC, Proceedings. The 16th International Workshop on Rapid System Prototyping RSP 2005, 2005
 
(1470) Pajaniradja S., Coussy P., Heller D., Blanc F., Tabet F., Martin E., Adriano S., Nouacer R., Kriaa L., Vaumorin E., SystemC’mantic1: A high level modeling and Co-design Framework for Reconfigurable Real Time Systems, Forum on specificiation and Design Languages (FDL’05), Lausanne, Switzerland, September 27-30, 2005
 
(1471) Bregier V., Folco B., Renaudin M., Fesquet L., Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits, ISRN: TIMA-RR--06/02-03--FR, 2005
 
(1472) Folco B., Bregier V., Fesquet L., Renaudin M., Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits, 15th IFIP Int. Conf. on Very Large Scale Integration Systems (VLSI-SoC'05), October 17-19. Perth, FR, 2005
 
(1473) Chapuis O., Trannoy Nathalie, Tessier G., Gomes S., Vairac Pascal, Nepveu F., Dhilaire Stephan, Charlot B., Cretin Bernard, Volz Sébastian, Temperature Measurement of Microsystems by Scanning Thermal Microscopy, International Worshop on Thermal Investigation of ICs and Systems, 27-30 Sep 2005, Belgirate Lake Maggiore Italy, 2005
 
(1474) Danelon V., Carbonero J.L., Mir S., Kheriji R., Test orienté défaut pour les circuits radio fréquences, 14ème Journées Nationales Microondes (JNM’05), Nantes, France, May , 2005
 
(1475) Amblard P., The earliest formal language and its associated finite state evaluation automaton : Jevons' machine, 11th International conference Automata and Formal Languages (AFL'05), May 17-20. Dobogoko, HU, 2005
 
(1476) Farkas G., Courtois B., Poppe A., Szekely V., Szabo P., Rencz M., Thermal characterization and modeling of stacked die packages, Technical Conference and Exhibition on Integration and Packaging of Micro, Nano and Electronic Systems (InterPACK'05), San Francisco, Ca., USA, July 17-22, 2005
 
(1477) Courtois B., Farkas G., Szekely V., Szabo P., Rencz M., Poppe A., Thermal modelling of multiple die packages, Electronic Packaging Technology Conference, 2005. EPTC 2005. Proceedings of 7th. Singapore, SG, 2005
 
(1478) Ress S., Horvath G.Y., Bognar G.Y., Perkaly G., Szabo P., Poppe A., Szekely V., Courtois B., Rencz M., Thermo-Mechanical Characterization and Integrity Checking of Packages and Movable-Structures, Technical Proceedings of the 2005 Nanotechnology Conference and Trade Show, Volume 3. Anaheim, California, US, 2005
 
(1479) Renaudin M., Beigné E., Crochon E., Caucheteux D., Toward Asynchronous and High Data Rates Contactless Systems, Proceedings of the 1st IEEE Ph.D. Research in Micro-Electronics and Electronics Conference (PRIME’'05), Lausanne, Switzerland, 25-28 July, 2005
 
(1480) Leveugle R., Portolan M., Towards a secure and reliable system, Embedded and ubiquitous computing (International conference EUC 2005), Nagasaki, Japan, December 6-9, 2005) , 2005
 
(1481) Anghel L., Nicolaidis M., Kolonis E., Transient and permanent fault tolerance memory cells for unreliable future nanotechnologies, IEEE Latin American Test Workshop (LATW'05), Salvador Bahia, Brazil, 2005
 
(1482) Cretin Bernard, Charlot B., Gomes S., Trannoy Nathalie, Volz Sébastian, Tessier G., Dhilaire Stephan, Genix Mickaël, Vairac Pascal, Ultra-local temperature mapping with an intrinsic thermocouple, Proceedings on 11th International Workshop on THERMAL INVESTIGATIONS OF ICs an Systems, 2005
 
(1483) Nicolaidis M., Une Philosophie Numérique des Univers, TIMA EDITIONS, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 303 pages, 2005
 
(1484) Bonaciu M., Bouchhima A., Jerraya A. A., Youssef W., Bacivarov I., Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration, Asia South Pacific Design Automation Conference (ASP-DAC 2005), Shangai, China, January 18-21, 2005
 
(1485) Amblard P., Using lustre in practical educational activities : digital circuits design, formal languages, ETAPS Workshop : Synchronous Language Applications Programming (SLAP’05), Edinburgh, April 3, 2005
 
(1486) Al Sammane G., Chevallier R., Borrione D., Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning, Great Lakes Symposium on VLSI archive Proceedings of the 15th ACM Great Lakes symposium on VLSI. Chicago, Illinois, US, 2005
 
(1487) Buhrig A., Basrour S., Matou K., Charlot B., Marzencki M., Ammar Y., Renaudin M., Wireless sensor network node with asynchronous architecture and vibration harvesting micro power generator, The Smart Objects and Ambient Intelligence Conference (SoC-EUSAI'05), October 12-14. Grenoble, FR, 2005
 
(1488) Nicolaidis M., Teixeira J.P., 10th IEEE International On-Line Testing Symposium (IOLT 2004), Madeira Island, Portugal, July 12-14, 2004, IEEE Computer Society, 252 pages, 2004
 
(1489) Szekely V., Rencz M., Courtois B., Lasance C., 10th International Workshop on THERmal Investigations of ICs and Systems (THERMINIC 2004), Sophia Antipolis, Côte d'Azur, France, 29 September - 1 October, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, , 2004
 
(1490) Aitken R., Sun X., Salsano A., Velazco R., 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’04), Cannes, France, October 11-13, IEEE Computer Society, , 2004
 
(1491) Mir S., Rolindez L., Prenat G., Bounceur A., A 0.18 ìm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns, ISRN: TIMA-RR--04/05-05--FR, 2004
 
(1492) Prenat G., Mir S., Rolindez L., Bounceur A., A 0.18 ìm CMOS Implementation On-chip Analogue Test Signal Generation from Digital Test Patterns, ISRN: TIMA-RR--04/02-02--FR, 2004
 
(1493) Rolindez L., Prenat G., Bounceur A., Mir S., A 0.18 mu m CMOS implementation of on-chip analogue test signal generation from digital test patterns, Proceedings. Design, Automation and Test in Europe Conference and Exhibition, 2004
 
(1494) Ciontu F., Courtois B., Roman C., A carbon nanotube-based sensor for measuring forces developed by cells, Nanotechnology Conference and TradeShow (NanoTech’04), Boston, Massachusetts, U.S.A., March 7-11, 2004
 
(1495) Leveugle R., Portolan M., A context-switch based checkpoint and rollback scheme, 19th Conference on Design of Circuits and Integrated Systems (DCIS), Bordeaux, France, November 24-26, 2004
 
(1496) Panyasak D., Renaudin M., Sicard G., A current shaping methodology for lowering EM disturbances in asynchronous circuits, Microelectronics journal, June: 35(6), page: 531-40, 2004
 
(1497) Charlot B., Fournier C., Torki K., Filloy C., A digital CMOS circuit for reflectance thermography, ISRN: TIMA-RR--05/02-02--FR, 2004
 
(1498) Torki K., Filloy C., Charlot B., Tessier G., Fournier C., A digital CMOS circuit for reflectance thermography, 10th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC’04), Sophia Antipolis, Côte d'Azur, France, 29 September - 1 October, 2004
 
(1499) Nicolaidis M., Achouri N., Anghel L., A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies, 22nd IEEE VLSI Test Symposium, 2004
 
(1500) Bacivarov I., Jerraya A. A., Yoo S., A fast and accurate validation technique for operating system in multi-processor system-on-chip design, Proceedings of the SPIE The International Society for Optical Engineering, 5227(1):, page: 342-8, 2004
 
(1501) Parrain F., Charlot B., Galy N., Courtois B., A full identification system for a tactile fingerprint sensor, Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP’04), Montreux, Switzerland, May 12-14, 2004
 
(1502) Borrione D., Schmaltz J., A functional approach to the formal specification of networks on chip, Formal Methods in Computer Aided Design. 5th International Conference, FMCAD 2004. Proceedings Lecture Notes in Computer Science Vol.3312., 2004
 
(1503) Schmaltz J., Borrione D., A Functional Approach to the Formal Specification of Networks on Chip, Formal Methods in Computer-Aided Design: 5th International Confrence, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004. Proceedings , Springer , 52, 2004
 
(1504) Borrione D., Schmaltz J., A functional specification and validation model for networks on chip in the ACL2 logic , 5th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'04), Austin, Texas, USA, Septembre 18-19, 2004
 
(1505) Borrione D., Schmaltz J., A functionnal approach to the formal specification of networks on chip, ISRN: TIMA-RR--04/04-01--FR, 2004
 
(1506) Zergainoh N.-E., Baghdadi A., Jerraya A. A., A generic architecture platform based-methodology for an efficient design of Hardware/Software application-specific multiprocessor System-On-Chip , Annals of telecommunications, Vol. 59-August, page: , 2004
 
(1507) Rolindez L., Mir S., Prenat G., Vasquez D., A low-cost digital frequency testing approach for mixed-signal devices using sigma delta modulation , ISRN: TIMA-RR--04/05-03--FR, 2004
 
(1508) Rolindez L., Vasquez D., Mir S., Prenat G., A low-cost digital frequency testing approach for mixed-signal devices using sigma-delta modulation, 10th International Mixed-Signal Testing Workshop (IMSTW’04), Portland, USA, June 23-25, 2004
 
(1509) Slimani K., Renaudin M., Sicard G., A Methodology for estimating energy consumption of QDI asynchronous circuits, 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’04), Isle of Santorini, Greece, September 15-17, 2004
 
(1510) Bognar G.Y., Rencz M., Szekely V., Courtois B., Charlot B., An 8x8 thermopile based uncooled infrared sensor, Europen Micro and Nano Systems (EMN’04), Paris, France, October 20-21, 2004
 
(1511) Jerraya A. A., Cesario W., Gharsalli F., Baghdadi A., Bonaciu M., Majauskas G., An efficient architecture for the implementation of message passing programming model on massive multiprocessor, Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004
 
(1512) Jerraya A. A., Han Sang-Il, Bonaciu M., Chae Soo-Ik, Baghdadi A., An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory, Proceedings-2004.-Design-Automation-Conference-, 2004
 
(1513) Renaudin M., Sicard G., Allier E., Fesquet L., A new type of Asynchronous Analog to Digital Interface, Journal of International Measurement Confederation, Vol.35 , page: , 2004
 
(1514) Parrain F., Courtois B., Basrour S., Galy N., Charlot B., An integrated MEMS fingerprint Sensor, ISRN: TIMA--RR--04/08-01-FR, 2004
 
(1515) Ress S., Rencz M., Poppe A., Kollar E., Szekely V., Courtois B., A procedure to correct the error in the structure function based thermal measuring methods, Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium IEEE Cat. No.04CH37545., 2004
 
(1516) Courtois B., Ciontu F., Roman C., Aromatic amino acids and physisorbed on graphene: electronic properties and Hamiltonian reduction, ISRN: TIMA-RR--05/01-02--FR, 2004
 
(1517) Roman C., Ciontu F., Courtois B., Aromatic amino acids physisorbed on graphene :electronic properties and hamiltonian model reduction, Europen Micro and Nano Systems (EMN’04), Paris, France, October 20-21, 2004
 
(1518) Velazco R., Ziade H., Ayoubi R., A survey on fault injection techniques, International Arab Journal of Information Technology (IAJIT), Vol. 1, page: 171-186, 2004
 
(1519) Basrour S., Parrain F., Galy N., Courtois B., Charlot B., A sweeping mode integrated fingerprint sensor with 256 tactile microbeams, Journal of Microelectromechanical Systems, 13(4), page: 636-44, 2004
 
(1520) Germain F., Renaudin M., Bouesse G.F., Asynchronous AES Crypto-Processor including Secured and Optimized Blocks, Journal of Integrated Circuits and Systems, Vol. 1, page: 5-13, 2004
 
(1521) Monnet Y., Leveugle R., Renaudin M., Asynchronous circuits sensitivity to fault injection, Proceedings.-10th-IEEE-International-On-Line-Testing-Symposium. 2004, 2004
 
(1522) Fesquet L., Aeschlimann F., Renaudin M., Allier E., Asynchronous FIR filters: towards a new digital processing chain, Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on, 2004
 
(1523) Fesquet L., Renaudin M., Essalhiene M., Asynchronous technology for energy reduction in embedded systems, Annals of telecommunications, Vol. 59-August, page: , 2004
 
(1524) Sicard G., Renaudin M., Panyasak D., Asynchronus design for improved EMC behavior of ICs, 4th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo’04), Angers, France, March 31-April 1st, 2004
 
(1525) Sarmento A., Jerraya A. A., Cesario W., Automatic building of executable models from abstract SoC architectures made of heterogeneous subsystems, Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004
 
(1526) Sonza Reorda M., Sanchez E., Velazco R., Squillero G., Automatic verification of RT-level microprocessor cores using behavioral specifications: a case study, XIX Conference on Design of Circuits and Integrated Systems (DCIS’04), Bordeaux, France, November 24-26, 2004
 
(1527) Basrour S., Ammar Y., Behavioural modeling of micro-batteries for Self Powered Micro Systems, Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP'04), May 12-14, 2004
 
(1528) Toma D., Borrione D., Al Sammane G., Combining several paradigms for circuit validation and verification , ISRN: TIMA-RR--04/07-01--FR, 2004
 
(1529) Paviot Y., Cesario W., Stuikys V., Jerraya A. A., Majauskas G., Lyonnard D., Gauthier L., Communication Co-Processor Design by Composition of Parameterized Cells, Information Technology and Control, , 13-20, 2004
 
(1530) Paviot Y., Communication services partitioning for automatic generation of hardware software interfaces , These de Doctorat, 2004
 
(1531) Mir S., Simeu E., Naal M. A., Comparative study of online testing methods for AMS application to decimation filters, Proceedings. 2004 International Conference on Information and Communication Technologies: From Theory to Applications IEEE Cat. No.04EX852, 2004
 
(1532) Mir S., Simeu E., Naal M. A., Comparative Study of On-Line Testing Methods for AMS Systems. Application to Decimation Filters, ISRN: TIMA-RR--04/05-02--FR, 2004
 
(1533) De Labacherie M., Basrour S., Coudevylle J.-R., Comparison of High Q microresonators operating on a thin plate mode : the Lamé-mode, Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP’04), Montreux, Switzerland, May 12-14, 2004
 
(1534) Sicard G., Conception avec VHDL-AMS, , , 2004
 
(1535) Abou-Samra S.-J., Guyot A., Conception pour la faible consommation , , , 2004
 
(1536) Sonza Reorda M., Squillero G., Velazco R., Anghel L., Sanchez E., Coupling Different Methodologies to Validate Obsolete Microprocessors, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004
 
(1537) Youssef W., Jerraya A. A., Paviot Y., Yoo S., Sasongko A, Debugging HW/SW interface for MPSoC: video encoder system design case study, Proceedings-2004.-Design-Automation-Conference, 2004
 
(1538) Sasongko A, Paviot Y., Yoo S., Youssef W., Jerraya A. A., Debugging HW/SW Interface for MPSoC: Video Encoder System Design Case Study, ISRN: TIMA-RR--04/05-01--FR, 2004
 
(1539) Basrour S., Dépôts en phase liquide : application aux microtechniques, Techniques de fabrication des microsystèmes 1 : structures et microsystèmes électromécaniques en couches minces, Hermès, 91-120, 2004
 
(1540) Courtois B., Rencz M., Szekely V., Ciontu F., Bognar G.Y., Charlot B., Design and verification of an electrostatic MEMS simulator , Nanotechnology Conference and TradeShow (NanoTech’04), Boston, Massachusetts, U.S.A., March 7-11, 2004
 
(1541) Gueddah N., Torki K., Masmoudi M., Abid M., Design of a 1V CMOS operational amplifier for programmable resolution A/D converter, SCS'2004 Congrès International : Signaux, Circuits et Systèmes, Monastir – Tunisia, 2004
 
(1542) Bergeret E., Borrione D., Perez A, Toma D., Design of a proven correct SHA circuit , International Conference on Electrical, Electronic and Computer Engineering (ICEEC-04), Cairo, Egypt, September 5-7, 2004
 
(1543) Quartana J., Design of Asynchronous Network on Chip: application to GALS systems, These de Doctorat, 2004
 
(1544) Dziri A., Design tools and hardware/software components integration models for heterogeneous embedded systems design, These de Doctorat, 2004
 
(1545) Rencz M., Szekely V., Courtois B., Nguyen L., Howard N., Zhang L., Die attach quality control of 3D stacked dies, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium IEEE Cat. No.04CH37585, 2004
 
(1546) Beigné E., Renaudin M., Prevosto S., Robisson B., Bouesse G.F., Liardet P.-Y., DPA on quasi delay insensitive asynchronous circuits: concrete results, XIX Conference on Design of Circuits and Integrated Systems (DCIS’04), Bordeaux, France, November 24-26, 2004
 
(1547) Sicard G., Renaudin M., Labonne E., Dynamic Voltage Scaling and Adaptive Body Biasing Study for Asynchronous Design, ISRN: TIMA-RR--04/06-01--FR, 2004
 
(1548) Leveugle R., Early analysis of fault-attack effects for cryptographic hardware, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC’04), Florence, Italy, June 30 (Supplemental volume of the 2004 International Conference on Dependable Systems and Networks (DSN’04), pp. 348-353, 2004), 2004
 
(1549) Ammari A., Leveugle R., Early SEU fault injection in digital, analog and mixed signal circuits: a global flow, Proceedings. Design, Automation and Test in Europe Conference and Exhibition, 2004
 
(1550) Panyasak D., ELECTROMAGNETIC EMISSION REDUCTION IN INTEGRATED CIRCUITS : THE ASYNCHRONOUS ALTERNATIVE, These de Doctorat, 2004
 
(1551) Courtois B., Fruman D., European Forum on Micro and Nano Systems 2004 (EMN’04), Paris, France, October 20-21, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, , 2004
 
(1552) Jerraya A. A., EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package, ASP DAC 2004: Asia and South Pacific Design Automation Conference 2004, 2004
 
(1553) Anghel L., Nicolaidis M., Achouri N., Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologies, 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04), 2004
 
(1554) Jager T., Despesse G., Exploitation of the thermotunnel effect for energy scavenging, Journal of Applied Physics, Vol. 96, page: 5026–5031, 2004
 
(1555) De Labacherie M., Coudevylle J.-R., Basrour S., Fabrication and characterization of high-Q microresonators using thin plate mechanical mod, Proceedings of SPIE -- Volume 5343 Reliability, Testing, and Characterization of MEMS/MOEMS III, 2004
 
(1556) Jerraya A. A., Bouchhima A., Yoo S., Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model, ASP DAC 2004: Asia and South Pacific Design Automation Conference 2004 IEEE, 2004
 
(1557) Al Sammane G., Borrione D., Schmaltz J., Formal design and verification of on chip networking, Proceedings. 2004 International Conference on Information and Communication Technologies: From Theory to Applications IEEE Cat. No.04EX852., 2004
 
(1558) Renaudin M., Yakovlev A., From Hardware Processes to asynchronous circuits via petri nets: An Application to Arbiter Design , Workshop on Token Based Computing (TOBACO’04), Bologna, Italy, June 22, 2004
 
(1559) Schmaltz J., Functional Specification and Validation of the Octagon Network on Chip using the ACL2 Theorem Prover, ISRN: TIMA-RR--04/01-02--FR, 2004
 
(1560) Simeu E., Mir S., Bounceur A., Génération et optimisation de vecteurs de test pour des composants analogiques et mixtes, 7ème Journées Nationales du Réseau Doctoral de Microélectronique, Marseille, France, May 4-6, 2004
 
(1561) Simeu E., Bounceur A., Mir S., Génération et optimisation de vecteurs de test pour des composants analogiques et mixtes, ISRN: TIMA-RR--04/05-04--FR, 2004
 
(1562) Courtois B., Guest Editorial, Analog Integrated Circuits and Signal Processing, August, Volume 40, Number 2, page: 115-116, 2004
 
(1563) Zergainoh N.-E., Jerraya A. A., Baghdadi A., Hardware/Software Codesign of On-chip communication architecture for application-specific multiprocessor System-On-Chip, IJES - International Journal of Embedded Systems , Vol.1, page: , 2004
 
(1564) Cesario W., Jerraya A. A., Wagner F.R., Hardware/Software Interfaces Design for SoC, The Industrial Information Technology Handbook, CRC Press, section VI, N°94, 2004
 
(1565) Tual J.-P., Proust Ph., Germain F., Sourgen L., Bouesse G.F., Renaudin M., High security smartcards, Proceedings. Design, Automation and Test in Europe Conference and Exhibition, 2004
 
(1566) Bouesse G.F., Renaudin M., Monnet Y., Improving DPA and DFA resistance of circuits using asynchronous logic, e-Smart 2004 and e-Government & Smartcard International Meeting, 5th Edition, Sophia Antipolis, French Riviera, France, September 22-24, 2004
 
(1567) Rencz M., Courtois B., Szekely V., Kollar E., Poppe A., Ress S., Increasing the accuracy of structure function based evaluation of thermal transient measurements, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems IEEE Cat. No.04CH37543, 2004
 
(1568) Courtois B., Infrastructures for education, research and industry in microelectronics - a review, DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications., 2004
 
(1569) Di Pendina G., Courtois B., Delori H., Colin S., Paillotin J.-F., Eyraud S., Torki K., Infrastructures for education, research and industry in microelectronics – Developments at CMP and worldwide cooperation, 10th International Symposium on Integrated Circuits, Devices & Systems (ISIC'’04), Integrated Systems on Silicon Suntec, Singapore, 8-10 September, 2004
 
(1570) Lagnier F., Amblard P., Levy M., Introduction to formal processor verification at logic level : a case study, Workshop on Computer Architecture Education (WCAE’04), Munich, Germany, June 19-23, 2004
 
(1571) Nicolescu G., Jerraya A. A., La spécification et la validation des systèmes monopuces, Hermès, , 2004
 
(1572) Fesquet L., Le paquetage VITAL, , , 2004
 
(1573) Fesquet L., Les bases de la conception analogique intégrée, , , 2004
 
(1574) Rezzag A., Logical synthesis of micropipeline asynchronous circuits, These de Doctorat, 2004
 
(1575) Jerraya A. A., Long term trends for embedded system design, Proceedings of the Euromicro Symposium on Digital System Design, 2004
 
(1576) Jerraya A. A., Long Term Trends for Embedded System Design, ISRN: TIMA-RR--04/09-02--FR, 2004
 
(1577) Slimani K., Low power asynchronous microprocessors, These de Doctorat, 2004
 
(1578) Fragoso J., Slimani K., Fesquet L., Renaudin M., Low Power Asynchronous Processors, Low-Power Electronics Design, CRC Press, Chapter 22; Volume: 1, 2004
 
(1579) Bouchhima A., Yoo S., Cesario W., Gauthier L., Jerraya A. A., Low-power SoC with power-aware operating systems generation, “Low-Power Electronics Design”, CRC Press, n°1941, August , , , 2004
 
(1580) Gauthier L., Jerraya A. A., Cesario W., Bouchhima A., Yoo S., Low-Power SoC with Power-Aware Operating Systems Generation, Low-Power Electronics Design, CRC Press, chapitre 3, 2004
 
(1581) Jerraya A. A., Zergainoh N.-E., Urard P., Popovici K., Matlab based environment for designing DSP systems using IP blocks, The 12th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI’04), Kanazawa, Japan, October 18-19, 2004
 
(1582) Rufer L., Dhayni A., Mir S., MEMS Built-in-Self-Test Using MLS , ISRN: TIMA-RR--04/05-06--FR, 2004
 
(1583) Dhayni A., Mir S., Rufer L., MEMS Built-In-Self-Test Using MLS, European Test Symposium, Ninth IEEE (ETS'04), 2004
 
(1584) Bethillier Marc, Foltete E., Basrour S., Ballandras S., Hirsinger L., Marzencki M., De Labacherie M., Micro-convertisseur d'énergie mécano-électrique, 3ème Workshop Franco-Suisse du Laboratoire Européen Associé en Microtechniques, Arc-et-Senans, France, 21-22 septembre, 2004
 
(1585) Courtois B., Microsystem Technologies: Foreword to special issue on Design, Test, Integration and Packaging of MEMS/MOEMS, 2003, Microsystem Technologies, August, Volume 10, Number 5, page: 345, 2004
 
(1586) Fesquet L., Renaudin M., Folco B., Bregier V., Modeling and synthesis of multi-rail multi-protocol QDI circuits, Thirteenth International Workshop on Logic and Synthesis, Temecula Creek (IWLS’04), California, USA, June 2-4, 2004
 
(1587) Sirianni A., Mounier L., Renaudin M., Boubekeur M., Borrione D., Modeling CHP descriptions in labeled transitions systems for an efficient formal validation of asynchronous circuit specification, "Languages for System Specification", Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems and Property Specifications from FDL'03, Christoph Grimm, Kluwer, June , Kluwer Academic Publishers, , 2004
 
(1588) Sirianni A., Modeling, simulation and verification of asynchronous circuits in SystemC v2.0.1 standard, These de Doctorat, 2004
 
(1589) Fesquet L., Modélisation et synthèse des systèmes matériels, , , 2004
 
(1590) Bouchhima A., Yoo S., Youssef W., Jerraya A. A., Multi-processor SoC design methodology using a concept of two-layer hardware-dependent software, Proceedings.-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition. 2004, 2004
 
(1591) Jerraya A. A., Wolf W., MULTIPROCESSOR SYSTEMS-ON-CHIPS, Morgan Kaufmann Publishers, 608, 2004
 
(1592) Ciontu F., Nanosprint: an infrastructure for nanotechnology foresight, Europen Micro and Nano Systems (EMN’04), Paris, France, October 20-21, 2004
 
(1593) Jerraya A. A., Rousseau F., Grasset A., Network interface generation for MPSOC: from communication service requirements to RTL implementation, Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004
 
(1594) Lyonnard D., Gauthier L., Nicolescu G., Cesario W., Jerraya A. A., Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits, Journal of Systems and Software, Volume 70 2004, page: 229-244, 2004
 
(1595) Rufer L., Courtois B., Charlot B., Mir S., On-chip testing of embedded silicon transducers, ISRN: TIMA-RR--04/07-02--FR, 2004
 
(1596) Rufer L., Charlot B., Mir S., Courtois B., On-chip testing of embedded silicon transducers, Proceedings. IEEE International SOC Conference IEEE Cat. No.04TH8744, 2004
 
(1597) Mir S., Courtois B., Rufer L., Charlot B., On-chip testing of embedded silicon transducers, The 16th International Conference on Microelectronics IEEE Cat. No.04EX918, 2004
 
(1598) Courtois B., Charlot B., Mir S., Rufer L., On-chip testing of embedded transducers, Proceedings 17th International Conference on VLSI Design, 2004
 
(1599) Mir S., Rufer L., Courtois B., On-chip testing of embedded transducers, ISRN: TIMA-RR--04/05-07--FR, 2004
 
(1600) Ammari A., Leveugle R., Hadjiat K., On combining fault classification and error propagation analysis in RT-Level dependability evaluation, Proceedings. 10th IEEE International On Line Testing Symposium, 2004
 
(1601) Mir S., Rufer L., Simeu E., Online Testing Embedded Systems: Adapting Automatic Control Techniques to Microelectronic Testing , ISRN: ISRN-RR--04/09-01-FR, 2004
 
(1602) Portolan M., Leveugle R., Operating system function reuse to achieve low-cost fault tolerance, On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International, 2004
 
(1603) Simeu E., Mir S., Bounceur A., Optimisation of digitally coded test vectors for mixed-signal components, 19th Conference on Design of Circuits and Integrated Systems (DCIS’04), Bordeaux, France, November 24-26, 2004
 
(1604) Danelon V., Mir S., Carbonero J.L., Kheriji R., Optimising test sets for RF components with a defect-oriented approach, The 16th International Conference on Microelectronics IEEE Cat. No.04EX918., 2004
 
(1605) Carbonero J.L., Danelon V., Mir S., Kheriji R., Optimising test sets for RF components with a defect-oriented approach, ISRN: TIMA-RR--05/02-01--FR, 2004
 
(1606) Nicolescu B., Velazco R., Savaria B.Y., Performance evaluation and failure prediction for the soft implemented error detection technique, 10th International On-Line Testing Symposium (IOLTS’04), Funchal, Mareira, Portugal, July 12-14, 2004
 
(1607) Velazco R., Savaria B.Y., Nicolescu B., Performance evaluation and failure rate prediction for the soft implemented error detection technique, Proceedings. 10th IEEE International On Line Testing Symposium., 2004
 
(1608) Fesquet L., Mancini S., Rolland R., Baixas A., Pratique d'un SOPC : application au filtrage numérique, , , 2004
 
(1609) Courtois B., Szekely V., Rencz M., Lasance C., Proceedings on 10th International Workshop on THERMAL INVESTIGATIONS of ICs and Systems (THERMINIC 2004), 29 September - 1 October 2004, Sophia Antipolis, Côte d'Azur, France, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 335 pages, 2004
 
(1610) Courtois B., Markus K., Proceedings on Symposium on Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP'04), Montreux, Switzerland, May 12-14, 2004, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 487 pages, 2004
 
(1611) Sasongko A, Prototyping based on reconfigurable platform for verification of system-on-chip, These de Doctorat, 2004
 
(1612) Amblard P., Proving good synchronization between Finite State Machines : a case study, EUROMICRO Symposium on Digital System Design (DSD 2004), Rennes, France, August 31-September 3, 2004
 
(1613) Bouesse G.F., Baixas A., Sicard G., Renaudin M., Quasi delay insensitive asynchronous circuits for low EMI, 4th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo’04), Angers, France, March 31-April 1st, 2004
 
(1614) Razafindraibe A., Renaudin M., Robert M., Bouesse G.F., Maurine P., Folco B., Secured Structures for Secured Asynchronous QDI Circuits, XIX Conference on Design of Circuits and Integrated Systems (DCIS’04), Bordeaux, France, November 24-26, 2004
 
(1615) Nicolaidis M., Alexandrescu D., Anghel L., Simulating single event transients in VDSM ICs for ground level radiation, Journal of Electronic Testing: Theory and Applications, Aug. ; 20(4), page: 413-21, 2004
 
(1616) Faure F., Velazco R., Single event effects characterization of complex cigital circuits: test methodology and tools, , , 285-307, 2004
 
(1617) Courtois B., Roman C., Ciontu F., Single molecule detection and macromolecular weighting using an all-carbon-nanotube nanoelectromechanical sensor, 4th IEEE Conference on Nanotechnology. 16-19 Aug. 2004 Munich, Germany, 2004
 
(1618) Savaria B.Y., Nicolescu B., Velazco R., Software detection mechanisms providing full coverage against single bit-flip faults, IEEE Transactions on Nuclear Science, Volume: 51, page: 3510- 3518, 2004
 
(1619) Nicolescu G., Jerraya A. A., Spécification et validation des systèmes monopuces (Traité EGEM série Electronique et micro-éléctronique), Hermès, 216p. 16x24, 2004
 
(1620) Al Sammane G., Specification of the VHDL subset supported by TheoSim , ISRN: TIMA-RR--04/07-03--FR, 2004
 
(1621) Carro L., Jerraya A. A., Cesario W., Wagner F.R., Strategies for the integration of hardware and software IP components in embedded systems-on-chip, Integration, the VLSI Journal, Volume 37 2004, page: 223-252, 2004
 
(1622) Korvink J., Courtois B., Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2003), 5-7 May 2003 - Mandelieu-La Napoule, , Springer , Volume 40, Number 2, 185 pages, 2004
 
(1623) Courtois B., Michel B., Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2003), 5-7 May 2003, Mandelieu-La Napoule, , Springer , Volume 10, Number 5, 345-437, August 2004, 2004
 
(1624) Ammari A., Leveugle R., Cimonnet D., System-level dependability analysis with RT-level fault injection accuracy, Proceedings. 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004
 
(1625) Renaudin M., Sicard G., Remond Y., Slimani K., TAST profiler and low energy asynchronous design methodology, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. 14th International Workshop, PATMOS 2004. Proceedings , 2004
 
(1626) Fesquet L., TD de modélisation et synthèse des systèmes matériels, , , 2004
 
(1627) Achouri N., Techniques d'Auto Réparation pour les Mémoires à Grandes Densités de Défauts, These de Doctorat, 2004
 
(1628) Courtois B., Poppe A., Rencz M., Szekely V., Testing the die attach quality of 3D stacked dies, International Mechanical Engineering Congress and Exposition (IMECE’04), Anaheim, California, USA, November 13-19, 2004
 
(1629) Toma D., Schmaltz J., Borrione D., Al Sammane G., Ostier P., Theosim : combining symbolic simulation and theorem proving for hardware verification, 17th Symposium on Integrated Circuits and System Design (SBCCI'04), Porto de Galinhas, Pernambuco, Brazil, September 7-11, 2004
 
(1630) Borrione D., Toma D., Al Sammane G., Ostier P., Schmaltz J., TheoSim: combining symbolic simulation and theorem proving for hardware verification, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design IEEE Cat. No.04TH8784., 2004
 
(1631) Rencz M., Szekely V., Poppe A., Farkas G., Courtois B., Thermal qualification of 3D stacked die packages, Proceedings of 6th Electronics Packaging Technology Conference EPTC 2004 IEEE Cat. No.04EX971, 2004
 
(1632) Fesquet L., Rolland R., Mancini S., TP d'architecture d'un SoC, , , 2004
 
(1633) Dziri A., Cesario W., Jerraya A. A., Wagner F.R., Unified component integration flow for multi-processor SoC design and validation, Proceedings.-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition. 2004, 2004
 
(1634) Nicolescu B., Savaria B.Y., Velazco R., Gorse N., Aboulhamid E.M., Validating a dynamic signature monitoring approach using the LTL model checking technique, Radiation and Effects on Components and Systems Workshop (RADECS’'04), Madrid, Spain, September 22-24, 2004
 
(1635) Boubekeur M., Validation of Asynchronous Circuits Specifications: Methods and tools, These de Doctorat, 2004
 
(1636) Borrione D., Toma D., Verification of a cryptographic circuit: SHA-1 using ACL2, 5th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2’04), Austin, Texas, USA, September 18-19, 2004
 
(1637) Courtois B., 3rd International IEEE Conference on Polymers and Adhesives in Microelectronics and Photonics (POLYTRONIC 2003), Montreux, Switzerland, October 21-23, 2003, IEEE Computer Society, , 2003
 
(1638) Gizopoulos D., Nicolaidis M., 9th IEEE International On-Line Testing Symposium (IOLTS 2003), Kos Island, Greece, July 7-9, 2003, IEEE Computer Society, 226 pages, 2003
 
(1639) Rencz M., Courtois B., Lasance C., Szekely V., 9th International Workshop on THERmal Investigations of ICs and Systems (THERMINIC 2003), Aix-en-Provence, France, 24-26 September, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, , 2003
 
(1640) Nicolaidis M., Kolonis E., A Biologically Inspired EDA Framework for Nanotechnologies, ISRN: TIMA-RR--03/05-01--FR, 2003
 
(1641) Szekely V., Rencz M., Poppe A., Courtois B., Algorithmic and modeling aspects in the electro-thermal simulation of thermally operated microsystems, 2003 Nanotechnology Conference and Trade Show. Nanotech 2003. Nanotech 2003 Joint Meeting. 6th International Conference on Modeling and Simulation of Microsystems, MSM 2003. 3rd International Conference on Computational Nanoscience and Technology, ICCN 20, 2003
 
(1642) Nicolaidis M., Achouri N., Anghel L., A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
 
(1643) Achouri N., Anghel L., Nicolaidis M., A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities , ISRN: TIMA-RR--03/08-02--FR, 2003
 
(1644) Tambour L., A Methodology and Semi-Automated Flow for Design and Validation of Digital Signal Processing ASIC Macro-cells, These de Doctorat, 2003
 
(1645) Saleh S., Velazco R., Anghel L., A methodology for test replacement solutions of obsolete processors, ISRN: TIMA-RR--03/08-05--FR, 2003
 
(1646) Saleh S., Velazco R., Anghel L., A Methodology for Test Replacement Solutions of Obsolete Processors, 9th IEEE International On-Line Testing Symposium, 2003
 
(1647) Rencz M., Szekely V., Courtois B., Poppe A., Farkas G., A methodology for the generation of dynamic compact models of packages and heat sinks from thermal transient measurements, IEEE/CPMT/SEMI. 28th International Electronics Manufacturing Technology Symposium Cat. No.03CH37479, 2003
 
(1648) Lyonnard D., An approach for the systematic gathering of interface items toward the generation of multiprocessor architectures, These de Doctorat, 2003
 
(1649) Renaudin M., Borrione D., Sirianni A., Boubekeur M., Rigaud J.B., Dumitrescu E., An approach to the introduction of formal validation in an asynchronous circuit design flow, 36th Hawaii International Conference on Systems Sciences. 6-9 Jan, 2003
 
(1650) Borrione D., Dumitrescu E., Boubekeur M., Renaudin M., Sirianni A., Rigaud J.B., An approach to the introduction of formal validation in an asynchronous circuit design flow, ISRN: TIMA-RR--03/10-01--FR, 2003
 
(1651) Zergainoh N.-E., Tambour L., Michel H., Urard P., Jerraya A. A., An efficient methodology and semi automated flow for design and validation of complex digital signal processing ASICS macro cells, Proceedings 14th IEEE International Workshop on Rapid Systems Prototyping, 2003
 
(1652) Allier E., Renaudin M., Sicard G., Fesquet L., A new class of asynchronous A/D converters based on time quantization, Proceedings Ninth International Symposium on Asynchronous Circuits and Systems, 2003
 
(1653) Domingues C., Mir S., Rufer L., Rolindez L., An implementation of memory-based on-chip analogue test signal generation, Proceedings of the ASP DAC 2003. Asia and South Pacific Design Automation Conference 2003 Cat. No.03EX627, 2003
 
(1654) Paviot Y., Application du flot de ciblage logiciel, Conception des logiciels embarqués pour les systèmes monopuces, Hermès, 196p. 16x24, 2003
 
(1655) Jerraya A. A., Cesario W., Lyonnard D., Paviot Y., Gauthier L., Baghdadi A., Nicolescu G., Yoo S., Application-specific multiprocessor systems-on-chip, Microelectronics journal, Vol.33, No.11, November , page: , 2003
 
(1656) Ostier P., Borrione D., Schmaltz J., Al Sammane G., Toma D., A Shortened Form of Constrained Symbolic Simulation with Mathematica and ACL2, ISRN: TIMA--RR-03/10-05--FR, 2003
 
(1657) Ziade H., Rezgui S., Velazco R., Assessing the soft error rate of digital architectures devoted to operate in radiation environment: a case studied, Journal of Electronic Testing: Theory and Applications, 19(1), page: 83-90, 2003
 
(1658) Galy N., Courtois B., Parrain F., Charlot B., A sweeping mode integrated tactile fingerprint sensor, TRANSDUCERS '03. 12th International Conference on Solid State Sensors, Actuators and Microsystems. Digest of Technical Papers Cat. No.03TH8664., 2003
 
(1659) Allier E., Renaudin M., Sicard P., Fesquet L., Asynchronous ADCs: Design Methodology and Case study, 8th International Workshop on ADC modelling and testing (IWADC’03), Perugia, Italy, September 8-10 , 2003
 
(1660) Allier E., Asynchronous Analog to Digital Interface: a New Class of Converters Based on Time Quantization, These de Doctorat, 2003
 
(1661) Fragoso J., Renaudin M., Asynchronous Circuits Design: An Architectural Approach, Chapter in , , , 2003
 
(1662) Sicard G., Renaudin M., Fragoso J., Automatic generation of 1-of-M QDI asynchronous adders, Proceedings 16th Symposium on Integrated Circuits and Systems Design. SBCCI , 2003
 
(1663) Petkov I., Jerraya A. A., Automatic generation of HW-SW interfaces for MPSOC, Proceedings of the 12th International Scientific and Applied Science Conference "Electronics ET'2003"., 2003
 
(1664) Dinh Duc Anh Vu, Automatic synthesis of QDI asynchronous circuits, These de Doctorat, 2003
 
(1665) Farkas G., Poppe A., Courtois B., Szekely V., Rencz M., Boundary condition independent dynamic compact models of packages and heat sinks from thermal transient measurements, Proceedings of the 5th Electronics Packaging Technology Conference EPTC 2003, 2003
 
(1666) Charlot B., Mir S., Roman C., Building an analogue fault simulation tool and its application to MEMS, Microelectronics journal, 34(10), page: 897-906, 2003
 
(1667) Jerraya A. A., Bouchhima A., Bacivarov I., Yoo S., Paviot Y., Building fast and accurate SW simulation models based on hardware abstraction layer and simulation environment abstraction layer, Proceedings Design, Automation and Test in Europe Conference and Exhibition., 2003
 
(1668) Mir S., Rufer L., Simeu E., Built-in-self -test of linear time invariant systems using maximum - lenght sequences, ISRN: TIMA-RR--03/07-02--FR, 2003
 
(1669) Mir S., Simeu E., Rufer L., Built-in self-test of linear time invariant systems using maximum-length sequences, IEEE European Test Workshop (ETW’03), Maastricht, The Netherlands, May 25-28, 2003
 
(1670) Juneidi Z., CAD tools for MEMS, These de Doctorat, 2003
 
(1671) Nicolaidis M., Carry checking/parity prediction adders and ALUs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. ; 11(1), page: 121-8, 2003
 
(1672) Jerraya A. A., Samet F., Dziri A., Wagner F.R., Cesario W., Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL, Proceedings of the ASP DAC 2003. Asia and South Pacific Design Automation Conference, 2003
 
(1673) Toma D., Borrione D., Al Sammane G., Ostier P., Schmaltz J., Constrained symbolic simulation with Mathematica and ACL2, Correct Hardware Design and Verification Methods. 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003. Proceedings Lecture Notes in Comput. Sci. Vol. 2860., 2003
 
(1674) Schmaltz J., Toma D., Ostier P., Al Sammane G., Borrione D., Constrained Symbolic Simulation with Mathematica and ACL2, ISRN: TIMA-RR--03/07-03--FR, 2003
 
(1675) Dumitrescu E., Construction of Reduced Models and Symbolic Model Checking of Industrial RTL Designs, These de Doctorat, 2003
 
(1676) Allier E., Renaudin M., Fesquet L., Sicard G., Conversion analogique-numérique faible consommation : conception asynchrone et echantillonnage irrégulier, 4ème Colloque sur le Traitement Analogique de l'Information, du Signal, et ses Applications (TAISA’03), Louvain-La-Neuve, Belgique, September 25-26 , 2003
 
(1677) Hunsinger F., Jerraya A. A., François S., Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC), Proceedings. 4th International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, 2003
 
(1678) François S., Hunsinger F., Jerraya A. A., Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC), ISRN: TIMA-RR--03/08-07--FR, 2003
 
(1679) Antoni L., Leveugle R., Feher B., Dependability analysis: a new application for run-time reconfiguration, Proceedings International Parallel and Distributed Processing Symposium, 2003
 
(1680) Rufer L., Domingues C., Mir S., Design of a MEMS-based ultrasonic pulse-echo system, 18th Conference on Design of Circuits and Integrated Systems, Ciudad Real, Spain, November 18-21, 2003
 
(1681) Markus K., Courtois B., Karam J.M., Bergman K., Michel B., Korvink J., Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP 2003), Cannes, France, May 5-7, SPIE Int. Soc. Opt. Eng, , 2003
 
(1682) Ammari A., Violante M., Leveugle R., Sonza Reorda M., Detailed comparison of dependability analyses performed at RT and gate levels, Proceedings. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003
 
(1683) Nicolescu B., Velazco R., Detecting soft errors by a purely software approach: method, tools and experimental results, Embedded Software for SoC, Kluwer Academic Publishers, Chapter 4, 39-50, 2003
 
(1684) Velazco R., Nicolescu B., Detecting soft errors by a purely software approach: method, tools and experimental results, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2003
 
(1685) Achouri N., Nicolaidis M., Boutobza S., Dynamic data-bit memory built-in self-repair, ICCAD 2003. International Conference on Computer Aided Design IEEE Cat. No.03CH37486., 2003
 
(1686) Nicolescu B., Velazco R., Efficiency of a software approach for transient error detection: a case study, 4th IEEE Latin-American Test Workshop (LATW'03), Natal, Brazil, February 16-19, 2003
 
(1687) Perronnard P., Savaria B.Y., Velazco R., Nicolescu B., Efficiency of transient bit-flips detection by software means: a complete study, Proceedings. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., 2003
 
(1688) Torki K., Szekely V., Rencz M., Poppe A., Courtois B., Electro-thermal simulation for the prediction of chip operation within the package, 19th Semiconductor Thermal Measurement and Management Symposium (SEMITHERM’03), San Jose, California, USA, March 11-13, 2003
 
(1689) Torki K., Poppe A., Szekely V., Rencz M., Courtois B., Electro-thermal simulation for the prediction of chip operation within the package, Nineteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium Cat. No.03CH37437, 2003
 
(1690) Rencz M., Poppe A., Szekely V., Courtois B., Electro-thermal simulation of MEMS elements, Design, Test, Integration and Packaging of MEMS/MOEMS 2003 IEEE Cat. No.03EX713, 2003
 
(1691) Jerraya A. A., Sasongko A, Baghdadi A., Rousseau F., Embedded application prototyping on a communication-restricted reconfigurable platform, 14th IEEE International Workshop on Rapid System Prototyping (RSP'03), San Diego, USA, June 9-11, 2003
 
(1692) Sasongko A, Baghdadi A., Rousseau F., Jerraya A. A., Embedded application prototyping on a communication-restricted reconfigurable platform, Proceedings 14th IEEE International Workshop on Rapid Systems Prototyping, 2003
 
(1693) Wehn N., Yoo S., Jerraya A. A., Verkest D., Embedded Software for SoC, Kluwer Academic Publishers, 585, 2003
 
(1694) Sirianni A., Sicard G., Renaudin M., Fesquet L., Slimani K., Remond Y., Estimation et optimisation de la consommation d’énergie des circuits asynchrones, 4èmes journées d'études Faible Tension, Faible Consommation (FTFC’03), pp. 59-64, Paris, France, 15-16 May, 2003
 
(1695) Guyot A., Exercices du cours d'Opérateurs Arithmétiques , , , 2003
 
(1696) De Labacherie M., Coudevylle J.-R., Basrour S., Fabrication and characterization of high Q microresonators using thin plate mechanical mode, Proceedings of the SPIE The International Society for Optical Engineering, 2003
 
(1697) Antoni L., Fault injection using run-time reconfiguration of FPGAs, These de Doctorat, 2003
 
(1698) Amblard P., Lagnier F., Levy M., Finite state machines: composition, verification, minimization: a case study, Proceedings of the 10th International Conference Mixed Design of Integrated Circuits and Systems. MIXDES 2003, 2003
 
(1699) Borrione D., Schmaltz J., Formalization and verification of the AMBA AHB communication architecture using the ACL2 theorem prover, ISRN: TIMA-RR--03/03-01--FR, 2003
 
(1700) Schmaltz J., Borrione D., Formalization and verification of the AMBA AHB communication architecture using the ACL2 theorem prover, 6th International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'03), Poznan, Poland, April 14-16, 2003
 
(1701) Borrione D., Schmaltz J., Formalization and verification of the MBA AHB communication architecture using the ACL2 theorem prover, ISRN: TIMA--RR-03/10-02--FR, 2003
 
(1702) Charlot B., Mir S., From microelectronics to integrated microsystems testing , Journal on Nano et Micro-Technologies, Vol. 3, page: 249-270, 2003
 
(1703) Mir S., Charlot B., From Microelectronics to Integrated Microsystems Testing, Microsystems Technology – Fabrication, test and reliability, Hermes Penton Science, 241-263, 2003
 
(1704) Mir S., From microelectronics to microsystems integrated circuit testing, Invited Talk at 5th IFAC Symposium on Fault Detection, Supervision and Safety of Technical Processes (SAFEPROCESS’03), Washington, D.C., USA, June 9-11, 2003
 
(1705) Renaudin M., Sicard G., Fragoso J., Generalized 1-of-M QDI adders, Third ACiD-WG Workshop of the European Commission’s Fifth Framework Programme, Heraklion, Crete, January 27-28, 2003
 
(1706) Birbas M., Jerraya A. A., Birbas A.N, Alonso A., Sanchez L., Voros N.S., Hardware/Software Co-Design of Complex Embedded Systems: An Approach Using Efficient Process Models, Multiple Formalism Specification and Validation via Co-Simulation, Design Automation for Embedded Systems, March 2003, Volume 8, Number 1, page: 5-49, 2003
 
(1707) Gharsalli F., Hardware-Software Interface Design for Global Memory Intégration in System on Chip, These de Doctorat, 2003
 
(1708) Rebaudengo M., Reorda M.S., Velazco R., Violante M., Faure F., Impact of data cache memory on the single event upset-induced error rate of microprocessors, IEEE Transactions on Nuclear Science, Volume: 50 , Part 1, page: 2101 - 2106, 2003
 
(1709) Ciontu F., Roman C., Courtois B., Information coding and intramolecular integration of logic functionality, 2003 Nanotechnology Conference and Trade Show. Nanotech 2003. Nanotech 2003 Joint Meeting. 6th International Conference on Modeling and Simulation of Microsystems, MSM 2003. 3rd International Conference on Computational Nanoscience and Technology, ICCN 20, 2003
 
(1710) Courtois B., Infrastructures for education and research: from national initiatives to worldwide development, Invited paper at Festkolloquium Zukunftstrendsin der Mikroelektronik Anlass: von 60. Geburtstag Professor Manfred Glesner, Darmstadt, Germany, August 29, 2003
 
(1711) Mir S., Integrated circuits testing: from microelectronics to microsystems, ISRN: TIMA-RR--03/07-01--FR, 2003
 
(1712) Jerraya A. A., Yoo S., Introduction to hardware abstraction layers for SoC, Design, Automation and Test in Europe (DATE'03), Munich, Germany, March 3-7, 2003
 
(1713) Jerraya A. A., Yoo S., Introduction to Hardware Abstraction Layers for SoC, Embedded Software for SoC, Kluwer Academic Publishers, chapitre 14, 179-186, 2003
 
(1714) Nicolle S., Renaudin M., Alacoque L., Irregular sampling and local quantification scheme A-D converter, Electronics Letters, 6 Feb.: 39(3), page: 263-4, 2003
 
(1715) Nicolaidis M., Perez Ribas R., Measuring the width of transient pulses induced by ionising radiation, 2003 IEEE International Reliability Physics Symposium Proceedings 41st Annual Cat. No.03CH37400, 2003
 
(1716) Anghel L., Achouri N., Nicolaidis M., Memory Built-In Self-repair for Nanotechnologies, ISRN: TIMA-RR--03/08-02--FR, 2003
 
(1717) Anghel L., Achouri N., Nicolaidis M., Memory Built-In Self-Repair for Nanotechnologies, 9th IEEE International On-Line Testing Symposium, 2003
 
(1718) Domingues C., Mir S., Rufer L., Simeu E., MLS-based technique for MEMS characterization , 3rd International Workshop on Microfabricated Ultrasonic Transducers (MUT’03), Lausanne, Switzerland, June 26-27, 2003
 
(1719) Borrione D., Mounier L., Sirianni A., Boubekeur M., Renaudin M., Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications, ISRN: TIMA--RR-03/10-04--FR, 2003
 
(1720) Sirianni A., Mounier L., Borrione D., Boubekeur M., Renaudin M., Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications, Forum on specification and Design Languages (FDL'03), Frankfurt, Germany, September 23-26, 2003
 
(1721) Chavet C., Modelisation and Validation of a Chip Embedded Architecture for Secure Applications, ISRN: TIMA-RR--03/11-01--FR, 2003
 
(1722) Roman C., Ciontu F., Molecular approaches for nano-bio devices, ISRN: TIMA-RR--03/12-01--FR, 2003
 
(1723) Hadjiat K., Leveugle R., Multi-level fault injections in VHDL descriptions: alternative approaches and experiments, Journal of Electronic Testing: Theory and Applications, Oct. ; 19(5), page: 559-75, 2003
 
(1724) Bacivarov I., Yoo S., Nicolescu G., Youssef W., Bouchhima A., Jerraya A. A., Multi-level software validation for NoC, Networks-on-chip., Kluwer Academic Publishers, 261-79, 2003
 
(1725) Mir S., Rufer L., Domingues C., Simeu E., On-chip pseudorandom MEMS testing, ISRN: TIMA-RR--03/06-01--FR, 2003
 
(1726) Mir S., Rufer L., Simeu E., Domingues C., On-chip pseudorandom MEMS testing, 9th International Mixed-Signal Testing Workshop (IMSTW’03), Sevilla, Spain, June 25-27, 2003
 
(1727) Mir S., Simeu E., Rufer L., On-chip testing of linear time invariant systems using maximum length sequences, IFAC Workshop on Programmable Devices and Systems, Ostrava, Czech Republic, February , 2003
 
(1728) Mir S., Simeu E., Rufer L., On-chip testing of linear time invariant systems using maximum-length sequences, ISRN: TIMA-RR--03/01-01--FR, 2003
 
(1729) Rufer L., Simeu E., Mir S., Domingues C., On-chip testing of MEMS using pseudo-random test sequences, Design, Test, Integration and Packaging of MEMS/MOEMS 2003 IEEE Cat. No.03EX713, 2003
 
(1730) Rufer L., Simeu E., Mir S., Domingues C., On-Chip testing of MEMS using pseudo-random test sequences, ISRN: TIMA-RR--03/03-02--FR, 2003
 
(1731) Mir S., Naal M. A., Simeu E., On-Line Testable Decimation Filter Design for AMS Systems, 9th IEEE International On-Line Testing Symposium, 2003
 
(1732) Mir S., Naal M. A., Simeu E., On-Line Testable Design: Application to Decimation Filter for AMS Systems, ISRN: TIMA-RR--03/08-01--FR, 2003
 
(1733) Boutobza S., Achouri N., Nicolaidis M., Optimal reconfiguration functions for column or data-bit built-in self-repair, Proceedings-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition. 2003:, 2003
 
(1734) Fouillat P., Pouget V., Dallet D., Lewis D., Velazco R., Performance impact of various SEE mechanisms in classical analog-to-digital converter architectures, IEEE Nuclear and Space Radiation Effects Conference (NSREC'03), Monterey, USA, July 19-23, 2003
 
(1735) Hristov M., Jerraya A. A., Amblard P., Petkov I., Physical design of HW interfaces for MPSoC, 7th International Symposium on Microelectronics Technologies and Microsystems in cooperation with 12th International Scientific and Applied Science Conference ELECTRONICS 2003, 2003
 
(1736) Renaudin M., Sicard G., Fragoso J., Power/Area trade-offs in 1-of-M parallel-prefix asynchronous adders, 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'03), Torino, Italy, September 10-12, 2003
 
(1737) Saleh S., Anghel L., Velazco R., Preliminary validation of an approach dealing with processor obsolescence, ISRN: TIMA-RR--03/08-03--FR, 2003
 
(1738) Velazco R., Anghel L., El Moucary A., Saleh S., Deswaertes S., Preliminary Validation of an Approach Dealing with Processor Obsolescence, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
 
(1739) Allier E., Fesquet L., Renaudin M., Sicard G., Procédé et dispositif de conversion analogique-numérique, FR2835365, 2003
 
(1740) Rencz M., Lasance C., Courtois B., Szekely V., Proceedings on 9th International Workshop on THERMAL INVESTIGATIONS of ICs and Systems (THERMINIC 2003), 24-26 September 2003, Aix-en-Provence, France, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 341 pages, 2003
 
(1741) Markus K., Courtois B., Proceedings on Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'03), Cannes, France, May 5-7, 2003, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 412 pages, 2003
 
(1742) Pastore S., Mancini M., Faure F., Sechi G.R., Alderighi M., Casini F., Velazco R., D'Angelo S., Proposal for a radiation test of Virtex-based ALUs, Proceedings of the 7th European Conference on Radiation and its Effects on Components and Systems RADECS 2003, 2003
 
(1743) Mancini M., Faure F., Sechi G.R., Pastore S., Velazco R., D'Angelo S., Casini F., Alderighi M., Radiation test methodology for SRAM-based FPGAs by using THESIC+, Proceedings 9th IEEE International On Line Testing Symposium. IOLTS 2003, 2003
 
(1744) Nicolaidis M., Reliability threats in VDSM-shortcomings in conventional test and fault tolerance alternatives, Proceedings. International Test Conference 2003 IEEE Cat. No.03CH37494, 2003
 
(1745) Yoo S., Cho Y., Lee G., Choi K., Zergainoh N.-E., Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design, Embedded Software for SoC, Kluwer Academic Publishers, 125-136, 2003
 
(1746) Choi K., Cho Y., Zergainoh N.-E., Yoo S., Lee G., Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design, Design, Automation and Test in Europe (DATE'03), Munich, Germany, March 3-7, 2003, 2003
 
(1747) Borrione D., Toma D., SHA formalization, International Workshop on the ACL2 Theorem Proverand Its Applications (ACL2'03) Boulder, USA, July 13-14, 2003
 
(1748) Toma D., Borrione D., SHA Formalization, ISRN: TIMA-RR--03/10-06--FR, 2003
 
(1749) Velazco R., Savaria B.Y., Nicolescu B., SIED: software implemented error detection, Proceedings. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003
 
(1750) Nicolaidis M., Anghel L., Alexandrescu D., Simulating Single Event Transients in VDSM ICs for Ground Level, ISRN: TIMA-RR--03/08-05--FR, 2003
 
(1751) Velazco R., Faure F., Single event upsets on a read only memory based complex programmable logic device, Proceedings of the 7th European Conference on Radiation and its Effects on Components and Systems RADECS 2003 , 2003
 
(1752) Baghdadi A., Sasongko A, Jerraya A. A., Rousseau F., SoC validation through prototyping on ARM integrator platform , ARM Information Quarterly Journal, Vol.2, page: , 2003
 
(1753) Toma D., Al Sammane G., Specification of VHDL List Intermediate Format, ISRN: TIMA-RR--03/05-02--FR, 2003
 
(1754) Sicard G., Renaudin M., Rigaud J.B., Maurine P., Static Implementation of QDI asynchronous primitives, 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'03), Torino, Italy, September 10-12, 2003
 
(1755) Borrione D., Dumitrescu E., Symbolic simulation as a simplifying strategy for SoC verification, Proceedings 3rd IEEE International Workshop on System on Chip for Real Time Applications., 2003
 
(1756) Renaudin M., Sicard G., Bouesse G.F., Rigaud J.B., Maurine P., TAL : une bibliothèque de cellules pour le design de circuits asynchrones QDI, 4èmes journées d'études Faible Tension, Faible Consommation (FTFC’03), Paris, France,15-16 May , 2003
 
(1757) Jerraya A. A., Sasongko A, Baghdadi A., Rousseau F., Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform, Design Automation for Embedded Systems, Volume 8, Numbers 2-3, June 2003, page: 155-171, 2003
 
(1758) Nicolaidis M., Une Philosophie Numérique de l’Univers, ISRN: TIMA-RR--03/04-02--FR, 2003
 
(1759) Antoni L., Feher B., Leveugle R., Using run-time reconfiguration for fault injection applications, IEEE Transactions on Instrumentation and Measurement, Oct. ; 52(5), page: 1468-73, 2003
 
(1760) Anghel L., Velazco R., Saleh S., Validation of an approach dealing with processor obsolescence, 18th International Symposium on Defect and Fault Tolerance for VLSI Systems (DFT'03), Cambridge, MA, USA, November 3-5, 2003
 
(1761) Sirianni A., Mounier L., Boubekeur M., Borrione D., Renaudin M., Validation of asynchronous circuit specifications using IF/CADP, 12th IFIP International Conference on Very Large Scale Integration (VLSI’03), Darmstadt, Germany, December 1-3, 2003
 
(1762) Borrione D., Schmaltz J., Verification of a parameterized bus architecture using ACL2, ISRN: TIMA--RR-03/10-03--FR, 2003
 
(1763) Borrione D., Schmaltz J., Verification of a parameterized bus architecture using ACL2, International Workshop on the ACL2 Theorem Proverand Its Applications (ACL2'03) Boulder, USA, July 13-14, 2003
 
(1764) Lasance C., Courtois B., Szekely V., Rencz M., 8th International Workshop on THERmal Investigations of ICs and Systems (THERMINIC 2002), Madrid, Spain, October 1-4, 2002, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, , 2002
 
(1765) Renaudin M., Allier E., Fesquet L., Sicard G., A 6-bit Low-Power Asynchronous Analog-to-Digital Converter, ISRN: TIMA-RR--02/03-06--FR, 2002
 
(1766) Herve C., Torki K., A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors, Nuclear Instruments and Methods in Physics Research A, 481(1-3), page: 566-74, 2002
 
(1767) Courtois B., Torki K., Delori H., Charlot B., Paillotin J.-F., Access to microsystem technology: the CMP services solution, 2002 23rd International Conference on Microelectronics. Proceedings Cat. No.02TH8595, 2002
 
(1768) Courtois B., Galy N., Parrain F., Charlot B., A CMOS compatible micromachined tactile fingerprint sensor, Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP'02), Cannes-Mandelieu, France, 6-8 May 2002, 2002
 
(1769) Courtois B., Galilee B., Galy N., Parrain F., A CMOS Compatible Micromachined Tactile Fingerprint Sensor, ISRN: TIMA--RR-02/02/2--FR, 2002
 
(1770) Renaudin M., Panyasak D., Sicard G., A current shaping methodology for low EMI asynchronous circuits, 3rd International Workshop on Electromagnetic Compatibility of Integrated design (EMC Compo’02), Toulouse, France, November 14-15, 2002, 2002
 
(1771) Ostier P., Georgelin P., Borrione D., A framework for VHDL combining theorem proving and symbolic simulation, Third International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'02), Grenoble, France, 6-14 April 2002, 2002
 
(1772) Roux S., Algorithm and architecture for embedded multimedia system, These de Doctorat, 2002
 
(1773) Galilee B., Algorithm-architecture study for multimedia handset: image segmentation thanks to an asynchronous processors array, These de Doctorat, 2002
 
(1774) Galilee B., Coulon P.Y., Renaudin M., Mamalet F., Algorithme-Architecture asynchrone massivement parallèle de ligne de partage des eaux, ISRN: TIMA-RR--02/03-05--FR, 2002
 
(1775) Courtois B., Rencz M., Szekely V., Poppe A., An algorithm for the direct co-simulation of dynamic compact models of packages with the detailed thermal models of boards, Proceedings 4th Electronics Packaging Technology Conference EPTC 2002 Cat. No.02EX566, 2002
 
(1776) Szekely V., Courtois B., Rencz M., An algorithm for the inclusion of RC compact models of packages into board level thermal simulation tools, International Conference on Computational Nanoscience and Nanotechnology - Fifth International Conference on Modeling and Simulation of Microsystems (ICCN-MSM'02), San Juan, Puerto Rico, USA, April 22-25, 2002, 2002
 
(1777) Alacoque L., Analog-Digital Level Locked Loop, These de Doctorat, 2002
 
(1778) Courtois B., Analog Integrated Circuits and Signal Processing Foreword, Analog Integrated Circuits and Signal Processing, Volume 32, Number 1, page: 5-5, 2002
 
(1779) Velazco R., Nicolescu B., Corominas A., An automated technique to provide software applications with SEU detection capabilities: basic principles and preliminary results, Radiation and its effects on Components and Systems Workshop (RADECS'02), Padova, Italy, September 19-20, 2002, 2002
 
(1780) Rolindez L., Mir S., Domingues C., Rufer L., An implementation of memory-based on-chip analogue test signal generation, ISRN: TIMA-RR--02/11-02--FR, 2002
 
(1781) Martinez S., Nicolescu G., Kriaa L., Jerraya A. A., Charlot B., Yoo S., Youssef W., Application of multi-domain and multi-language cosimulation to an optical MEM switch design, Proceedings of ASP DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, 2002
 
(1782) Cucu C., Courtois B., Ciontu F., Application-specific architecture for quantum cellular automata, Proceedings of the 2002 2nd IEEE Conference on Nanotechnology Cat. No.02TH8630, 2002
 
(1783) Gauthier L., Paviot Y., Jerraya A. A., Nicolescu G., Lyonnard D., Cesario W., Baghdadi A., Application-specific multiprocessor systems-on-chip, Microelectronics journal, Volume 33, Issue 11 , November 2002, page: 891-898, 2002
 
(1784) Baghdadi A., Jerraya A. A., Cesario W., Lyonnard D., Paviot Y., Yoo S., Nicolescu B., Gauthier L., Application-Specific Multiprocessor Systems-on-Chip, ISRN: TIMA-RR--02/11-03--FR, 2002
 
(1785) Cucu C., Ciontu F., Courtois B., Application-Specific Regular Architecture for Quantum Cellular Automata, ISRN: TIMA--RR-02/06-01--FR, 2002
 
(1786) Dumitrescu E., A practical approach to the formal verification of SoCs with symbolic model checking, International Workshop on System On Chip for real-time applications (IWSOC'02), Banff, Canada, July 5-7, 2002, 2002
 
(1787) Dumitrescu E., A Practical Approach to the Formal Verification of SoC’s with Symbolic Model-Checking, ISRN: TIMA--RR-02/02/4--FR, 2002
 
(1788) Baghdadi A., Zergainoh N.-E., Cesario W., Jerraya A. A., Architecture design space exploration for hardware/software codesign: system-level performance estimation , Technique et Science Informatiques (TSI), Vol.21, page: , 2002
 
(1789) Meftali S., Architectures exploration and memory allocation/assignment in multiprocessor SoC, These de Doctorat, 2002
 
(1790) Nicolescu B., A Software Approach for the Detection of Transient Errors Occurring in Processor-based Digital Architectures: Principles and Experimental Results, These de Doctorat, 2002
 
(1791) Velazco R., Sonza Reorda M., Rebaudengo M., Nicolescu B., Violante M., A software fault tolerance method for safety-critical systems: effectiveness and drawbacks, Proceedings 15th Symposium on Integrated Circuits and Systems Design, 2002
 
(1792) Renaudin M., Asynchronous System Design, ISRN: TIMA--RR-02/03-01--FR, 2002
 
(1793) Jerraya A. A., Rousseau F., Gharsalli F., Meftali S., Automatic code-transformation and architecture refinement for application-specific multiprocessor SoCs with shared memory, SOC Design Methodologies. IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems on Chip VLSI SOC'01, 2002
 
(1794) Meftali S., Rousseau F., Gharsalli F., Jerraya A. A., Automatic code-transformations, and architecture rafinement for application-specific multiprocessor , Kluwer Academic Publishers, 193-204, 2002
 
(1795) Jerraya A. A., Gharsalli F., Rousseau F., Meftali S., Automatic generation of embedded memory wrapper for multiprocessor SoC, Proceedings-2002-Design-Automation-Conference, 2002
 
(1796) Jerraya A. A., Meftali S., Rousseau F., Gharsalli F., Automatic Generation of Embedded Memory Wrapper for Multiprocessor Soc, ISRN: TIMA-RR--02/03-2--FR, 2002
 
(1797) Jerraya A. A., Gauthier L., Yoo S., Nicolescu G., Automatic generation of fast timed simulation models for operating systems in SoC design, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2002
 
(1798) Leveugle R., Automatic modifications of high level VHDL descriptions for fault detection or tolerance, Proceedings-2002-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition. 2002:, 2002
 
(1799) Domingues C., Rufer L., Mir S., Behavioral modelling and simulation of a MUT-based pulso-echo system, 2nd International Workshop on Microfabricated Ultrasonic Transducers, Besançon, France, June 2002 , 2002
 
(1800) Domingues C., Rufer L., Mir S., Behavioural modelling and simulation of a MEMS-based ultrasonic pulse-echo system, Proceedings of the SPIE The International Society for Optical Engineering, 2002
 
(1801) Rufer L., Domingues C., Mir S., Behavioural modelling and simulation of a MEMS-based ultrasonic pulse-echo system , ISRN: TIMA--RR-02/02/3--FR, 2002
 
(1802) Velazco R., Pontarelli S., Leandri A., Ottavi M., Cardarilli G.C., Kaddour F., Bit flip injection in processor-based architectures: a case study, Proceedings of the Eighth IEEE International On Line Testing Workshop IOLTW 2002, 2002
 
(1803) Alacoque L., Nicolle S., Abouchi N., Renaudin M., Boucle analogique-numérique verrouillée sur l'amplitude, application à la conversion analogique-numérique pour la basse consommation, 3ème Colloque sur le Traitement Analogique de l'Information, du Signal et ses Applications (TAISA'02), ENST, Paris, France, September 12 -13, 2002, 2002
 
(1804) De Labacherie M., Coudevylle J.-R., Majjad H., Usuda T., Basrour S., Characteristics of torsional resonator with two degrees of freedom fabricated by UV-LIGA, Proceedings of the SPIE The International Society for Optical Engineering, 2002
 
(1805) Charlot B., Parrain F., Galy N., Courtois B., CMOS-compatible micromachined tactile fingerprint sensor, Proceedings of SPIE Design, Test, Integration, and Packaging of MEMS/MOEMS, 2002
 
(1806) Torki K., CMP service for the access to advanced technologies, Invited paper at Conference IT21, Sendai, Japan, October 11, 2002, 2002
 
(1807) Cesario W., Zergainoh N.-E., Baghdadi A., Jerraya A. A., Combining a performance estimation methodology with a hardware/software codesign flow supporting multiprocessor systems, IEEE Transactions on Software Engineering, Volume 28 (September 2002), page: 822 - 831, 2002
 
(1808) Wagner F.R., Jerraya A. A., Cesario W., Samet F., Dziri A., Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL, ISRN: TIMA-RR--02/11-01--FR, 2002
 
(1809) Zitouni A., Abid M., Tourki R., Torki K., Communication synthesis techniques for multiprocessor systems, International Journal of Electronics, Jan. ; 89(1), page: 55-76, 2002
 
(1810) Diaz-Nava M., Jerraya A. A., Baghdadi A., Cesario W., Gauthier L., Lyonnard D., Yoo S., Paviot Y., Nicolescu G., Component-based design approach for multicore SoCs, Proceedings-2002-Design-Automation-Conference, 2002
 
(1811) Jerraya A. A., Conception de haut niveau des systèmes monopuces (Traité EGEM, Série électronique et micro-électronique), Hermès, 224p. 16x24, 2002
 
(1812) Mir S., Conception de microsystèmes sur silicium (Traité EGEM, série Electronique et micro-électronique), Hermès, 220p. 16x24, 2002
 
(1813) Jerraya A. A., Conception logique et physique des systèmes monopuces (Traité EGEM Série électronique et micro-électronique), Hermès, 246p. 16x24, 2002
 
(1814) Zaidan N., Conception of a secure interface, These de Doctorat, 2002
 
(1815) Sonza Reorda M., Rebaudengo M., Violante M., Velazco R., Nicolescu B., Coping with SEUs/SETs in Microprocessors by Means of Low-cost Solutions: a Comparative Study and Experimental Results, ISRN: TIMA--RR-02/04/02--FR, 2002
 
(1816) Rebaudengo M., Velazco R., Nicolescu B., Violante M., Reorda M.S., Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study, IEEE Transactions on Nuclear Science, Volume 49, Part 3, June 2002, page: 1491 - 1495, 2002
 
(1817) Dutt N., Nicolau A., Rousseau F., Mishra P., Coprocessor Codesign for Programmable Architectures, ISRN: TIMA--RR-02/04-04--FR, 2002
 
(1818) Courtois B., Szekely V., Rencz M., Poppe A., Co-simulation of dynamic compact models of packages with the detailed models of printed circuit boards, Twenty Seventh Annual IEEE/CPMT/SEMI International Electronics Manufacturing Technology Symposium Cat. No.02CH37299, 2002
 
(1819) Jerraya A. A., Gauthier L., Lyonnard D., Yoo S., Coste P., Nicolescu G., Svarstad G., Cesario W., Desiderata for the specification and design of electronic systems, Technique et Science Informatiques (TSI), 21(3), page: 291-314, 2002
 
(1820) Courtois B., Torki K., Palan B., Husak M., Design and characterization of levitated suspended RF inductors, Proceedings of the SPIE The International Society for Optical Engineering., 2002
 
(1821) Palan B., Design of low noise pH-ISFET microsensors and integrated suspended inductors with increased quality, These de Doctorat, 2002
 
(1822) Martinez S., Design of silicon micromachined cross-connects for all-optical networks, These de Doctorat, 2002
 
(1823) Karam J.M., Courtois B., Markus K., Mukherjee T., Michel B., Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP 2002), May 6-8, 2002, Cannes, France, SPIE Int. Soc. Opt. Eng, , 2002
 
(1824) Mir S., Dispositifs et physique des microsystèmes sur silicium (Traité EGEM, série Electronique et micro-électronique), Hermès, 218p. 16x24, 2002
 
(1825) Fesquet L., Essalhiene M., Renaudin M., Dynamic voltage scheduling for real time asynchronous systems, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 12th International Workshop, PATMOS 2002. Proceedings Lecture Notes in Computer Science , 2002
 
(1826) Ballandras S., Basrour S., Daniau W., Robert L., Pastureaud T., Laude V., Electroacoustic interaction between SAW and vibration modes of high-aspect-ratio electrodes built using LIGA-UV techniques on singly rotated lithium niobate wafers, 2001-Microelectromechanical-Systems-Conference, 2002
 
(1827) Nicolaidis M., Dupont E., Embedded robustness IPs, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2002
 
(1828) Rohr P., Nicolaidis M., Dupont E., Embedded robustness IPs for transient-error-free ICs, IEEE Design and Test of Computers, May-June ; 19(3), page: 56-70, 2002
 
(1829) Kaddour F., De-Mingo J.R., Rodriguez S., Rezgui S., Velazco R., Error Rate Estimation for a Flight Application Using the CEU Fault Injection Approach, Proceedings of the Eighth IEEE International On Line Testing Workshop IOLTW 2002, 2002
 
(1830) Renaudin M., Rigaud J.B., Etude de l'art sur la conception des circuits asynchrones, perspectives pour l'intégration des systèmes complexes, ISRN: TIMA-RR--02/12-02--FR, 2002
 
(1831) Hadjiat K., Leveugle R., Évaluation prédictive de la sûreté de fonctionnement d'un circuit intégré, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM), Grenoble, France, April 23-25, 2002, 2002
 
(1832) Leveugle R., Hadjiat K., Expériences d'injection de fautes multi-niveaux dans des descriptions VHDL, Colloque CAO de circuits et systèmes intégrés, Paris, France, May 15-17, 2002, 2002
 
(1833) Violante M., Rebaudengo M., Cheynet P., Nicolescu B., Velazco R., Sonza Reorda M., Experimentally Evaluating an Automatic Approach for Generating Safety-Critical Software with Respect to Transient Errors, ISRN: TIMA--RR-02/02/5--FR, 2002
 
(1834) Baghdadi A., Exploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC, These de Doctorat, 2002
 
(1835) Jerraya A. A., Baghdadi A., Zergainoh N.-E., Exploration et conception systématique d’architectures multiprocesseurs monopuces dédiées à des applications spécifiques, 3ème Colloque CAO de circuits et systèmes intégrés, Paris, France, May 15-17, 2002
 
(1836) Parrain F., Fingerprint sensor using piezoresistive microstructures, These de Doctorat, 2002
 
(1837) Courtois B., Foreword of Special Issue on DTIP 2001 (The Symposium on Design, Test, Integration of MEMS/MOEMS held in Cannes-Mandelieu, April 25-27, 2001), Analog Integrated Circuits and Signal Processing, Vol. 32, page: , 2002
 
(1838) Charlot B., Mir S., Courtois B., Parrain F., Generation of Electrically Induced Stimuli for MEMS self-test, ISRN: TIMA--RR-02/02/1--FR, 2002
 
(1839) Renaudin M., Fesquet L., Quartana J., Rigaud J.B., High-level modeling and design of asynchronous arbiters for on-chip communication systems, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition., 2002
 
(1840) Rigaud J.B., Fesquet L., Renaudin M., Quartana J., High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems, ISRN: TIMA-RR--02/03-3--FR, 2002
 
(1841) Quartana J., Fesquet L., Rigaud J.B., Renaudin M., High-Level Modeling and Design of Asynchronous Arbiters. Poster presentation, ISRN: TIMA-RR--02/03-4--FR, 2002
 
(1842) Naal M. A., High level synthesis for on-line testability, These de Doctorat, 2002
 
(1843) Jerraya A. A., Nicolescu G., Gauthier L., Lyonnard D., Yoo S., Cesario W., Baghdadi A., Paviot Y., Bianchi R.A., HW/SW interfaces design of a VDSL modem using automatic refinement of a virtual architecture specification into a multiprocessor SoC: a case study , Design, Automation and Test in Europe (DATE'02), Paris, France, March 4-8, 2002, 2002
 
(1844) Ciontu F., Torki K., IC thermal map from digital and thermal simulations, 8th International Workshop on THERmal Investigations of ICs and Systems (THERMINIC'02), Madrid, Spain, 1-4 October 2002, 2002
 
(1845) Rolland R., Renaudin M., Fesquet L., Rigaud J.B., Thai-Ho Quoc, Implementing asynchronous circuits on LUT based FPGAs, Field Programmable Logic and Applications. Reconfigurable Computing Is Going Mainstream. 12th International Conference, FPL 2002. Proceedings Lecture Notes in Computer Science Vol.2438., 2002
 
(1846) Vidal J., Deharbe D., Borrione D., Improving static ordering of BDDs for reachability analysis, 11th IEEE/ACM International Workshop on Logic & Synthesis (IWLS'02), New Orleans, USA, June 4-7, 2002, 2002
 
(1847) Courtois B., Poppe A., Szekely V., Rencz M., Inclusion of RC compact models of packages into board level thermal simulation tools, Eighteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium. Proceedings 2002 Cat.No.02CH37311, 2002
 
(1848) Ciontu F., Courtois B., Roman C., Information coding and intramolecular integration of logic functionality, ISRN: TIMA- - RR--02/12-01- - FR, 2002
 
(1849) Velazco R., Corominas A., Ferraya P.A., Injecting bit flip faults by means of a purely software approach : a case studied, The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’02), Vancouver, Canada, November 6-8, 2002, 2002
 
(1850) Ferraya P.A., Corominas A., Velazco R., Injecting bit flip faults by means of a purely software approach: a case studied, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002., 2002
 
(1851) Carro L., Reis R., Velazco R., Injecting multiple upsets a SEU tolerant 8051 micro-controller, 8th IEEE International On-Line Testing Workshop (IOLT'02), Bendor, France, July 8-10, 2002, 2002
 
(1852) Reis R., Lima Kastensmidt F., Carro L., Velazco R., Injecting multiple upsets in a SEU tolerant 8051 micro-controller, Proceedings of the Eighth IEEE International On Line Testing Workshop IOLTW 2002., 2002
 
(1853) Calvo O., Velazco R., Marques C.A., Ferraya P.A., Injecting single event upsets in a digital signal processor by means of direct memory access requests: a new method for generating bit flips, RADECS-2001, 2002
 
(1854) Borrione D., Dumitrescu E., Sirianni A., Rigaud J.B., Boubekeur M., Renaudin M., Introducing formal validation in an asynchronous circuit design flow, The Fourth International Workshop on Designing Correct Circuits, Grenoble, France, April 6-7, 2002, 2002
 
(1855) Mir S., Martinez S., Introduction aux microsystèmes sur silicium, Conception de microsystèmes sur silicium (Traité EGEM, série Electronique et micro-électronique), Hermès, chapitre 1: 19-38, 2002
 
(1856) Nicolaidis M., IP for embedded robustness, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2002
 
(1857) Charlot B., Mir S., Martinez S., La CAO des microsystèmes, Conception de microsystèmes sur silicium, Hermès, 129-176 : chapitre 5, 2002
 
(1858) Cesario W., Jerraya A. A., La conception comportementale, Conception de haut niveau des systèmes monopuces (Traité EGEM, Série électronique et micro-électronique), Hermès, 65-108 ; chapitre 3, 2002
 
(1859) Renaudin M., La conception de systèmes asynchrones, Conception logique et physique des systèmes monopuces (Traité EGEM Série électronique et micro-électronique), Hermès, chapitre 5 : 143-220, 2002
 
(1860) Renaudin M., La conception logique, Conception logique et physique des systèmes monopuces, Hermès, 27-64 ; chapitre 2, 2002
 
(1861) Torki K., La conception physique : placement, routage et vérification du layout, Conception logique et physique des systèmes monopuces (Traité EGEM Série électronique et micro-électronique), Hermès, chapitre 3 : 65-106, 2002
 
(1862) Rousseau F., La conception système et le découpage logiciel/matériel, Conception de haut niveau des systèmes monopuces (Traité EGEM, Série électronique et micro-électronique), Hermès, chapitre 4: 109-138, 2002
 
(1863) Rufer L., La modélisation des microsystèmes électromécaniques, Conception de microsystèmes sur silicium, Hermès, chapitre 4: 101-128, 2002
 
(1864) Borrione D., La simulation et les méthodes de vérification formelle, Conception de haut niveau des systèmes monopuces (Traité EGEM, Série électronique et micro-électronique), Hermès, chapitre 5: 139-174, 2002
 
(1865) Parrain F., Les capteurs magnétiques en technologies microsystèmes, Dispositifs et physique des microsystèmes sur silicium (Traité EGEM, série Electronique et micro-électronique), Hermès, 175-198 : chapitre 5, 2002
 
(1866) Charlot B., Les domaines d'application des microsystèmes, Conception de microsystèmes sur silicium (Traité EGEM, série Electronique et micro-électronique), Hermès, 39-68 : chapitre 2, 2002
 
(1867) Parrain F., Mir S., Les interfaces microélectroniques, Conception de microsystèmes sur silicium (Traité EGEM, série Electronique et micro-électronique), Hermès, chapitre 6 : 177-215, 2002
 
(1868) Rufer L., Les microsystèmes électromécaniques, Dispositifs et physique des microsystèmes sur silicium, Hermès, chapitre 1 : 19-64, 2002
 
(1869) Charlot B., Parrain F., Mir S., Les microsystèmes thermiques, Dispositifs et physique des microsystèmes sur silicium (Traité EGEM, série Electronique et micro-électronique), Hermès, chapitre 2: 65-104, 2002
 
(1870) Martinez S., Goy J., Les MOEMS et les imageurs CMOS, Dispositifs et physique des microsystèmes sur silicium, Hermès, chapitre 4: 133-174, 2002
 
(1871) Charlot B., Les technologies de fabrication des microsystèmes, Conception de microsystèmes sur silicium, Hermès, chapitre 3: 69-100, 2002
 
(1872) Rigaud J.B., Libraries specification for the synthesis of asynchronous circuits, These de Doctorat, 2002
 
(1873) Renaudin M., Fesquet L., Allier E., Sicard G., Low-power asynchronous A/D conversion, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 12th International Workshop, PATMOS 2002. Proceedings Lecture Notes in Computer Science, 2002
 
(1874) Szekely V., Rencz M., Courtois B., Farkas G., Measuring interface thermal resistance values by transient testing, ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems Cat. No.02CH37258, 2002
 
(1875) Rezgui S., Velazco R., Method for error injection by interruptions, FR2819603, 2002
 
(1876) Zergainoh N.-E., Méthodologie et modèles pour la conception digitale, , Hermès, , 2002
 
(1877) Zergainoh N.-E., Méthodologie et modèles pour la conception digitale, Conception de haut niveau des systèmes monopuces, Hermès, chapitre 1 : 19-64, 2002
 
(1878) Basrour S., Microbobines pour MAGMAS, Micro-actionneurs électromagnétiques MAGMAS, Hermès, Vol.1, 2002
 
(1879) Fesquet L., Quartana J., Renaudin M., Rigaud J.B., Modeling and design of asynchronous priority arbiters for on-chip, SOC Design Methodologies Series: IFIP International Federation for Information Processing, Kluwer Academic Publishers, 313-324, 2002
 
(1880) Quartana J., Rigaud J.B., Renaudin M., Fesquet L., Modeling and design of asynchronous priority arbiters for on-chip communication systems, SOC Design Methodologies. IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems on Chip VLSI SOC'01, 2002
 
(1881) Mir S., Domingues C., Rufer L., Modélisation et simulation d'un microsystème ultrasonore pour une application pulse-echo , 5ème Journées Nationales du Réseau Doctoral de Microélectronique,Grenoble, France, April 2002, 2002
 
(1882) Leveugle R., Hadjiat K., Multi-level fault injection experiments based on VHDL descriptions: a case study, Proceedings of the Eighth IEEE International On Line Testing Workshop IOLTW 2002, 2002
 
(1883) Jerraya A. A., Cesario W., Lyonnard D., Nicolescu G., Paviot Y., Yoo S., Gauthier L., Diaz-Nava M., Multiprocessor SoC platforms: a component-based design approach, IEEE Design and Test of Computers, Nov.-Dec. 2002; Volume: 19 , Issue: 6, page: 52 - 63, 2002
 
(1884) Nicolaidis M., Alexandrescu D., Anghel L., New methods for evaluating the impact of single event transients in VDSM ICs, Proceedings 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002, 2002
 
(1885) Roman C., Diedrich C., Domingues C., Mir S., On-chip test signal generation for acoustic and ultrasound microelectronic interfaces, 8th IEEE International Mixed-Signal Testing Workshop (IMSTW'02),Montreux, Switzerland, June 2002, 2002
 
(1886) Roman C., Diedrich C., Domingues C., Mir S., On-chip test signal generation for acoustic and ultrasound microelectronic interfaces, ISRN: TIMA-RR--02/09-01--FR, 2002
 
(1887) Rezgui S., Lima Kastensmidt F., Lima Kastensmidt F., Velazco R., On the use of VHDL simulation and emulation to derive error rates, RADECS-2001.-2001-, 2002
 
(1888) Noguet D., Parallel architectures for image processing, These de Doctorat, 2002
 
(1889) Mir S., Charlot B., Perspectives des microsystèmes sur silicium, Dispositifs et physique des microsystèmes sur silicium, Hermès, 199-214 : chapitre 6, 2002
 
(1890) Velazco R., Rezgui S., Ecoffet R., Predicting Error Rate for Microprocessor-Based Digital Architectures throughC.E.U. (Code Emulating Upsets) Injection, ISRN: TIMA--RR-02/02/6--FR, 2002
 
(1891) Corominas A., Velazco R., Ecoffet R., Predicting error rates provoked by radiation in digital architectures: methods and tools, 5th Workshop on Radiation Effects on Semiconductor Devices for Space Application (RESEDA'02), Takasaki, Japan, 8-10 October 2002, 2002
 
(1892) Abramovici M., Nicolaidis M., Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), Isle of Bendor, France, July 8-10, 2002, IEEE Computer Society, 270 pages, 2002
 
(1893) Wik T., Zorian Y., Courtois B., Proceedings of the International Workshop on Memory Technology, Design and Testing (MTDT 2002) Isle of Bendor, France, July 10-12, 2002, IEEE Computer Society, , 2002
 
(1894) Courtois B., Lasance C., Rencz M., Szekely V., Proceedings on 8th International Workshop on THERMal INvestigations of ICs and Systems (THERMINIC 2002), 1-4 October 2002, Madrid, Spain, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 321 pages, 2002
 
(1895) Markus K., Courtois B., Proceedings on Symposium on Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP'02), Cannes-Mandelieu, France, May 5-8, 2002, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 830 pages, 2002
 
(1896) Bouesse G.F., Renaudin M., Fesquet L., QDI Circuits to Improve Smartcard Security, ISRN: TIMA-RR--02/03/10--FR, 2002
 
(1897) Galilee B., Mamalet F., Coulon P.Y., Renaudin M., Réseau calculant asynchrone dédié à la segmentation d'images, Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM'02), Grenoble, France, April 23-25, 2002, 2002
 
(1898) Nicolaidis M., Dupont E., Robustness IPs for reliability and security of SoCs, Proceedings International Test Conference 2002 Cat. No.02CH37382, 2002
 
(1899) Bourdarie S., Duzellier S., Nicolescu B., Velazco R., Ecoffet R., SEE in-flight data for two static 32KB memories on high earth orbit, 2002-IEEE-Radiation-Effects-Data-Workshop, 2002
 
(1900) Renaudin M., Panyasak D., Sicard G., Shaping Current Profile of Asynchronous Circuits, ISRN: TIMA-RR-02/03/09--FR, 2002
 
(1901) Alexandrescu D., Nicolaidis M., Anghel L., Simulating single event transients in DVSM ICs for ground level radiation, 3rd IEEE Latin American Test Workshop (LATW'02), Montevideo, Uruguay, February 10-13, 2002, 2002
 
(1902) Anghel L., Nicolaidis M., Alexandrescu D., Simulating Single Event Transients in VDSM ICs for Ground Level Radiation, ISRN: TIMA--RR-02/01/2--FR, 2002
 
(1903) Klim H., Bederr H., Mir S., Kerkhoff H., Blanton R.D., SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow?, 20th IEEE VLSI Test Symposium, 2002
 
(1904) Nicolescu G., Specification and validation for heterogeneous embedded systems, These de Doctorat, 2002
 
(1905) Hessel F., Jerraya A. A., Spécification et conception des systèmes hétérogènes, Conception de haut niveau des systèmes monopuces, Hermès, 175-200 ; chapitre 6, 2002
 
(1906) Goy J., Study, conception and fabrication of an APS image sensor in standard CMOS technology for low light level applications such as star trackers, These de Doctorat, 2002
 
(1907) Courtois B., Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2001), 25-27 April 2001-Cannes-Mandelieu, , Springer , Volume 32, Number 1, 101 pages, 2002
 
(1908) Renaudin M., Dinh Duc Anh Vu, Fesquet L., Synthesis of QDI asynchronous circuits from DTL-style petri-net, 11th IEEE/ACM International Workshop on Logic & Synthesis (IWLS'02), New Orleans, Louisiana,USA, June 4-7, 2002, 2002
 
(1909) Kriaa L., Youssef W., Martinez J., Kurzweg T., Levitan S.P., Martinez S., Nicolescu G., Courtois B., Jerraya A. A., SystemC-based cosimulation for global validation of MOEMS, Proceedings of the SPIE The International Society for Optical Engineering, 2002
 
(1910) Jerraya A. A., Kurzweg T., Kriaa L., Martinez S., Martinez J., Levitan S.P., Courtois B., Youssef W., Nicolescu G., SystemC-based cosimulation for global validation of MOEMS , Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP'02), Cannes-Mandelieu, France, May 5-8, 2002, 2002
 
(1911) Courtois B., Kriaa L., Nicolescu G., Levitan S.P., Kurzweg T., Jerraya A. A., Martinez J., Martinez S., Youssef W., SystemC-Based Cosimulation for Global Validation of MOEMS, ISRN: TIMA--RR-02/01-1--FR, 2002
 
(1912) Fragoso J., Rigaud J.B., Sirianni A., Renaudin M., Dinh Duc Anh Vu, Rezzag A., TAST CAD Tools, ISRN: TIMA--RR-02/04/01--FR, 2002
 
(1913) Fesquet L., Sirianni A., Rigaud J.B., Renaudin M., Fragoso J., Rezzag A., Dinh Duc Anh Vu, TAST: TIMA Asynchronous Synthesis Tools, ISRN: TIMA-RR--02/03-08--FR, 2002
 
(1914) Leveugle R., Test des circuits intégrés numériques - Conception orientée testabilité, Techniques de l'Ingénieur, article E 2 461, , , 2002
 
(1915) Leveugle R., Test des circuits intégrés numériques - Notions de base. Génération de vecteurs, Techniques de l'Ingénieur, article E 2 460, , , 2002
 
(1916) Leveugle R., Test des circuits intégrés numériques - Pour en savoir plus, Techniques de l'Ingénieur, article E 2 462, , , 2002
 
(1917) Paillotin J.-F., Torki K., Delori H., Charlot B., Courtois B., The CMP Service, 4th European Workshop on Microelectronics Education (EWME'02), Parador de Baiona, Spain, May 23-24, 2002, 2002
 
(1918) Szekely V., Rencz M., Courtois B., Kohari Z., Thermal evaluation and modelling of the SIP9 and SP10 MEMS packages , Eight Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM'02), Marina San Diego, California, USA, May 29 - June 1, 2002, 2002
 
(1919) Yoo S., Bacivarov I., Jerraya A. A., Timed HW-SW cosimulation using native execution of OS and application SW, Proceedings Seventh IEEE International High Level Design Validation and Test Workshop, 2002
 
(1920) Boutobza S., Tools for Memory BIST/BISR generation, These de Doctorat, 2002
 
(1921) Fesquet L., Essalhiene M., Renaudin M., Towards a Low Power RTOS for Asynchronous Processors, ISRN: TIMA-RR--02/03/07--FR, 2002
 
(1922) Rousseau F., Jerraya A. A., Gharsalli F., Lyonnard D., Unifying memory and processor wrapper architecture in multiprocessor SoC design, 15th-International-Symposium-on-System-Synthesis-, 2002
 
(1923) Jerraya A. A., Rousseau F., Gharsalli F., Meftali S., Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design, ISRN: TIMA--RR-02/04-03--FR, 2002
 
(1924) Simeu E., Naal M. A., Aktouf C., Rakotoar M., Using concurrent and semi-concurrent on-line testing during HLS: an adaptable approach, Proceedings of the Eighth IEEE International On Line Testing Workshop IOLTW 2002, 2002
 
(1925) Levy M., Amblard P., Lagnier F., Using formal tools to study complex circuits behaviour, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools., 2002
 
(1926) Leveugle R., Antoni L., Feher B., Using run-time reconfiguration for fault injection in hardware prototypes, Proceedings 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002, 2002
 
(1927) Ghenassia F., Jerraya A. A., Tambour L., Valentin T., Zergainoh N.-E., Urard P., Utilisation d'une méthode de correction de retards pour la vérification d'un assemblage de fonctions RTL par rapport à un assemblage de fonctions au niveau fonctionnel, 3ème Colloque CAO de circuits et systèmes intégrés, Paris, France, May 15-17, 2002
 
(1928) Nicolescu G., Bouchhima A., Yoo S., Jerraya A. A., Validation in a component-based design flow for multicore SoCs, 15th-International-Symposium-on-System-Synthesis-, 2002
 
(1929) Swift G., Rezgui S., Velazco R., Farmanesh F.F., Validation of an SEU simulation technique for a complex processor: PowerPC7400, IEEE Transactions on Nuclear Science, Volume: 49 , Part 1, page: 3156 - 3162, 2002
 
(1930) Coulon P.Y., Mamalet F., Renaudin M., Galilee B., Watershed parallel algorithm for asynchronous processors array, : Proceedings-2002-IEEE-International-Conference-on-Multimedia-and-Expo-(ICME), 2002
 
(1931) Faure F., Velazco R., A flexible platform for the functional validation of programmable circuits, ISRN: TIMA-RR--01/10-5--FR, 2001
 
(1932) Faure F., Velazco R., A flexible platform for the functional validation of programmable circuits, WRTLT Workshop (RTL ATPG and DFT Workshop) (WRTLT), Nara (Japan), 21-23 November 2001, 2001
 
(1933) Olmos S., Nicolescu B., Velazco R., Ecoffet R., Faure F., Dupont E., A flight experiment for the evaluation of hardware and software fault tolerance techniques, ISRN: TIMA--RR-01/10-8--FR, 2001
 
(1934) Ecoffet R., Nicolescu B., Dupont E., Velazco R., Olmos S., A flight experiment for the evaluation of hardware and software fault tolerance techniques , 52nd International Astronautical Congress (IAF'01), Toulouse, France, October 1-5, 2001, 2001
 
(1935) Jerraya A. A., Baghdadi A., Nicolescu G., Yoo S., Lyonnard D., A generic wrapper architecture for multi-processor SoC cosimulation and design, Ninth International Symposium on Hardware/Software Codesign. CODES 2001, 2001
 
(1936) Svarstad K., Jerraya A. A., Ben-Fredj N., Nicolescu G., A higher level system communication model for object-oriented specification and design of embedded systems, Proceedings of the ASP DAC 2001. Asia and South Pacific Design Automation Conference 2001v, 2001
 
(1937) Galilee B., Coulon P.Y., Renaudin M., Mamalet F., Algorithme-Architecture Parallèle Asynchrone pour la Segmentation d'Image par Ligne de Partage des Eaux, ISRN: TIMA-RR--01/05-01--FR, 2001
 
(1938) Leveugle R., A low-cost hardware approach to dependability validation of IPs, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001
 
(1939) Jerraya A. A., Nicolescu G., Svarstad K., A model for describing communication between aggregate objects in the specification and design of embedded systems, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001
 
(1940) Courtois B., Mir S., Lubaszewski M., Charlot B., An analog-based approach for MEMS testing, 2nd IEEE Latin-American Test Workshop (LATW 2001 ), Cancun, Mexico, February 11-14, 2001, 2001
 
(1941) Lyonnard D., Zergainoh N.-E., Baghdadi A., Jerraya A. A., An efficient architecture model for systematic design of application-specific multiprocessor SoC, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001
 
(1942) Vivet P., Renaudin M., Senn P., Bouvier J., Abrial A., A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller, IEEE Journal of Solid State Circuits, July ; 36(7), page: 1101-7, 2001
 
(1943) Meftali S., Rousseau F., Jerraya A. A., Gharsalli F., An optimal memory allocation for application-specific multiprocessor system-on-chip, International-Symposium-on-System-Synthesis-, 2001
 
(1944) Kriaa L., Youssef W., Yoo S., Charlot B., Jerraya A. A., Nicolescu G., Martinez S., Application of Multi-domain and Multi-language Cosimulation to an Optical MEM Switch Design, ISRN: TIMA-RR--01/09-1--FR, 2001
 
(1945) Lyonnard D., Cesario W., Jerraya A. A., Baghdadi A., Gauthier L., Paviot Y., Yoo S., Nicolescu G., Application-specific multiprocessor systems-on-chip, The Tenth Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI'01), Nara, Japan, October 18-19, 2001, 2001
 
(1946) Yoo S., Jerraya A. A., Gauthier L., Application-specific operating systems generation and targeting for embedded SoCs , The Tenth Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'01), October 18-19, 2001, 2001
 
(1947) Vivet P., A quasi-delay insensitive integrated circuit design methodology : application to the study and design of a 16-bit asynchronous RISC microprocessor, These de Doctorat, 2001
 
(1948) Nicolau A., Rousseau F., Dutt N., Mishra P., Architecture description language driven design space exploration in the presence of coprocessors, The Tenth Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'01), Nara, Japan, October 18-19, 2001, 2001
 
(1949) Nicolau A., Dutt N., Rousseau F., Mishra P., Architecture Description Language Driven Design Space Exploration in the Presence of Coprocessors, ISRN: TIMA--RR-01/12-1--FR, 2001
 
(1950) Simeu E., Abdelhay A., A robust fault detection scheme for concurrent testing of linear digital systems, Proceedings Seventh International On Line Testing Workshop, 2001
 
(1951) Rencz M., Benedek Zs., Poppe A., Courtois B., Kollar E., Mir S., Farkas G., Torki K., Szekely V., A scalable multi-functional thermal test chip family: design and evaluation , Journal of Electronic Packaging, Vol. 123, page: , 2001
 
(1952) Parrain F., Charlot B., Courtois B., Mir S., A self-testable CMOS thermopile-based infrared imager, Design, Test, Integration, and Packaging of MEMS/MOEMS, 2001
 
(1953) Ziade H., Velazco R., Rezgui S., Assessing the soft error rate of digital architectures devoted to operate in radiation environment: a case studied, IEEE Latin-American Test Workshop (LATW 2001 ), Cancun, Mexico, February 11-14, 2001, 2001
 
(1954) Valderrama C., Jerraya A. A., Ben Ismail T., Abid M., Vijayaraghavan V., Changuel A., A unified model for co-simulation and co-synthesis of mixed hardware/software systems, Readings in Hardware/Software Co-Design, Ed. by G. De Micheli, R. Ernst, and W. Wolf, Morgan Kaufmann Publishers, 579-583, 2001
 
(1955) Gharsalli F., Jerraya A. A., Meftali S., Rousseau F., Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory, ISRN: TIMA--RR-01/12-2--FR, 2001
 
(1956) Meftali S., Rousseau F., Jerraya A. A., Gharsalli F., Automatic code-transformations and architecture refinement, for application-specific , IFIP International Conference on Very Large Scale Integration - The Global System on Chip Design & CAD Conference (VLSI-SOC 2001), Montpellier, France, December 3-5 2001, 2001
 
(1957) Jerraya A. A., Gauthier L., Yoo S., Automatic generation and targeting of application-specific operating systems and embedded systems softwar, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov. 2001; Volume: 20, Issue: 11, page: 1293-301, 2001
 
(1958) Yoo S., Gauthier L., Jerraya A. A., Automatic generation and targeting of application specific operating systems and embedded systems software, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001
 
(1959) Yoo S., Jerraya A. A., Baghdadi A., Lyonnard D., Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip, Proceedings of the 38th Design Automation Conference, 2001
 
(1960) Baghdadi A., Lyonnard D., Yoo S., Jerraya A. A., Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip, ISRN: TIMA-RR--01/02-03--FR, 2001
 
(1961) Nicolescu G., Jerraya A. A., Yoo S., Gauthier L., Automatic Generation of Fast Timed Simulation Models for Operating Systems in Multiprocessor SoC Design, ISRN: TIMA--RR-01/11-2--FR, 2001
 
(1962) Alzaher-Noufal I., CAD tools for the generation of self-checking arithmetic operators, These de Doctorat, 2001
 
(1963) Parrain F., Mir S., Charlot B., Courtois B., Capteur infrarouge CMOS à thermopiles comportant des fonctions de self-test, ISRN: TIMA-RR--01/07-01--FR, 2001
 
(1964) Courtois B., Charlot B., Parrain F., Mir S., Capteur infrarouge CMOS à thermopiles comportant des fonctions de self-test, Journal on Nano et Micro-Technologies, Vol. 1, page: 387-412, 2001
 
(1965) Rufer L., Thouraud B.-Z., Mir S., Simo M., CMOS front-end for capacitive micromachined ultrasonic transducers, 1st International Workshop on Microfabricated Ultrasonic Transducers, Roma, Italy, May 10-11, 2001, 2001
 
(1966) Mir S., Thouraud B.-Z., Simo M., Rufer L., CMOS Front-end for Capacitive Micromachined Ultrasonic Transducers, ISRN: TIMA-RR--01/06-01--FR, 2001
 
(1967) Torki K., CMP provides the access to advanced low cost manufacturing, 13th International Conference on Microelectronics (ICM'01), Rabat, Morocco, October 29-31 2001, 2001
 
(1968) Torki K., Courtois B., CMP: the access to advanced low cost manufacturing, Proceedings 2001 International Conference on Microelectronic Systems Education. MSE'01. Designing Microsystems in the New Millennium, 17-18 June6. Las Vegas, US, 2001
 
(1969) Nicolescu G., Cesario W., Jerraya A. A., Lyonnard D., Gauthier L., Colif: A design representation for application-specific multiprocessor SOCs, IEEE Design and Test of Computers, Sep-Oct 2001; Volume: 18, page: 8-20, 2001
 
(1970) Gauthier L., Cesario W., Nicolescu G., Lyonnard D., Jerraya A. A., Colif: A multilevel design representation for application-specific multiprocessor system-on-chip design, Proceedings 12th International Workshop on Rapid System Prototyping, 2001
 
(1971) Renaudin M., Vivet P., Composant micro-électronique intégrant des moyens de traitement numérique asynchrone et une interface de couplage électromagnétique sans contact / Micro-electronic component, incorporating asynchronous digital processing means and a contact-free electromagnetic coupling interface, FR2795891, 2001
 
(1972) Martinez S., Courtois B., Jerraya A. A., Yoo S., Youssef W., Kriaa L., Nicolescu G., Conception de systèmes hétérogènes contenant des microsystèmes optiques , ISRN: TIMA--RR-01/11-1--FR, 2001
 
(1973) Velazco R., Sonza Reorda M., Nicolescu B., Rebaudengo M., Violante M., Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparative study and experimental results, 6th European Conference on Radiation and its Effects on Components and Systems (RADECS'01),Grenoble, France, September 10-14 2001, 2001
 
(1974) Nicolaidis M., Anghel L., Cost Reduction and Evaluation of a Temporary Faults Detecting technique, ISRN: TIMA-RR-01/02-02--FR, 2001
 
(1975) Divoux C., Levitan S.P., Basrour S., Mounaix P., Reyne G., Deformable magnetic mirror for adaptive optics: technological aspects, Sensors and Actuators A : Physical, 89, page: 1-9, 2001
 
(1976) Essalhiene M., Fesquet L., Lhuillery F., Ho Q. T., Renaudin M., Démonstration de prototypes d'objets communicants en technologie asynchrone, ISRN: TIMA--RR-01/10-14--FR, 2001
 
(1977) Pressecq F., Goy J., Courtois B., Karam J.M., Design and test of an active pixel sensor (APS) for space applications, Proceedings of the SPIE The International Society for Optical Engineering, 2001
 
(1978) Coudevylle J.-R., De Labacherie M., Majjad H., Basrour S., Design and test of new high Q microresonators fabricated by UV-LIGA, Proceedings of the SPIE The International Society for Optical Engineering, 2001
 
(1979) Farkas G., Courtois B., Szekely V., Pohl L., Benedek Zs., Poppe A., Rencz M., Torki K., Mir S., Design issues of a multi-functional intelligent thermal test die, Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium Cat. No.01CH37189, 2001
 
(1980) Mir S., Farkas G., Pohl L., Poppe A., Rencz M., Szekely V., Torki K., Benedek Zs., Design of a muli-functional intelligent thermal test die, ISRN: TIMA-RR--01/03-01--FR, 2001
 
(1981) Mir S., Benedek Zs., Torki K., Farkas G., Pohl L., Rencz M., Poppe A., Szekely V., Design of a multi-functional intelligent thermal test die, Design Automation and Test in Europe (DATE'01), Munich, Germany, March 13-16, 2001, 2001
 
(1982) Courtois B., Pressecq F., Karam J.M., Goy J., Design of an APS CMOS Image Sensor for Low Light Level Applications Using Standard CMOS Technology, Analog Integrated Circuits and Signal Processing, Oct.-Nov. 29(1-2), page: 95-104, 2001
 
(1983) Tourki R., Abid M., Elmalek J., Torki K., Design of an efficient fuzzy clustering algorithm for breast cancer diagnosis, Smart Systems and Devices Conference (SSD 2001), Hammamet, Tunisia, March 27-30, 2001 , 2001
 
(1984) Juneidi Z., Torki K., Hamza R., Design Rules for Non-Manhattan Shapes, ISRN: TIMA-RR--01/10-4--FR, 2001
 
(1985) Karam J.M., Levitan S.P., Walker J.A., Tay A.A.O., Markus K., Courtois B., Design, Test, Integration, and Packaging of MEMS/MOEMS 2001, 25-27 April 2001, Cannes, France, SPIE Int. Soc. Opt. Eng, , 2001
 
(1986) Leveugle R., Hadjiat K., Early prediction of SEU consequences through VHDL mutant generation, 6th European Conference on Radiation and its Effects on Components and Systems (RADECS 01), Grenoble, France, September 10-14, 2001, 2001
 
(1987) Nicolescu B., Velazco R., Reorda M.S., Effectiveness and limitations of various software techniques for , Proceedings Seventh International On Line Testing Workshop, 2001
 
(1988) Suescun R., Velazco R., Nicolescu B., Effectiveness and limitations of various software techniques for “soft error” detection:, ISRN: TIMA-RR--/10-7--FR, 2001
 
(1989) Charlot B., Parrain F., Mir S., Courtois B., Electrically induced stimuli for MEMS self-test, Proceedings-19th-IEEE-VLSI-Test-Symposium.-VTS-, 2001
 
(1990) Mir S., Courtois B., Charlot B., Parrain F., Electrically Induced Stimuli For MEMS Self-Test, ISRN: TIMA-RR-01/02-01--FR, 2001
 
(1991) Mermet J., Electronic Chips & Systems Design Languages, Kluwer Academic Publishers, , 2001
 
(1992) Jerraya A. A., Matheron G., Electronic system design methodology: Europe's positioning, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001
 
(1993) Rezgui S., Error rate prediction for digital architectures: A method and experimental results, These de Doctorat, 2001
 
(1994) Mingo J.R., Rodriguez S., Ecoffet R., Velazco R., Rezgui S., Estimating error rates in processor-based architectures, IEEE Transactions on Nuclear Science, October 2001, Volume: 48, page: 1680 - 1687, 2001
 
(1995) Laude V., Robert L., Daniau W., Pastureaud T., Basrour S., Wilm M., Ballandras S., Khelif A., Experimental observation of higher order surface acoustic modes in high aspect ratio electroplated nickel electrodes on Y+128 lithium niobate, 2001 IEEE Ultrasonics Symposium. Proceedings. An International Symposium, 2001
 
(1996) Nicolaidis M., Kolonis E., Fail-safe synchronization circuit for duplicated systems, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001
 
(1997) Jerraya A. A., Gauthier L., Nicolescu G., Yoo S., Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication, Sixth IEEE International High Level Design Validation and Test Workshop, 2001
 
(1998) Charlot B., Fault modeling and design-for-test of MEMS, These de Doctorat, 2001
 
(1999) Courtois B., Charlot B., Mir S., Fault simulation of MEMS using HDLs, Journal of Modeling and Simulation of Microsystems, 2(1), page: 35-42, 2001
 
(2000) Anghel L., Fault tolerance versus technological limitations of silicon, These de Doctorat, 2001
 
(2001) Cesario W., Jerraya A. A., Flexible design flow for behavioral synthesis. An effective approach for tool integration, Technique et Science Informatiques (TSI), 20(10), page: 1279-304, 2001
 
(2002) Ritter G., Formal sequential equivalence checking of digital systems by symbolic simulation , These de Doctorat, 2001
 
(2003) Georgelin P., Formal verification of synchronous digital designs, based on symbolic simulation, These de Doctorat, 2001
 
(2004) Georgelin P., Borrione D., Formal verification of VHDL using VHDL-like ACL2 models, Electronic Chips & Systems Design Languages, Kluwer Academic Publishers, Partie III: chapitre 23, 2001
 
(2005) Zergainoh N.-E., Jerraya A. A., Gauthier L., Tambour L., Lyonnard D., Baghdadi A., Framework for system design, validation and fast prototyping of multiprocessor SoCs, Architecture and Design of Distributed Embedded Systems Series: IFIP International Federation for Information Processing,, Kluwer Academic Publishers, ., 2001
 
(2006) Charlot B., Courtois B., Parrain F., Mir S., Generation of electrically induced stimuli for MEMS self-test, Journal of Electronic Testing: Theory and Applications, Dec. 17(6), page: 459-70, 2001
 
(2007) Zergainoh N.-E., Baghdadi A., Lyonnard D., Jerraya A. A., Generic architecture platform for multiprocessor system-on-chip design, 5 International Workshop on Distributed and Parallel Embedded Systems DIPES 2000., 2001
 
(2008) Zergainoh N.-E., Lyonnard D., Jerraya A. A., Baghdadi A., Generic architecture platform for multiprocessor system-on-chip design, Architecture and Design of Distributed Embedded Systems, Kluwer Academic Publishers, , 2001
 
(2009) Nicolescu G., Martinez S., Torki K., Courtois B., Juneidi Z., Jerraya A. A., Global modeling and simulation of System-on-Chip embedding MEMS devices, ASICON 2001. 2001 4th International Conference on ASIC Proceedings Cat. No.01TH8549, 2001
 
(2010) Juneidi Z., Martinez S., Courtois B., Torki K., Nicolescu G., Global Modeling and Simulation of System-on-Chip embedding MEMS devices, ISRN: TIMA-RR--01/10-1--FR, 2001
 
(2011) Courtois B., Guest Editorial, Analog Integrated Circuits and Signal Processing, 2001
 
(2012) Courtois B., Guest Editorial, Analog Integrated Circuits and Signal Processing, October, Volume 29, Numbers 1-2, page: 5-6, 2001
 
(2013) Coste P., Heterogeneous System Design, These de Doctorat, 2001
 
(2014) Leveugle R., High level modifications of VHDL descriptions for on-line detection or tolerance of errors provoked by SEUs , 6th European Conference on Radiation and its Effects on Components and Systems (RADECS 01), Grenoble, France, September 10-14, 2001 , 2001
 
(2015) Cercueil R., Leveugle R., High level modifications of VHDL descriptions for on-line test or fault tolerance, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001
 
(2016) Leveugle R., Cercueil R., High level modifications of VHDL tolerance for on-line test or fault tolerance, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), San Francisco, California, USA, 24-26 October 2001, 2001
 
(2017) Torki K., Tourki R., Ouni R., Abid M., Soudani A., Nasri S., ICs drive down the cost of connectivity for high speed ethernet, Tunisian-German Conference Smart Systems and Devices (SSD 2001), Hammamet, Tunisia, March 27-30 2001, 2001
 
(2018) Velazco R., Ferraya P.A., Marques C.A., Calvo O., Injecting single event upsets in a digital signal processor by means of direct memory access requests: a new method for generating bit flips, 6th IEEE Radiation and its Effects on Components and Systems, (RADECS'01), Grenoble, France, September 10-14, 2001, 2001
 
(2019) Martinez S., Courtois B., Insertion losses in micromachined free-space optical cross-connects due to fiber misalignments, Proceedings of the SPIE The International Society for Optical Engineering, 2001
 
(2020) Fesquet L., Lhuillery F., Essalhiene M., Ho Q. T., Renaudin M., La technologie asynchrone pour la conception d'objets communicants : une revue. Asynchronisme de la puce au système , ISRN: TIMA--RR-01/10-11--FR, 2001
 
(2021) Fesquet L., Les fonctions analogiques intégrées , , , 2001
 
(2022) Juneidi Z., Charlot B., Torki K., Courtois B., MEMS synthesis and optimization, Proceedings of the SPIE The International Society for Optical Engineering, 2001
 
(2023) Juneidi Z., Torki K., Charlot B., Courtois B., MEMS Synthesis and Optimization, ISRN: TIMA-RR--01/10/3--FR, 2001
 
(2024) Charlot B., Mir S., Veychard D., Parrain F., Microbeams with electronically controlled high thermal impedance, Analog Integrated Circuits and Signal Processing, 29(1-2), page: 71-83, 2001
 
(2025) Mir S., Veychard D., Charlot B., Parrain F., Microbeams with electronically controlled high thermal impedance, ISRN: TIMA-RR--01/06-03--FR, 2001
 
(2026) Nicolescu G., Jerraya A. A., Yoo S., Mixed-level cosimulation for fine gradual refinement of communication in SoC design, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001
 
(2027) De Labacherie M., Basrour S., Coudevylle J.-R., Majjad H., Modeling and characterization of Lame-mode microresonators realized by UV-LIGA, TRANSDUCERS '01. EUROSENSORS XV. 11th International Conference on Solid State Sensors and Actuators. Digest of Technical Papers, 2001
 
(2028) Renaudin M., Quartana J., Fesquet L., Rigaud J.B., Modeling and design of asynchronous priority arbiters for on-chip communication systems, ISRN: TIMA--RR-01/10-10--FR, 2001
 
(2029) Rigaud J.B., Renaudin M., Fesquet L., Quartana J., Modeling and design of asynchronous priority arbiters for on-chip communication systems, IFIP International Conference On Very Large Scale Integration (VLSI-SOC'01), Le Corum, Montpellier, France, December 3-5, 2001, 2001
 
(2030) Mir S., Rufer L., Modelling of silicon electrostatic ultrasonic transducers, 1st International Workshop on Microfabricated Ultrasonic Transducers, Roma, Italy, May 10-11, 2001, 2001
 
(2031) Rufer L., Mir S., Modelling of Silicon Electrostatic Ultrasonic Transducers, ISRN: TIMA-RR--01/06-02--FR, 2001
 
(2032) Rencz M., Poppe A., Farkas G., Szekely V., Courtois B., New tools and methods for the thermal transient testing of packages, Proceedings 2001 HD International Conference on High Density Interconnect and Systems Packaging SPIE, 2001
 
(2033) Abdelhay A., On-line testing of linear digital systems, These de Doctorat, 2001
 
(2034) Borrione D., On the development of hardware description languages, Invited paper at the Wissenschaftliches Kolloquium of the Braunschweigische Wissenschaftliche Gesellschaft in the honor of Prof. R. Piloty, Braunschweig, Germany, May 18, 2001, 2001
 
(2035) Reda S., Salem A., Borrione D., Wahba A., Ghonaimy M., On the use of don't cares during symbolic reachability analysis, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems Cat. No.01CH37196., 2001
 
(2036) Gauthier L., OS generation for multitask software targeting on heterogeneous multiprocessor architectures for specific embedded systems., These de Doctorat, 2001
 
(2037) Haniotakis Th., Nikolos D., Tsiatouhas Y., Vergos H.-T., Nicolaidis M., Path delay fault testing of multiplexer-based shifters, International Journal of Electronics, Aug. ; 88(8), page: 923-37, 2001
 
(2038) Courtois B., Proceedings of the 8th Conference Computer Networks, Studia Informatica, Vol. 22 (43), page: , 2001
 
(2039) Lasance C., Szekely V., Courtois B., Rencz M., Proceedings on 7th International Workshop on THERMal INvestigations of ICs and Systems (THERMINIC 2001), September 24-27, 2001, Paris, France, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 299 pages, 2001
 
(2040) Courtois B., Markus K., Proceedings on Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'2001), Cannes - Mandelieu, France, April 25-27, 2001, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 556 pages, 2001
 
(2041) Metra C., Nicolaidis M., Proceedings Seventh International On-Line Testing Workshop (IOLT 2001), 9-11 July 2001, Taormina, Italy, IEEE Computer Society, 230 pages, 2001
 
(2042) Ben Ismail T., Jerraya A. A., Marchioro G.F., Daveau J.- M., Protocol selection and interface generation for HW-SW codesign, Readings in Hardware/Software Co-Design, Morgan Kaufmann Publishers, 366-374 : Chapitre 4, 2001
 
(2043) Tourki R., Abid M., Torki K., Atri M., Rapid prototyping of an ATM traffic control algorithm, Smart Systems and Devices Conference (SSD'2001), Hammamet, Tunisia, March 27-30, 2001 , 2001
 
(2044) Abdelhay A., Simeu E., Naal M. A., Robust self concurrent test of linear digital systems, Proceedings-10th-Asian-Test-Symposium, 2001
 
(2045) Yoo S., Jerraya A. A., Nicolescu G., Gerin P., Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures, Proceedings of the ASP DAC 2001. Asia and South Pacific Design Automation Conference, 2001
 
(2046) De Labacherie M., Basrour S., Majjad H., Coudevylle J.-R., Simulation and Characterization of High Q Microresonators Fabricated by UV – LIGA, Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems, 2001
 
(2047) Piguet CH., Renaudin M., Omnes T.-J.-F., Special Session on Low-Power Systems on Chips & Marc RENAUDIN's Talk, ISRN: TIMA--RR-01/10-9--FR, 2001
 
(2048) Renaudin M., Piguet CH., Omnes T.-J.-F., Special session on low-power systems on chips (SOCs), Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001., 2001
 
(2049) Martinez S., Courtois B., Study of scalability for micromachined free-space optical cross-connects, Photonics Packaging and Integration III part of SPIE Symposium on Integrated Optics, San Jose, California, USA, January 20-26 2001, 2001
 
(2050) Rodrigues V.M., Borrione D., Georgelin P., Symbolic Simulation and Verification of VHDL with ACL2 , System-on-Chip Methodologies and Design Languages edited by Jean Mermet, Kluwer Academic Publishers, , 2001
 
(2051) Courtois B., Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP 2000), Paris, France, 9-11 May 2000: Special Issue, Analog Integrated Circuits and Signal Processing, Springer , Volume 29, Numbers 1-2, 158 pages, 2001
 
(2052) Cota E.F., Reis R., Lubaszewski M., Velazco R., Carro L., Rezgui S., Lima Kastensmidt F., Synthesis of an 8051-like microcontroller tolerant to transient faults, Journal of Electronic Testing: Theory and Applications, April 2001, Volume 17, Number 2, page: 149 - 161, 2001
 
(2053) Mermet J., Ashenden P. J., Seepold R., System-on-Chip Methodologies & Design Languages, Kluwer Academic Publishers, , 2001
 
(2054) Velazco R., Cheynet P., Violante M., Sonza Reorda M., Nicolescu B., Rebaudengo M., System safety through automatic high-level code transformations: an experimental evaluation, Proceedings Design, Automation and Test in Europe. Conference and Exhibition, 2001
 
(2055) Ouni R., Tourki R., Abid M., Torki K., Nasri S., Soudani A., TCP flow control technique for an interworking interface: hardware implementation, Computer Standards & Interfaces, Nov.; 23(5), page: 383-97, 2001
 
(2056) Courtois B., Leclercq J.L., Lescot J., Ribas R.P., Thermal and mechanical evaluation of micromachined planar spiral inductors, Proceedings of the SPIE The International Society for Optical Engineering, 2001
 
(2057) Rencz M., Szekely V., Courtois B., Poppe A., THERMODEL: A Tool for Thermal Model Generation, and Application for MEMS, Analog Integrated Circuits and Signal Processing, Volume 29, Numbers 1-2, page: 49 - 59, 2001
 
(2058) Rezgui S., Velazco R., Reguer E., THESIC : Una plataforma flexible para la validation funcional de circuitos integrados , IBERCHIP, Montevideo, Uruguay, March 23-28, 2001, 2001
 
(2059) Souani C., Abid M., Torki K., Atri M., Tourki R., Two VLSI processors for 1D wavelet transform, Tunisian-German Conference Smart Systems and Devices (SSD 2001), Hammamet, Tunisia, March 27-30, 2001, 2001
 
(2060) Calvo O., Velazco R., Leveugle R., Upset-like Fault Injection in VHDL Descriptions:, ISRN: TIMA-RR--01/10-6--FR, 2001
 
(2061) Velazco R., Calvo O., Leveugle R., Upset-like fault injection in VHDL descriptions: A method and preliminary results, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., 2001
 
(2062) Leveugle R., Antoni L., Feher B., Using run-time reconfiguration for fault injection applications, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics Cat. No.01CH 37188, 2001
 
(2063) Velazco R., Convert P., Hansen H., Rezgui S., Guerard B., Using the ILL facility to evaluate the sensitivity of integrated circuits to thermal neutrons, 6th Conference on Radiation and its Effects on Components and Systems (RADECS' 01), Grenoble, France, , 2001
 
(2064) Velazco R., Calvo O., VHDL fault injection of SEUs in on FPGA based Fuzzy Logic Controller, 16th Conference on Design of Circuits and Integrated Systems (DCIS'01), Porto, Portugal, November 20-23 2001, 2001
 
(2065) Valderrama C., Daveau J.- M., Marchioro G.F., Jerraya A. A., VHDL generation from SDL specification, Readings in Hardware/Software Co-Design, Morgan Kaufmann Publishers, 125-134 : Chapitre 2, 2001
 
(2066) Courtois B., Rencz M., Szekely V., Lasance C., 5th International Workshop on THERMAL INVESTIGATIONS of ICs and MICROSTRUCTURES (THERMINIC 1999), October 3-6, 1999, ROME, Italy: Special Issue, Microelectronics Journal, Elsevier, Volume 31, Issues 9-10, 725-824, 2000
 
(2067) Eyraud S., Delori H., Courtois B., Torki K., Charlot B., Paillotin J.-F., Achievements and advances at CMP, Proceedings of the 3rd European Workshop on Microelectonics Education (EWME'2000), Aix-en-Provence, France 18-19 May 2000, (ISBN 0-7923-6456-2), 2000
 
(2068) Torki K., Abid M., Souani C., Zitouni A., Tourki R., A communication synthesis approach for distributed systems, Technique et Science Informatiques (TSI), April ; 19(4), page: 515-47, 2000
 
(2069) Borrione D., Dushina J., Pierre L., A compositional model for the functional verification of high-level synthesis results, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Oct. ; 8(5), page: 526-30, 2000
 
(2070) Vivet P., Renaudin M., Bouvier J., Abrial A., A contactless smart-card chip based on an asynchronous 8-bit microcontroller, Asynchronous Circuits Design (ACiD) Workshop, Grenoble, January 31st - February 1st, 2000, 2000
 
(2071) Nguyen T., Pierre L., Georgelin P., A formal approach for the specification of communications in distributed systems, ISCA 13th International Conference on Parallel and Distributed Computing Systems (PDCS'2000), Las Vegas, Nevada, USA, August 8-10, 2000, 2000
 
(2072) Bianchi R.A., Karam J.M., Courtois B., ALC crystal oscillators based pressure and temperature measurement integrated circuit for high temperature oil well applications, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Sept. 2000; Volume: 47, page: 1241-1245, 2000
 
(2073) Georgelin P., Borrione D., Moraes-Rogrigues V., An ACL2 model of VHDL for symbolic simulation and formal verification, Proceedings 13th Symposium on Integrated Circuits and Systems Design Cat. No.PR00843, 2000
 
(2074) Karam J.M., Bianchi R.A., Courtois B., Analog ALC crystal oscillators for high-temperature applications, IEEE Journal of Solid State Circuits, 35(1); Janv. 2000, page: 2-14, 2000
 
(2075) Abdelhay A., Simeu E., Analytical redundancy based approach for concurrent fault detection in linear digital systems, Proceedings 6th IEEE International On Line Testing Workshop Cat. No.PR00646, 2000
 
(2076) Abrial A., Senn P., Renaudin M., Bouvier J., Vivet P., A new contactless smartcard IC using an on-chip antenna and an asynchronous micro-controller, Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26th European, 2000
 
(2077) Velazco R., Rezgui S., Rodriguez S., Ecoffet R., A new methodology for the simulation of soft errors on microprocessors : a case study , Military and Aerospace of Programmable Devices and Technologies (MAPLD 2000), Laurel, Maryland, USA, September 26-28, 2000, 2000
 
(2078) Jerraya A. A., Gauthier L., Lyonnard D., Nicolescu G., Cesario W., An XML-based meta-model for the design of multiprocessor embedded systems, Proceedings VHDL International Users Forum Fall Workshop, 2000
 
(2079) Jerraya A. A., Application specific multi-processor system on chip, Invited talk at the First Advanced Computing Workshop Trends in Embedded Computing, Autrans, France, 12-13 December 2000, 2000
 
(2080) Abid M., Torki K., Tourki R., Zitouni A., Souani C., Approche de synthèse de communication pour les systèmes distribués, Technique et Science Informatiques (TSI), vol.19, page: , 2000
 
(2081) Amblard P., Lagnier F., Maraninchi F., Waille Ph., Sicard P., Fernandez J.-C., Architectures logicielles et matérielles, Dunod, , 2000
 
(2082) Parrain F., Courtois B., Mir S., Charlot B., A Self-Testable CMOS Thermopile-Based Infrared Imager, ISRN: TIMA-RR-00/10-02--FR, 2000
 
(2083) Renaudin M., ASPRO : a toy demo , Asynchronous Circuits Design Workshop (AciD 2000), Grenoble, France, January 31- February 1, 2000, 2000
 
(2084) Renaudin M., Asynchronous circuits and systems, Invited Talk at International Summer School on Advanced Microelectronics-Grenoble "MIGAS", Autrans, France, June 28 - July 4 2000, 2000
 
(2085) Renaudin M., Asynchronous circuits and systems : a promising design alternative, Microelectronic Engineering, Volume 54 , page: 133-149, 2000
 
(2086) Renaudin M., Asynchronous logic : a promising design alternative, Invited Tutorial at the XV Conference on Design of Circuits and Integrated Systems (DCIS 2000), Le Corum, Montpellier, France, November 21-24, 2000, 2000
 
(2087) Morawiec A., Ubar R., Raik J., Back-tracing and event-driven techniques in high-level simulation with decision diagrams, IEEE International Symposium on Circuits and Systems (ISCAS'2000), Geneva, Switzerland, 28-31 May 2000, 2000
 
(2088) Morawiec A., Mermet J., Behavioral abstraction of HDL models for simulation performance, Asia-Pacific Conference on Chip Design Languages APChDL2000 at 16th IFIP World Computer Congress 2000, Beijing, China, 21-24 August 2000, 2000
 
(2089) Sugar Z., Behavioral Synthesis Based on Scheduling, These de Doctorat, 2000
 
(2090) Karam J.M., Bianchi R.A., Courtois B., Nadal R., Pressecq F., CMOS-compatible temperature sensor with digital output for wide temperature range applications, Microelectronics journal, Sept. -Oct. 31(9-10):, page: 803-10, 2000
 
(2091) Courtois B., Palan B., Husak M., CMOS ISFET-based structures for biomedical applications, 1st Annual International IEEE EMBS Special Topic Conference on Microtechnologies in Medicine and Biology. Proceedings Cat. No.00EX451, 2000
 
(2092) Courtois B., Torki K., CMP Experience on deep sub-micron design-methodology support and transfer, Proceedings of the 3rd European Workshop on Microelectonics Education (EWME'2000), Aix-en-Provence, France 18-19 May 2000, 2000
 
(2093) Hessel F., Coste P., Jerraya A. A., Zergainoh N.-E., Le Marrec Ph., Nicolescu G., Communication Synthesis of Multilanguage Specification, ISRN: TIMA-RR--00/06-1--FR, 2000
 
(2094) Sicard G., Conception d'une rétine analogique/numérique en technologie avancée, Invited Talk at Operation Thématique "Rétines", GDR, March 10, 2000, 2000
 
(2095) Jerraya A. A., Nacabal F., Valderrama C., Hessel F., Paulin P., Co-simulation C-VHDL pour la validation fonctionnel de logiciel embarqué, Technique et Science Informatiques (TSI), vol.19, page: , 2000
 
(2096) Nicolaidis M., Anghel L., Cost reduction and evaluation of a temporary faults detecting technique, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 Cat. No. PR00537, 2000
 
(2097) Jerraya A. A., Paulin P., Hessel F., Valderrama C., Nacabal F., C-VHDL co-simulation for functional validation of embedded software, Technique et Science Informatiques (TSI), Oct. 2000; 19(8), page: 1097-126, 2000
 
(2098) Ubar R., Morawiec A., Raik J., Cycle-based simulation algorithms for digital systems using high-level decision diagrams, Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France , 2000
 
(2099) Gauthier L., Jerraya A. A., Cycle-true simulation of the ST10 microcontroller, Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France , 2000
 
(2100) Jerraya A. A., Gauthier L., Cycle­true simulation of the ST10 microcontroller (core and peripherals), ISRN: TIMA-RR--00/02/1--FR, 2000
 
(2101) Jerraya A. A., Gauthier L., Cycle-true simulation of the ST10 microcontroller including the core and the peripherals, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype, 2000
 
(2102) Mounaix P., Levitan S.P., Reyne G., Basrour S., Divoux C., Deformable magnetic mirror for adaptive optics: first results, Proceedings IEEE Thirteenth Annual International Conference on Micro Electro Mechanical Systems (Cat. No.00CH36308), 2000
 
(2103) Amblard P., De nouvelles pistes dans l'initiation à la conception de circuits digitaux : machines pipelinées et preuves de circuits, Sixièmes Journées Pédagogiques, Centre Commun de Microélectronique de l'Ouest (CCMO), Saint Malo, France, November 29&30 - December 1st 2000, 2000
 
(2104) Anelli G., Design and characterization of radiation tolerant integrated circuits in deep submicron CMOS technologies for the LHC experiments, These de Doctorat, 2000
 
(2105) Courtois B., Pressecq F., Karam J.M., Goy J., Design and test of an active pixel sensor (APS) CMOS image sensor for space applications, Electroning Imaging 2001 Conference on sensors, cameras, and systems for scientific/industrial applications III (E117), San Jose, California, USA, January 21-26 2001, 2000
 
(2106) Ubar R., Borrione D., Design error diagnosis in digital circuits without error model, VLSI: Systems on a Chip. IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration VLSI'99., 2000
 
(2107) Velazco R., Lima Kastensmidt F., Cota E.F., Lubaszewski M., Rezgui S., Designing and testing a radiation hardened 8051-like micro-controller, Military and Aerospace of Programmable Devices and Technologies (MAPLD 2000), Laurel, Maryland, USA, September 26-28, 2000, 2000
 
(2108) Carro L., Cota E.F., Rezgui S., Velazco R., Reis R., Lubaszewski M., Designing a radiation hardened 8051-like micro-controller, Proceedings 13th Symposium on Integrated Circuits and Systems Design, 2000
 
(2109) Reis R., Cota E.F., Rezgui S., Lima Kastensmidt F., Lubaszewski M., Carro L., Velazco R., Designing a Radiation Hardened 8051-like Micro-controller, ISRN: TIMA-RR--00/06-2--FR, 2000
 
(2110) Pressecq F., Courtois B., Goy J., Karam J.M., Design of an APS CMOS image sensor for space applications using standard CAD tools and CMOS technology, Proceedings of the SPIE The International Society for Optical Engineering, 2000
 
(2111) Poppe A., Benedek Zs., Pohl L., Szekely V., Farkas G., Torki K., Courtois B., Rencz M., Mir S., Design of a scalable multi-functional thermal test die with direct and boundary scan access for programmed excitation and data measurement, 6th International Workshop on Thermal Investigations of ICs and Systems plus a special Half Day on Compact Models, 2000
 
(2112) Souani C., Tourki R., Torki K., Abid M., Atri M., Design of new optimized architecture processor for DWT, Real Time Imaging, Aug.; 6(4), page: 297-312, 2000
 
(2113) Lubaszewski M., Mir S., Kolarik V., Nielsen C., Courtois B., Design of self-checking fully differential circuits and boards, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(2): April, page: 113-28, 2000
 
(2114) Hamza R., Torki K., Juneidi Z., Design rules for non-Manhattan shapes, Proceedings-of-the-SPIE-The-International-Society-for-Optical-Engineering.Santa Clara, US, 2000
 
(2115) Cesario W., Baghdadi A., Zergainoh N.-E., Jerraya A. A., Roudier T., Design Space Exploration for Hardware/Software Codesign of Multiprocessor ArchitecturesMultiprocessor Architectures, ISRN: TIMA-RR--00/02-4--FR, 2000
 
(2116) Baghdadi A., Zergainoh N.-E., Roudier T., Cesario W., Jerraya A. A., Design space exploration for hardware/software codesign of multiprocessor systems, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype , 2000
 
(2117) Markus K., Courtois B., Gabriel K.J., Crary S.B., Karam J.M., Tay A.A.O., Design, Test, Integration, and packaging of MEMS/MOEMS, Paris, France, 2000, SPIE Int. Soc. Opt. Eng, , 2000
 
(2118) Sugar Z., Cesario W., Moussa I., Jerraya A. A., Efficient integration of behavioral synthesis within existing design flows, Proceedings 13th International Symposium on System Synthesis, 2000
 
(2119) Jerraya A. A., Ernst R., Embedded system design with multiple languages, Proceedings ASP DAC 2000. Asia and South Pacific Design Automation Conference 2000 with EDA TechnoFair 2000, 2000
 
(2120) Vargas F., Amory A., Velazco R., Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL, Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW), 2000
 
(2121) Velazco R., Ecoffet R., Rezgui S., Mingo J.R., Rodriguez S., Estimating error rates in processor-based architectures, Workshop on Radiation Effects on Components and Systems (RADECS 2000), Louvain-la-Neuve, Belgium, September 11-13, 2000, 2000
 
(2122) Cheynet P., Nicolescu B., Velazco R., Violante M., Reorda M.S., Rebaudengo M., Evaluating the effectiveness of a software fault-tolerance technique on RISC- and CISC-based architectures, Proceedings 6th IEEE International On Line Testing Workshop, 2000
 
(2123) Alexandrescu D., Anghel L., Nicolaidis M., Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy, 13th Symposium on Integrated Circuits and Systems Design (SBCCI'00), 2000
 
(2124) Velazco R., Ecoffet R., Haussy J., Lambert J., Cheynet P., Tissot A., Evidences of SEU tolerance for digital implementations of artificial neural networks: one year MPTB flight results, 1999 Fifth European Conference on Radiation and Its Effects on Components and Systems. RADECS 99, 2000
 
(2125) Griffaton N., Basrour S., Ballandras S., Gelly J.F., Lanteri F., Experimental and theoretical analysis of silicon-based piezoelectric transducers for ultrasound imaging, Microtechnologies in Medicine and Biology, 1st Annual International, Conference, 2000
 
(2126) Nicolescu B., Rebaudengo M., Sonza Reorda M., Violante M., Cheynet P., Velazco R., Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors, IEEE Transactions on Nuclear Science, Dec. 2000, Volume: 47 , Part 3, page: 2231-2236, 2000
 
(2127) Charlot B., Courtois B., Mir S., Extending Fault-Based Testing to Microelectromechanical Systems, JETTA - Journal of Electronic Testing: Theory and Application, 16, page: 279-288, 2000
 
(2128) Leveugle R., Fault injection in VHDL descriptions and emulation, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2000
 
(2129) Baghdadi A., Lyonnard D., Zergainoh N.-E., Jerraya A. A., Gauthier L., Tambour L., Framework for system design, validation and fast prototyping of multiprocessor system-on-chip: applied to telecommunication systems, International Workshop on Distributed and Parallel Embedded Systems, DIPES-2000 IFIP, Paderborn, Germany, October 18-19, 2000, 2000
 
(2130) Courtois B., Rencz M., Szekely V., Poppe A., Friendly tools for the thermal simulation of power packages, IWIPP 2000. International Workshop on Integrated Power Packaging Cat. No.00EX426, 2000
 
(2131) Poppe A., Courtois B., Szekely V., Rencz M., From MEMS to the global simulation of SoCs, Proceedings of the SPIE The International Society for Optical Engineering, 2000
 
(2132) Charlot B., Courtois B., Mir S., Lubaszewski M., From microelectronics to MEMS testing, IEEE Microelectronics Reliability and Qualification Workshop, Glendale, California, USA, 1 November 2000, 2000
 
(2133) Courtois B., Mir S., Charlot B., Lubaszewski M., From Microelectronics to MEMS Testing, ISRN: TIMA-RR-00/10-01--FR, 2000
 
(2134) Lyonnard D., Zergainoh N.-E., Baghdadi A., Jerraya A. A., Generic architecture platform for multiprocessor embedded system-on-chip design, International Workshop on Distributed and Parallel Embedded Systems, DIPES 2000 IFIP WG 10.3 / WG 10.4 / WG 10.5, Paderborn University, Germany, October 2000, 2000
 
(2135) Mingo J.R., Velazco R., Rezgui S., Rodriguez S., Ground testing of architecture including digital processor signal AD21060 , European Conference on Digital Signal Processing (DSP 2000), Munich, Allemagne, October 11-12, 2000, 2000
 
(2136) Violante M., Sonza Reorda M., Rebaudengo M., Velazco R., Cheynet P., Nicolescu B., Hardening the software with respect to transient errors: a method and experimental results , 1st IEEE Latin-American Test Workshop (LATW 2000), Rio de Janeiro, Brazil, March 13-15, 2000 , 2000
 
(2137) Morawiec A., Ubar R., Raik J., High-level decision diagrams for improving simulation performance of digital systems, The 4th World Multiconference on Systemics, Cybernetics and Informatics SCI'2000, Orlando, Florida, USA, July 23-26 2000, 2000
 
(2138) Simeu E., Naal M. A., High level synthesis methodology for on-line testability optimization, Proceedings 6th IEEE International On Line Testing Workshop Cat. No.PR00646, 2000
 
(2139) Veychard D., Parrain F., Mir S., Charlot B., High thermal impedance beams for suspended MEMS, Design, Test, Integration, and Packaging of MEMS/MOEMS, 2000
 
(2140) Rencz M., Töröka S., Torki K., Courtois B., Szekely V., IDDQ Testing of Submicron CMOS—by Cooling?, JETTA - Journal of Electronic Testing: Theory and Application, 16, page: 453-461, 2000
 
(2141) Morawiec A., Improving the simulation performance of event-driven and cycle-based simulation techniques of HDL models, These de Doctorat, 2000
 
(2142) Le Marrec Ph., Nicolescu G., Daveau J.- M., Jerraya A. A., Hessel F., Coste P., Zergainoh N.-E., Interlanguage Communication Synthesis for Heterogeneous Specifications, Design Automation for Embedded Systems, August 2000, Volume 5, Numbers 3-4, page: 223-236, 2000
 
(2143) Torki K., Abid M., Nasri S., Ouni R., Tourki R., Soudani A., Interoperability of ATM-Ethernet interworking system: design and congestion control, 1st-European-Conference-on-Universal-Multiservice-Networks.-ECUMN'2000-Cat.-No.00EX423.Colmar, FR, 2000
 
(2144) Lagnier F., Levy M., Amblard P., Introducing digital circuits design and formal verification concurrently, Proceedings of the 3rd European Workshop on Microelectonics Education (EWME'2000), Aix-en-Provence, France 18-19 May 2000 , 2000
 
(2145) Bied-Charreton D., Calin T., Nicolaidis M., Zaidan N., ISIS: a fail-safe interface realised in smart power technology, Proceedings 6th IEEE International On Line Testing Workshop Cat. No.PR00646, 2000
 
(2146) De Labacherie M., Jeannot J.C., Schropfer G., Goy J., Courtois B., Micro-accéléromètre intégré 3 axes, Microcapteurs et microsystèmes intégrés (NMT, Nano et Micro Technologies), Hermès, Vol. 1 N°1, 2000
 
(2147) Stehelin G., Kamarinos G., Courtois B., Guillemot N., Microelectronics Education: proceedings of the 3rd European Workshop on Microelectonics Education (EWME'2000), Aix-en-Provence, France 18-19 May 2000, Kluwer Academic Publishers, , 2000
 
(2148) Husak M., Courtois B., Palan B., Microsystems for space applications, Acta Polytechnica, Czech Technical University in Prague, 40(3), page: 53-7, 2000
 
(2149) Rigaud J.B., Renaudin M., Modeling and design/synthesis of arbitration problems , Asynchronous Interfaces : Tools, Techniques and Implementations Workshop (AINT'2000), TU Delft, The Netherlands, July 19-20 2000, 2000
 
(2150) Hessel F., Multilanguage Codesign of Heterogeneous Systems, These de Doctorat, 2000
 
(2151) Jerraya A. A., Hessel F., Coste P., Multilanguage codesign using SDL and matlab, SASIMI 2000, Kyoto, Japan, April 2000, 2000
 
(2152) Coste P., Jerraya A. A., Hessel F., Multilanguage Codesign Using SDL and Matlab, ISRN: TIMA-RR--00/02-3--FR, 2000
 
(2153) Coste P., Hessel F., Jerraya A. A., Nicolescu G., Le Marrec Ph., Multilanguage design of a robot arm controller: Case study, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System on Chip Era, 2000
 
(2154) Le Marrec Ph., Hessel F., Coste P., Jerraya A. A., Nicolescu G., Multilanguage Design of a Robot Arm Controller: Case Study, ISRN: TIMA-RR--00/02-2--FR, 2000
 
(2155) Zergainoh N.-E., Le Marrec Ph., Coste P., Nicolescu G., Hessel F., Jerraya A. A., Multi-level communication synthesis of heterogeneous multilanguage specification, Proceedings 2000 International Conference on Computer Design, 2000
 
(2156) Nicolescu G., Zergainoh N.-E., Coste P., Hessel F., Jerraya A. A., Le Marrec Ph., Multi-level communication synthesis of heterogeneous multilanguage specifications, International Conference on Computer Design (ICCD 2000), Austin, Texas, USA, September 17-20, 2000, 2000
 
(2157) Le Marrec Ph., Multilevel co-simulation in a multilanguage design flow, These de Doctorat, 2000
 
(2158) Magyari D., Benedek Zs., Torki K., Courtois B., Rencz M., Ress S., Szekely V., Poppe A., Töröka S., New approaches in the transient thermal measurements, Microelectronics journal, Volume 31 , page: 727-733, 2000
 
(2159) Courtois B., Szekely V., Rencz M., Poppe A., New hardware tools for the thermal transient testing of packages, Proceedings of 3rd Electronics Packaging Technology Conference EPTC 2000 Cat. No.00EX456., 2000
 
(2160) Simeu E., Naal M. A., On­Line Testability Optimization in High Level Synthesis, ISRN: TIMA-RR--00/04-1--FR, 2000
 
(2161) Simeu E., Optimal detector design for on-line testing of linear analog systems, VLSI Design, 11(1), page: 59-74, 2000
 
(2162) Hadjiat K., Leveugle R., Optimized generation of VHDL mutants for injection of transition errors, Proceedings 13th Symposium on Integrated Circuits and Systems Design Cat. No.PR00843, 2000
 
(2163) Rezgui S., Velazco R., Ecoffet R., Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection, IEEE Transactions on Nuclear Science, Dec. 2000; Volume: 47 , Part 3, page: 2405-2411, 2000
 
(2164) Segura J., Nicolaidis M., Proceedings of 6th IEEE International On-Line Testing Workshop (IOLT 2000), July 3-5, 2000 Palma De Mallorca, Spain, IEEE Computer Society, 220 pages, 2000
 
(2165) Rencz M., Poppe A., Courtois B., Lasance C., Szekely V., Proceedings on 6th International Workshop on THERMal INvestigations of ICs and Systems (THERMINIC 2000), September 24-27, 2000, Budapest, Hungary, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 275 pages, 2000
 
(2166) Markus K., Courtois B., Proceedings on Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP of MEMS/MOEMS ), Paris, France, 9-11 May 2000, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 594 pages, 2000
 
(2167) Coissard V., Processor core for exact arithmetic, These de Doctorat, 2000
 
(2168) Borrione D., Rodrigues V.M., Georgelin P., Reasoning about VHDL components with ACL2, Workshop on Formal Methods (WMF'00), SOCIEDADE BRASILEIRA DE COMPUTACAO, Jo‹o Pessoa, Para'ba, Brazil, 2nd - 4th October 2000, 2000
 
(2169) Cesario W., Jerraya A. A., Moussa I., Sugar Z., Rethinking behavioral synthesis for a better integration within existing design flows, Proceedings 2000 International Conference on Computer Design, 2000
 
(2170) Peters A.W., Simeu E., Robust model-based concurrent fault detection - application to linear analog systems, 6th IEEE International Mixed-Signal Testing Workshop (IMSTW 2000), Montpellier, France, June 21-23, 2000, 2000
 
(2171) Nicolaidis M., Anghel L., Alzaher-Noufal I., Self-checking circuits versus realistic faults in very deep submicron, Proceedings-18th-IEEE-VLSI-Test-Symposium, 2000
 
(2172) Jerraya A. A., Gauthier L., Software & RTOS targeting for multiprocessor architectures, MEDEA Conference on Embedded System Design, Munich, Germany, October 11-13, 2000, 2000
 
(2173) Rayane I., Peters A.W., Simeu E., Symbolic modeling for fault detection and isolation : application to linear analog systems, 16th IMACS World Congress on Scientific Computation, Modeling and Applied Mathematics, Lausanne, Switzerland, August 21-25 2000, 2000
 
(2174) Borrione D., Borrione D., Rodrigues V.M., Georgelin P., Symbolic simulation and verification of VHDL with ACL2, HDLCON'2000, 8-10 March 2000, San Jose, California, USA, 2000
 
(2175) Cota E.F., Lubaszewski M., Velazco R., Carro L., Rezgui S., Synthesis of a 8051-like microcontroller tolerant to transient faults , 1st IEEE Latin-American Test Workshop (LATW 2000), Rio de Janeiro, Brazil, March 13-15, 2000, 2000
 
(2176) Robert L., Sittler F., Wery M., Basrour S., The morphology and electrochemical behavior of electrodeposited nickel onto metallized silicon, Plating and Surface Finishing, 87(5), page: 153-9, 2000
 
(2177) Courtois B., Kohari Z., Szekely V., Rencz M., Thermal evaluation and modeling of MEMS packages, IEMT/IMC Symposium, Omiya, Japan, April 2000, 2000
 
(2178) Kohari Z., Szekely V., Courtois B., Rencz M., Thermal evaluation and modelling of the SIP9 and SP10 MEMS packages, ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems Cat. No.00CH37069, 2000
 
(2179) Szekely V., Poppe A., Rencz M., Courtois B., THERMODEL : a tool for thermal model generation, and application for MEMS packages, Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP of MEMS/MOEMS), Paris, France, 9-11 May 2000 , 2000
 
(2180) Courtois B., Poppe A., Rencz M., Szekely V., THERMODEL: a tool for thermal model generation and application for MEMS packages, Proceedings of the SPIE The International Society for Optical Engineering, 2000
 
(2181) Parrain F., Zergainoh N.-E., Courtois B., Mir S., Charlot B., Rencz M., Nicolescu G., Coste P., Jerraya A. A., Towards design and validation of mixed-technology SOCs, Great Lakes Symposium on VLSI Proceedings of the 10th Great Lakes symposium on VLSI, 2000
 
(2182) Charlot B., Rencz M., Jerraya A. A., Courtois B., Zergainoh N.-E., Parrain F., Coste P., Nicolescu G., Mir S., Towards Design And Validation Of Mixed-Technology SOCs, ISRN: TIMA-RR--00/01-1--FR, 2000
 
(2183) Velazco R., Rezgui S., Transient bitflip injection in microprocessor embedded applications, Proceedings 6th IEEE International On Line Testing Workshop, 2000
 
(2184) Rodrigues V.M., Georgelin P., Borrione D., Using macros to mimic VHDL in ACL2, Computer-Aided Reasoning: ACL2 Case Studies, Kluwer Academic Publishers, 162-185, 2000
 
(2185) Feher B., Antoni L., Leveugle R., Using run-time reconfiguration for fault injection in hardware prototypes, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2000
 
(2186) Morawiec A., Raik J., Ubar R., Vector decision diagrams for simulation of digital systems, Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS2000), Smolenice, Slovakia, April 5-7 2000, 2000
 
(2187) Abid M., Atri M., Torki K., Souani C., Tourki R., VLSI design of 1-D architecture with parallel filters, Integration, the VLSI Journal, vol. 29, page: , 2000
 
(2188) Torki K., Abid M., Souani C., Tourki R., VLSI design of 1-D DWT architecture with parallel filters, Integration, the VLSI Journal, Sept. ; 29(2), page: 181-206, 2000
 
(2189) Guyot A., Web based exercices on computer arithmetic, Proceedings of the 3rd European Workshop on Microelectonics Education (EWME'2000), Aix-en-Provence, France 18-19 May 2000 , 2000
 
(2190) Szekely V., Courtois B., Rencz M., 4th International Workshop on THERMAL INVESTIGATIONS of ICs and MICROSTRUCTURES (THERMINIC 1998) September 27-29,Cannes, "Côte d'Azur", France: Special Issue, Microelectronics Journal, Elsevier, Volume 30, Issue 11 , November, 1083-1172, 1999
 
(2191) Nicolaidis M., Alzaher-Noufal I., A CAD framework for generating self-checking multipliers based on residue codes, Design Automation and Test in Europe Conference and Exhibition 1999, 1999
 
(2192) Velasco-Medina J., Nicolaidis M., Rayane I., AC/DC BIST for testing analog circuits, Twelfth Annual IEEE International ASIC/SOC-Conference, 1999
 
(2193) Zimmermann J., Guyot A., Bara S., Negoi A.C., A dedicated circuit for charged particles simulation using the Monte Carlo method, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, June ; 21(2), page: 103-16, 1999
 
(2194) Renaudin M., Vivet P., Robin F., A design framework for asynchronous/synchronous circuits based on CHP to HDL translation, Proceedings Fifth International Symposium on Advanced Research in Asynchronous-Circuits and Systems, 1999
 
(2195) Velasco-Medina J., Nicolaidis M., Rayane I., A digital BIST for operational amplifiers embedded in mixed-signal circuits, Proceedings 17th IEEE VLSI Test Symposium, 1999
 
(2196) Veychard D., Courtois B., Boutamine H., Karam J.M., Liateni K., Cao A., Moulinier D., Affour B., Advanced integrated solution for MEMS design, Proceedings of the SPIE The International Society for Optical Engineering, 1999
 
(2197) Torki K., Courtois B., Advanced low cost manufacturing from CMP service, IEEE International Conference on Microelectronic Systems Education, 1999. MSE '99., 1999
 
(2198) Courtois B., Bianchi R.A., Karam J.M., ALC crystal oscillator based pressure and temperature integratedmeasurement system for high temperature oil well applications, European Frequency and Time Forum, 1999 and the IEEE International Frequency Control Symposium, 1999., Proceedings of the 1999 Joint Meeting of the, 1999
 
(2199) Bianchi R.A., Analog integrated circuits design techniques for high temperature applications in standard silicon technologies, These de Doctorat, 1999
 
(2200) Jerraya A. A., Moussa I., Diaz-Nava M., Analysing the cost of design for reuse, Reuse Techniques for VLSI Design, Kluwer Academic Publishers, chapitre 2, 1999
 
(2201) Clermidy F., Nicolaidis M., Collette T., A new placement algorithm dedicated to parallel computers: bases and application, Proceedings 1999 Pacific Rim International-Symposium on Dependable Computing, 1999
 
(2202) Nicolaidis M., Velasco-Medina J., Rayane I., A one-bit-signature BIST for embedded operational amplifiers in mixed-signal circuits based on the slew-rate detection, Design Automation and Test in Europe Conference and Exhibition 1999, 1999
 
(2203) Robin F., Renaudin M., Vivet P., ASPRO: an asynchronous 16-bit RISC microprocessor with DSP capabilities, ESSCIRC'99. Proceedings of the 25th European Solid State Circuits Conference, 1999
 
(2204) Rencz M., Courtois B., Szekely V., A step forward in the transient thermal characterization of chips and packages, Microelectronics and Reliability, 39(1):; Jan. 1999, page: 89-96, 1999
 
(2205) Simeu E., Rayane I., Peters A.W., Automatic design of optimal concurrent fault detector for linear analog systems, Digest of Papers. Twenty Ninth Annual Internationa Symposium on Fault Tolerant-Computing, 1999
 
(2206) Velasco-Medina J., Bist techniques for analog and mixed-signal circuits, These de Doctorat, 1999
 
(2207) Nicolaidis M., Anghel L., Calin T., Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS, 17TH IEEE VLSI Test Symposium, 1999
 
(2208) Ribas R.P., Courtois B., CAD environment for MEMS, International Conference on Microelectronics and Packaging (SBMicro'99), Campinas, Brazil, 3-6 August 1999, Technical Digest, pp. 316-325, 1999
 
(2209) Hazard Ph., Karam J.M., Veychard D., Capteur Thermoelectrique notamment pour appareils electriques, FR2778742, 1999
 
(2210) Pressecq F., Nadal R., Courtois B., Karam J.M., Bianchi R.A., Sifflet S., CMOS compatible temperature sensor with digital output for wide temperature range applications, 5th International Workshop Thermal Investigations of ICs and Systems, 1999
 
(2211) Calin T., CMOS system design and test for reliability and fault tolerance, These de Doctorat, 1999
 
(2212) Coste P., Le Marrec Ph., Zergainoh N.-E., Daveau J.- M., Jerraya A. A., Hessel F., Communication interface synthesis for multilanguage specifications, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype, 1999
 
(2213) Jerraya A. A., Crudo S., Pavesi M., Diaz-Nava M., Suescun R., Sugar Z., Gazzi L., Moussa I., Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper, Proceedings 1999 Design Automation Conference, 1999
 
(2214) Jerraya A. A., Moussa I., Sugar Z., Suescun R., Bianchi R.A., Pavesi M., Gazzi L., Crudo S., Comparing RTL and Behavioral Design Methodologies in the Case of a 2M Transistors ATM Shaper, ISRN: TIMA-RR--99/04-3--FR, 1999
 
(2215) David J.P., Loquet J.G., Cheynet P., Ecoffet R., Velazco R., Duzellier S., Comparison between ground tests and flight data for two static 32 KB memories, The 5th European Conference on Radiation and its effects on components and systems (RADECS'99), Abbaye de Fontevraud, France, 13 -17 September 1999, 1999
 
(2216) Bernal A., Conception et étude d'une architecture numérique de haute performance pour le calcul de la fonction exponentielle modulaire, These de Doctorat, 1999
 
(2217) Nicolaidis M., Anghel L., Concurrent checking for VLSI, Microelectronic Engineering, Volume 49, Issues 1-2 , November, page: 139-156, 1999
 
(2218) Guillaume Ph., Contribution to the back-end of system on a chip synthesis, These de Doctorat, 1999
 
(2219) Nicolaidis M., Vargas F., Criteria for static current estimation: how good are they? An approach incorporating IC quality requirements, Proceedings XII Symposium on Integrated Circuits and Systems Design , 1999
 
(2220) Raik J., Morawiec A., Ubar R., Cycle-based simulation with decision diagrams, Conference and Exhibition on Design, Automation and Test in Europe (DATE'99), Munich, Germany, 9-12 March 1999, 1999
 
(2221) Cosculluela J., Snoeys W., Jarron P., Anelli G., Calin T., Nicolaidis M., Moreira P., Paccagnella A., Marchioro A., Velazco R., Campbell M., Delmastro M., Faccio F., Giraldo A., Heijne E., Kloukinas K., Letheren M., Deep submicron CMOS technologies for the LHC experiments, Nuclear Physics B Proceedings Supplements, Aug. 1999; 78, page: 625-34, 1999
 
(2222) Lubaszewski M., Hofmann K., Courtois B., Mir S., Karam J.M., Rencz M., Szekely V., Glesner M., Design and test of MEMS, Proceedings Twelfth International Conference on VLSI Design, 1999
 
(2223) Mir S., Design and test of next generation integrated systems embedding MEMS, ECS'99. Proceedings of the 2nd Electronics-Circuits and Systems Conference, 1999
 
(2224) Demidenko S., Courtois B., Design, Characterization and Packaging for MEMS and Microelectronics (MICRO/MEMS'99), SPIE Int. Soc. Opt. Eng, , 1999
 
(2225) Ubar R., Borrione D., Design error diagnosis in digital circuits without error model, Tenth International Conference on Very Large Scale Integration (VLSI'99), Lisboa, Portugal, 1-4 December 1999, 1999
 
(2226) Laurent B., Design of reuse blocks - reflections on methodology, These de Doctorat, 1999
 
(2227) Crary S.B., Fujita H., Markus K., Ehrfeld W., Courtois B., Karam J.M., Design, Test, and Microfabrication of MEMS and MOEMS (DTM'99), Paris, France, 30 March - 1 April 1999, SPIE Int. Soc. Opt. Eng, , 1999
 
(2228) Simeu E., Rayane I., Peters A.W., Detection Circuit Design for Concurrent Testing of Linear Analog Systems, ISRN: TIMA-RR--99/04-4--FR, 1999
 
(2229) Basrour S., Schmidt M., Majjad H., Delobelle P., Dynamic determination of Young's modulus of electroplated nickel used in LIGA technique, Sensors and Actuators A : Physical, A74(1-3), page: 148-51, 1999
 
(2230) Vergos H.-T., Tsiatouhas Y., Nicolaidis M., Nikolos D., Haniotakis Th., Easily testable carry-save multipliers with respect to path delay faults, ECS'99. Proceedings of the 2nd Electronics Circuits and Systems Conference, 1999
 
(2231) Ecoffet R., Velazco R., Cheynet P., Effects of radiation on digital architectures: one year results from a satellite experiment, Proceedings. XII Symposium on Integrated Circuits and Systems Design, 1999
 
(2232) Velazco R., Cheynet P., Ecoffet R., Effects of radiation on digital architectures: one year results of a satellite experiment, Brasilian Symposium on Circuit Design, XII SBCC, Natal , Brazil, pp.168-174, 29 September- 2 October 1999, 1999
 
(2233) Veychard D., Electro-thermal converter with long time constant in microsystem technology for thermal breaker, These de Doctorat, 1999
 
(2234) Roudier T., Zergainoh N.-E., Jerraya A. A., Baghdadi A., Cesario W., Teruya M.Y., Estimation de performance au niveau système : une ouverture à l'exploration pour le codesign, ISRN: TIMA-RR--99-07-2--FR, 1999
 
(2235) Balme L., Bacivarov L., European program in quality of complex integrated sysems (EPIQCS) - A contribution to the european educational effort in quality field, Inforec Press, Romania, , , 1999
 
(2236) Velazco R., Lambert J., Cheynet P., Haussy J., Tissot A., Ecoffet R., Evidences of SEU tolerance for digital implementations of Artificial Neural Networks: one year MPTB flight results, 5th European Conference on Radiation and its Effects on Components and Systems (RADECS'99), Abbaye de Fontevraud, France, 13 -17 September 1999 , 1999
 
(2237) Chagoya A., Leveugle R., Experiments on multimedia support of VLSI design teaching in the MODEM project, Proceedings 1999 IEEE International Conference on Microelectronic Systems Education MSE'99`Systems Education in the 21st-Century', 1999
 
(2238) Guillaume Ph., Boulanger B., Cornero M., Paulin P., Santana M., Exploitation au niveau des ressources d'adressage machine dans le cadre d'applications embarquées, ISRN: TIMA--RR-99/04-8--FR, 1999
 
(2239) Rayane I., Simeu E., Peters A.W., Extended state modeling for concurrent testing of linear analog systems, 5th International On-Line Testing Workshop, Rhodes Greece, July 5-7 1999, 1999
 
(2240) Courtois B., Charlot B., Mir S., Extending fault-based testing to microelectromechanical systems, European Test Workshop , 1999
 
(2241) Charlot B., Mir S., Courtois B., Extending fault­based testing to Microelectromechanical Systems, ISRN: TIMA-RR--99/05-1--FR, 1999
 
(2242) Charlot B., Moussouris S., Mir S., Courtois B., Fault modeling of electrostatic comb-drives for MEMS, Proceedings of the SPIE The International Society for Optical Engineering, 1999
 
(2243) Charlot B., Moussouris S., Mir S., Courtois B., Fault modeling of electrostatic comb-drives for MEMS, Design, Test, and Microfabrication of MEMS and MOEMS, 1999
 
(2244) Mir S., Cota E.F., Courtois B., Charlot B., Lubaszewski M., Fault modeling of suspended thermal MEMS, International Test Conference 1999. Proceedings-IEEE, 1999
 
(2245) Nicolaidis M., Duarte R.O., Fault-secure parity prediction Booth multipliers, IEEE Design and Test of Computers, July-Sept. ; 16(3), page: 90-101, 1999
 
(2246) Courtois B., Cota E.F., Charlot B., Mir S., Lubaszewski M., Fault simulation of MEMS using HDLs, Proceedings of the SPIE The International Society for Optical Engineering, 1999
 
(2247) Mir S., Courtois B., Cota E.F., Charlot B., Lubaszewski M., Fault simulation of thermal MEMS, ISRN: TIMA-RR--99/05-2--FR, 1999
 
(2248) Cesario W., Flexible architectural synthesis, These de Doctorat, 1999
 
(2249) Dushina J., Formal verification of high level synthesis results, These de Doctorat, 1999
 
(2250) Georgelin P., Borrione D., Formal verification of VHDL using VHDL-like ACL2 models, Forum on Design Languages 1999, Lyon, France, 30 August - 3 September 1999, 1999
 
(2251) Palan B., Courtois B., Fundamental noise limits of ISFET-based microsystems, Eurosensors XIII, The 13th European Conference on Solid-State Transducers, The Hague, The Netherlands, 12-15 September 1999, 1999
 
(2252) Blanton R.D., Courtois B., Guest Editors' Introduction, IEEE Design and Test of Computers, Volume: 16, page: 16-17, 1999
 
(2253) Guyot A., Bernal A., Hardware implementation of M-ary modular exponentiation algorithm, XIV Conference on Design of Circuits and Integrated Systems (DCIS'99), Palmas de Mallorca, Spain, 17-20 November 1999, 1999
 
(2254) Rencz M., Szekely V., Courtois B., ICs, MCMs, and PWBs, The 1999 Southwest Symposium on Mixed-Signal Design (SSMD'99), Tucson, Arizona, USA, 11-13 April 1999, 1999
 
(2255) Anghel L., Nicolaidis M., Implementation and evaluation of a soft error detecting technique, The 5th IEEE International On-Line Testing Workshop, Rhodes, Greece, 5-7 July 1999, 1999
 
(2256) Charlot B., Mir S., Intégration de la conception et des methodologies de test pour le microsystèmes, ISRN: TIMA-RR--99/04-5--FR, 1999
 
(2257) Jerraya A. A., Hessel F., Le Marrec Ph., Romdhani A., Valderrama C., MCI - multilanguage distributed co-simulation tool, Distributed and Parallel Embedded Systems, 1999
 
(2258) Valderrama C., Le Marrec Ph., Hessel F., Romdhani A., Jerraya A. A., MCI - multilanguage distributed co-simulation tool, Distributed and Parallel Embedded Systems, Kluwer Academic Publishers, vol.25, 1999
 
(2259) Simeu E., Mesure de testabilité pour la synthèse de haut niveau, ISRN: TIMA-RR--99/04-2--FR, 1999
 
(2260) Abdelhay A., Simeu E., Méthode généralisée de test en ligne des systèmes digitaux linéaires, ISRN: TIMA-RR--99/04-1--FR, 1999
 
(2261) Palan B., Courtois B., Husak M., Vinci-Dos-Santos F., Microsystems for space applications, 1st International Conference on Advanced Engineering Design, Abstract proceedings, Prague, pp.133-134, 31 May - 2 June 1999. , 1999
 
(2262) Coste P., Romdhani A., Suescun R., Jerraya A. A., Sugar Z., Zergainoh N.-E., Le Marrec Ph., Hessel F., Multilanguage design of heterogeneous systems, Proceedings of the Seventh International Workshop on Hardware/Software Codesign CODES'99, 1999
 
(2263) Marchioro G.F., Jerraya A. A., Romdhani A., Le Marrec Ph., Hessel F., Coste P., Valderrama C., Daveau J.- M., Zergainoh N.-E., Multilanguage specification for system design and codesign, System-Level Synthesis, Kluwer Academic Publishers, Vol. 357, 1999
 
(2264) Ernst R., Jerraya A. A., Multi-language system design, Design, Automation and Test in Europe (DATE '99), 1999
 
(2265) Hessel F., Sugar Z., Suescun R., Jerraya A. A., Romdhani M., Le Marrec Ph., Zergainoh N.-E., Coste P., Multilanguage systems codesign, ISRN: TIMA-RR--99/01-2--FR, 1999
 
(2266) Guyot A., Abou-Samra S.-J., Multiple V dd combinatorial divider without DC to DC converter, ISRN: TIMA-RR--99/04-3--FR, 1999
 
(2267) Karam J.M., Mir S., Courtois B., Lubaszewski M., Szekely V., Rencz M., Multi-Purpose System-Level Simulation of MEMS, ISRN: TIMA-RR--99/01-1--FR, 1999
 
(2268) Palan B., Husak M., Courtois B., Karam J.M., Vinci-Dos-Santos F., New ISFET sensor interface circuit for biomedical applications, Sensors and Actuators B : Chemical, vol. 57, page: 63-68, 1999
 
(2269) Courtois B., Poppe A., Rencz M., Szekely V., New way for thermal transient testing [IC packaging], Fifteenth Annual IEEE Semiconductor Thermal-Measurement and Management Symposium , 1999
 
(2270) Husak M., Courtois B., Palan B., Vinci-Dos-Santos F., Noise analysis of ISFET based sensors, 3rd International Student Conference on Electrical Engineering POSTER'99, CTU in Prague, pp.130-131, 27 May 1999 , 1999
 
(2271) David J.P., Loquet J.G., Ecoffet R., Duzellier S., Cheynet P., Velazco R., One year SEU flight results for two 32KB commercial SRAMs on-board a scientific satellite, The 5th IEEE International On-Line Testing Workshop (IOLTW'99), Rhodes, Greece, 5-7 July 1999, pp.108-111, 1999
 
(2272) Rayane I., Nicolaidis M., Velasco-Medina J., On-line BIST for testing analog circuits, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors , 1999
 
(2273) Vergos H.-T., Nicolaidis M., Nikolos D., Haniotakis Th., Tsiatouhas Y., On path delay fault testing of multiplexer-based shifters, Proceedings Ninth Great Lakes-Symposium-on-VLSI., 1999
 
(2274) Mir S., Charlot B., On the integration of design and test for chips embedding MEMS, IEEE Design and Test of Computers, 16(4), page: 28-38, 1999
 
(2275) Cesario W., Suescun R., Sugar Z., Jerraya A. A., Overlap and frontiers between behavioral and RTL synthesis, Conference and Exhibition on Design, Automation and Test in Europe (DATE'99), Munich, Germany, 9-12 March 1999, 1999
 
(2276) Courtois B., Karam J.M., Bianchi R.A., Pressure and temperature integrated measurement system for high temperature oil well applications based on ALC crystal oscillators, 5th International Workshop Thermal Investigations of ICs and Systems, 1999
 
(2277) Courtois B., Bianchi R.A., Karam J.M., Pressure and Temperature Integrated Measurement System for High Temperature Oil Well Applications based on ALC Crystal Oscillators, ISRN: TIMA-RR--99/06-1--FR, 1999
 
(2278) Courtois B., Markus K., Proceedings of Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, Paris,France, 30 March-1st April 1999, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 189 pages, 1999
 
(2279) Paschalis A., Nikolos D., Abraham J., Nicolaidis M., Proceedings on 5th IEEE International On-Line Testing Workshop (IOLT'99), July 5-7, Rhodes, Greece, , 239 pages, 1999
 
(2280) Rencz M., Lasance C., Szekely V., Courtois B., Proceedings on 5th International Workshop on THERMAL INVESTIGATIONS of ICs and MICROSTRUCTURES (THERMINIC 1999) October 3-6, 1999,ROME, Italy, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 370 pages, 1999
 
(2281) Ribas R.P., Veychard D., Courtois B., Karam J.M., Providing technology infrastructure for MEMS, Proceedings of the SPIE The International Society for Optical Engineering, 1999
 
(2282) Bacivarov L., Goncalves A., Balme L., Quality management, assurance and education. European dimensions, Inforec Press, , 1999
 
(2283) Goncalves A., Balme L., Bacivarov L., Quality management, assurance and education. European dimensions, Inforec Press, Romania, , 5-13, 1999
 
(2284) Koga R., Velazco R., Yu P., Alvarez M.T., Crain S.H., Bofill A., Radiation effects in a fixed-point digital signal processor, IEEE Radiation Effects Data Workshop.-Workshop-Record. Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference, 1999
 
(2285) Clermidy F., Reliability improvement of SIMD parallel computers by test and structural fault-tolerance, These de Doctorat, 1999
 
(2286) Nicolaidis M., Zorian Y., Scaling deeper to submicron: on-line testing to the rescue, Design Automation and Test in Europe Conference and Exhibition 1999, 1999
 
(2287) Vinci-Dos-Santos F., Palan B., Husak M., Courtois B., Karam J.M., Sensor interface circuit for ISFET based sensors, Journal of Solid-State Devices and Circuits, 7(1); feb. 1999, page: 17-23, 1999
 
(2288) Roche F.M., Cosculluela J., Monnier T., Velazco R., SEU testing of a novel hardened register implemented using standard CMOS technology, IEEE Transactions on Nuclear Science, Dec. 1999; Volume 46, page: 1440 - 1444, 1999
 
(2289) Georgelin P., Simulation symbolique et preuve de descriptions VHDL avec ACL2, ISRN: TIMA-RR-99/04-7--FR, 1999
 
(2290) Rencz M., Szekely V., Courtois B., Simulation, testing and modeling of the thermal behavior and electro-thermal interactions in ICs, MCMs and PWBs, Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999
 
(2291) Faccio F., Velazco R., Nicolaidis M., Cosculluela J., Calin T., Marchioro A., Kloukinas K., Single event effects in static and dynamic registers in a 0.25 mu m CMOS technology, IEEE Transactions on Nuclear Science, Dec. 1999, Volume: 46, page: 1434-1439, 1999
 
(2292) Ubar R., Borrione D., Single gate design error diagnosis in combinational circuits, Proceedings of the Estonian Academy of Sciences Engineering, March ; 5(1), page: 3-21, 1999
 
(2293) Chaahoub F., Study of design methods and CAD tools for analog integrated circuits, These de Doctorat, 1999
 
(2294) Cheynet P., Study of the robustness of the intelligent control facing with radiation induced faults, These de Doctorat, 1999
 
(2295) Velazco R., Cheynet P., Gordon M.B., Godin C., Torres-Alegre S., Andina D., Study of two ANN digital implementations of a radar detector candidate to an on-board satellite experiment, International Work Conference on Artificial and Natural Neural Networks, IWANN'99., 1999
 
(2296) Leveugle R., Ubar R., Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation, Electron Technology, 32(3), page: 282-7, 1999
 
(2297) Jerraya A. A., Mermet J., System-Level Synthesis: Proceedings of the NATO Advanced Study Institute on System Level Sythesis for Electronic Design, held in Il Ciocco, Lucca, Italy, 11-12 August 1998, Kluwer Academic Publishers, , 1999
 
(2298) Mermet J., Morawiec A., Techniques for improving the HDL simulation performance, Forum on Design Languages FDL'99, Lyon, France, 30 August -3 September, 1999, (Best Poster Award, 1999
 
(2299) Rencz M., Courtois B., Szekely V., Thermal investigations of ICs and Microstructures, "Encyclopedia of Microcomputers", a multi-volume work, Executive Ed. A. Kent, J.G. Williams, Marcel Dekker Inc. of New York, , 1999
 
(2300) Pahi A., Rencz M., Szekely V., Courtois B., Thermal monitoring and testing of electronic systems, IEEE Transactions on Components and Packaging Technologies, 22; June 1999, page: 231 - 237, 1999
 
(2301) Rencz M., Courtois B., Szekely V., Thermal transient evaluation of packages with the TTMK toolkit, The PACIFIC RIM / ASME International, Intersociety Electronic Packaging Conference, InterPACK'99, Maui, Lahaina, Hawaii, USA, 13-19 June 1999, 1999
 
(2302) Leclercq J.L., Ribas R.P., Veychard D., Courtois B., Thermopile-based GaAs micromachined devices, International Conference on Microelectronics and Packaging (SBMicro'99), Campinas, Brazil, 3-6 August 1999, Technical Digest, pp. 238-243, 1999
 
(2303) Nicolaidis M., Time redundancy based soft-error tolerance to rescue nanometer technologies, Proceedings 17th IEEE VLSI Test Symposium, 1999
 
(2304) Rencz M., Courtois B., Szekely V., Tool and method for the thermal transient evaluation of packages, Proceedings of the SPIE The International Society for Optical Engineering, 1999
 
(2305) Ress S., Poppe A., Benedek Zs., Courtois B., Szekely V., Rencz M., Torki K., Töröka S., Transient thermal measurements for dynamic package modeling: new approaches, 5th International Workshop Thermal Investigations of ICs and Systems, 1999
 
(2306) Coderch N., Cueto J., Velazco R., Cheynet P., Rezgui S., Un système de test pour la qualification de circuits intégrés destinés à fonctionner en environnement sévère, ISRN: TIMA-RR--99/04-6--FR, 1999
 
(2307) Abou-Samra S.-J., Aisa P.A., Courtois B., Guyot A., 3D CMOS SOI for high performance computing, International Symposium on Low Power Electronics and Design, 1998
 
(2308) Courtois B., Szekely V., Rencz M., 3rd International Workshop on THERMAL INVESTIGATIONS of ICs and MICROSTRUCTURES (THERMINIC 1997), September 21-23, Cannes, , Elsevier, Vol. 28, N° 4, May 1997, 1998
 
(2309) Rencz M., Szekely V., Courtois B., 3rd International Workshop on THERMAL INVESTIGATIONS of ICs and MICROSTRUCTURES (THERMINIC 1997), September 21-23, Cannes, "Côte d'Azur", France: , Volume, Elsevier, Issues 1-2 , November, 157 p., 1998
 
(2310) Szekely V., Courtois B., Rencz M., 4 th International Worshop on Thermal Investigations of ICs and Microstructures, THERMINIC, Cannes, France, TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, , 1998
 
(2311) Mir S., Bertrand Y., Lubaszewski M., Renovell M., Azais F., A built-in multi-mode stimuli generator for analogue and mixed-signal, XI Brazilian Symposium on Integrated Circuit Design (SBCCI'98), Buzios, Rio de Janeiro, Brazil, September 30 - October 3, 1998, Institute of Electrical & Electronics Enginee, Brazil , 175 - 178, 1998
 
(2312) Mir S., Bertrand Y., Lubaszewski M., Renovell M., Azais F., A built-in multi-mode stimuli generator for analogue and mixed-signal testing, Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on, 1998
 
(2313) Vinci-Dos-Santos F., Courtois B., Dent T., Krim N., Pearson I., A combined approach to the support of SMEs, Advances in information technologies : the Business Challenge, J.-Y. Roger et al. (Eds.), IOS Press, , 1998
 
(2314) Szekely V., Glesner M., Rodriguez J., Hofmann K., Rencz M., Karam J.M., Courtois B., Cao A., Boutamine H., A composite integrated mixed-technology design environment to support micro electro mechanical systems development, The First International Conference on Modeling and Simulation of Microsystems, Semiconductors, Sensors and Actuators, MSM'98, Santa Clara Marriott, California, USA, April 5-8, 1998, 1998
 
(2315) Amblard P., A finite state description of the earliest logical computer : the Jevons'Machine, Mixed design of integrated circuits and systems, A. Napieralski, Z. Ciota, A. Martinez, G. de Mey, J. Cabestany (Eds), 1998, Kluwer Academic Publishers, 256 p., 1998
 
(2316) Valderrama C., Tsasakou S., Birbas M., Karathanasis H., Voros N.S., Arab M.- S., Birbas A.N, A hardware/software co-design methodology for embedded telecommunication systems, Conference on European Multimedia, Microprocessor Systems and Electronic Commerce (EMMSEC'98), Bordeaux, France, September 1998, 1998
 
(2317) Mir S., Renovell M., Lubaszewski M., Bertrand F., Azais F., A multi-mode stimuli generator for analogue and mixed-signal built-in-self-test, 4th IEEE International Mixed Signal Testing Workshop, The Hague, The Netherlands, June 1998, 1998
 
(2318) Leveugle R., Brahic P., Analysis of defect tolerant crossbar network implementations [MCM], BEC '98. Proceedings. 6th Biennial Conference on Electronics and Microsystems Technology, 1998
 
(2319) Lubaszewski M., Velasco-Medina J., Nicolaidis M., An approach to the on-line testing of operational amplifiers, Proceedings Seventh Asian Test Symposium ATS'98 Cat. No.98TB100259., 1998
 
(2320) Daniau W., Basrour S., De Labacherie M., Soumann V., Suzuki K., Ataka M., Fujita H., Nakamura S., An electrostatic microactuator using LIGA process for a magnetic head tracking system of hard disk drives, Microsystem Technologies, 5(2), page: 69-71, 1998
 
(2321) Karam J.M., Vinci-Dos-Santos F., Courtois B., Husak M., Palan B., A new ISFET sensor interface circuit, Eurosensors XII. Proceedings of the 12th European Conference on Solid State Tranducers and the 9th UK Conference on Sensors and their Applications., 1998
 
(2322) Bernal A., Guyot A., A new low-power GaAs two-single-port memory cell, IEEE Journal of Solid State Circuits, July ; 33(7), page: 1103-10, 1998
 
(2323) Courtois B., Karam J.M., Hofmann K., Cao A., An integrated mixed-technology design environment to support micro electro mechanical systems development, Proceedings of the SPIE The International Society for Optical Engineering, 1998
 
(2324) Rencz M., Szekely V., Courtois B., Application results of a new thermal benchmark chip, SEMITHERM'98, Semiconductor Thermal Measurement and Management Symposium, San Diego, California, 10-12 March 1998, 1998
 
(2325) Jemai A., Jerraya A. A., Kission P., Architectural simulation in the context of behavioral synthesis, Proceedings.-Design,-Automation-and-Test-in-Europe, 1998
 
(2326) Lubaszewski M., Courtois B., A Reliable Fail-Safe System, IEEE Transactions on Computers, February 1998; Vol. 47, page: 236-241, 1998
 
(2327) Renaudin M., Robin F., Vivet P., ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor, Proceedings. Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems Cat. No.98EX138, 1998
 
(2328) Dent T., Krim N., Pearson I., Assisting SMEs to exploit their intellectual property - the ASSISTEC project, European Multimedia, Microprocessor Systems and Electronic Commerce (EMMSEC'98) Conference and Exhibition, Bordeaux, France, 28-30 September 1998, , 1998
 
(2329) Vaucher Ch., Houelle A., Mehrez H., Guyot A., Aberbour M., A time driven adder generator architecture, 9th IFIP International Conference on VLSI, VLSI'97, Gramado, RS, Brazil, 26-29 August 1997, 1998
 
(2330) Benmohammed M., Jerraya A. A., Rahmouni M., Liem Cl. B., Kission P., Automatic generation of reprogrammable controllers in a high level synthesis environment, Technique et Science Informatiques (TSI), Dec. 1998; 17(10), page: 1277-97, 1998
 
(2331) Nacabal F., Valderrama C., Jerraya A. A., Paulin P., Automatic VHDL-C Interface Generation for Distributed Cosimulation: Application to Large Design Examples, Design Automation for Embedded Systems, June 1998, Volume 3, Numbers 2-3, page: 199-217, 1998
 
(2332) Mermet J., A wordwide IP exchange network : WIN, IFIP 98 World Congress, Vienna and Budapest, 30 August - 6 September 1998, 1998
 
(2333) Leveugle R., Behavior modeling of faulty complex VLSIs: why and how?, BEC '98. Proceedings. 6th Biennial Conference on Electronics and Microsystems Technology, 1998
 
(2334) Leclercq J.L., Ribas R.P., Karam J.M., Courtois B., Viktorovitch P., Bulk micromachining characterization of 0.2 mu m HEMT MMIC technology for GaAs MEMS design, Materials Science & Engineering B Solid State Materials for Advanced Technology., 1998
 
(2335) Morissey A., Karam J.M., Glesner M., Rencz M., Szekely V., Alderman J., Lubaszewski M., Kelly G., Courtois B., Hofmann K., CAD, CAT and MPW for MEMS, Eighth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'98), Sendai, Japan, 19-20 October 1998, 1998
 
(2336) Krim N., Courtois B., Conq B., CADnet framework: an open platform for multidisciplinary and collaborative design, European Multimedia, Microprocessor Systems and Electronic Commerce (EMMSEC'98), Conference and Exhibition, Bordeaux, France, 28-30 September 1998, 1998
 
(2337) Rencz M., Glesner M., Szekely V., Lubaszewski M., Karam J.M., Courtois B., Hofmann K., CAD tools and foundries to boost microsystems development, Materials Science and Engineering B-Solid State Materials For Advanced Technology , 7 Feb. 1998; B51(1-3):, page: 242-53, 1998
 
(2338) Gordon M.B., Ecoffet R., Perrenot F., Cabestany J., El Chakik F., Muller J.D., Cheynet P., Velazco R., Classical vs neural approaches for on-board satellite image analysis, novel intelligent automation and control systems, In Eds. America Latina Formacion Academica, Hrsg. von J. Pfeiffer, Papierflieger, Clausthal-Zellerfeld, Vol. I, , , 1998
 
(2339) Karam J.M., Sifflet S., Pressecq F., Courtois B., Vinci-Dos-Santos F., Bianchi R.A., CMOS-compatible smart temperature sensors, Microelectronics journal, September 1998, page: 627-636, 1998
 
(2340) Courtois B., Pressecq F., Sifflet S., Bianchi R.A., Vinci-Dos-Santos F., Karam J.M., CMOS compatible temperature sensor based on the lateral bipolar transistor for very wide temperature range applications, Sensors and Actuators A : Physical, Nov. 1998; A71(1-2):, page: 3-9, 1998
 
(2341) Souani C., Tourki R., Zitouni A., Abid M., Torki K., Communication synthesis approach for distributed systems and its application during the design of a communication controller, Proceedings of the Tenth International Conference on Microelectronics. 14-16 Dec.Monastir, TN, 1998
 
(2342) Saucier G., Ubar R., Leveugle R., Compaction of decision diagrams for describing multi-process VHDL descriptions, BEC '98. Proceedings. 6th Biennial Conference on Electronics and Microsystems Technology, 1998
 
(2343) Tomaszewicz P., Amblard P., Rawski M., Comparison of different decomposition techniques of a digital circuit - A case study , 5th International Conference MIXDES 98, Lodz, Poland, 18-20 June 1998, 1998
 
(2344) Jerraya A. A., Diaz-Nava M., Moussa I., Cost evaluation in the design for reuse context, 2nd GI/ITG/GMM-Workshop, Reuse Techniques for VLSI Design, Karlsrube, Germany, 14 September 1998, 1998
 
(2345) Guyot A., Cours d'opérateurs arithmétiques, , , 1998
 
(2346) Nicolaidis M., Velasco-Medina J., Current-based testing for analog and mixed-signal circuits, Proceedings International Conference on Computer Design. VLSI in Computers and Processors Cat. No.98CB36273, 1998
 
(2347) Mir S., Velasco-Medina J., Nicolaidis M., Current-based testing for high-frequency CMOS operational amplifiers, XIII International Conference on Design of Circuits and Integrated Systems DCIS'98, Madrid, Spain, November 1998, 1998
 
(2348) Nicolaidis M., Velasco-Medina J., Mir S., Current-testable high-frequency CMOS operational amplifiers, Proceedings Eleventh Annual IEEE International ASIC Conference, 1998
 
(2349) Torki K., Deep sub-micron technologies from CMP service , International Conference on Microelectronics (ICM'98), Monastir, Tunisia, 14-16 December, 1998, 1998
 
(2350) Nicolaidis M., Design for soft-error robustness to rescue deep submicron scaling, Proceedings International Test Conference 1998 IEEE Cat. No.98CH36270., 1998
 
(2351) Guyot A., Bernal A., Design of a modular multiplier based on Montgomery's algorithm, 13th Conference on Design of Circuits and Integrated Systems (DCIS'98) Madrid, Spain, 17-20 November 1998, 1998
 
(2352) Djemal R., Atri M., Torki K., Abid M., Tourki R., Design of an adaptive flow control algorithm for ATM networks, International Conference on Microelectronics (ICM'98), Monastir, Tunisia, 14-16 December 1998, 1998
 
(2353) Duarte R.O., Nicolaidis M., Design of fault-secure parity-prediction Booth multipliers, Proceedings. Design, Automation and Test in Europe Cat. No.98EX123, 1998
 
(2354) Vinci-Dos-Santos F., Design rechniques for radiation-hardening of ICs, These de Doctorat, 1998
 
(2355) Ecoffet R., Beck K., Velazco R., Rezgui S., Peters L., Cheynet P., Digital fuzzy control: a robust alternative suitable for space application, IEEE Transactions on Nuclear Science, Dec. 1998; 45(6) pt. 1, page: 2941-7, 1998
 
(2356) Velazco R., Buchner S., Ecoffet R., Beck K., Peters L., Rezgui S., Digital fuzzy control: a robust alternative suitable for space application, IEEE Nuclear and Space Radiation Effects Conference (NSREC'98), Newport Beach, USA, 20-24 July 1998, 1998
 
(2357) Zorian Y., Duarte R.O., Nicolaidis M., Bederr H., Efficient fault-secure shifter design, JETTA - Journal of Electronic Testing: Theory and Application, vol. 12/April, page: , 1998
 
(2358) Zorian Y., Nicolaidis M., Bederr H., Duarte R.O., Efficient totally self-checking shifter design, Journal of Electronic Testing: Theory and Applications, Feb.-April ; 12(1-2), page: 29-39, 1998
 
(2359) Fouillat P., Sarger L., Lewis D., Maidon Y., Calin T., Pouget V., Velazco R., Lapuyade H., Elaboration of a new pulsed laser system for SEE testing , IEEE International On-Line Testing Workshop (IOLTW'98), Capri, Italy, 6-8 July 1998, 1998
 
(2360) Morawiec A., Gore T., Emerging standards for IP Reuse, Conference on Intellectual Property in Electronics (IP'97), Santa Clara, CA, USA, 17-18 March 1998, 1998
 
(2361) Nicolaidis M., Fail-safe interfaces for VLSI: theoretical foundations and implementation, IEEE Transactions on Computers, Jan. ; 47(1), page: 62-77, 1998
 
(2362) Veychard D., Mir S., Karam J.M., Courtois B., Castillejo A., Failure Mechanisms and Fault Classes for CMOS-Compatible Microelectromechanical Systems, Proceedings International Test Conference 1998, 1998
 
(2363) Velasco-Medina J., Calin T., Nicolaidis M., Fault detecion for linear analog circuits using current injection, Proceedings Design, Automation and Test in Europe, 23-26 Feb. 1998, 1998
 
(2364) Velazco R., Ecoffet R., Cheynet P., Buchner S., Flight results analysis of digital experiment devoted to satellite image processing by means of neural nets, IEEE International On-Line Testing Workshop (IOLTW'98), Capri, Italy, 6-8 July 1998, 1998
 
(2365) Borrione D., Pierre L., Dushina J., Formalization of finite state machines with data path for the verification of high-level synthesis, Proceedings. XI Brazilian Symposium on Integrated Circuit Design Cat. No.98EX216, 1998
 
(2366) Renovell M., Nicolaidis M., Kochs H.-D., Grosspietsch K.-E., Maier J., Abraham J., From dependable computing systems to computing for integrated dependable systems?, Digest of Papers. Twenty Eighth Annual International Symposium on Fault Tolerant Computing Cat. No.98CB36224, 1998
 
(2367) Borrione D., Ubar R., Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault model, Proceedings. XI Brazilian Symposium on Integrated Circuit Design Cat. No.98EX216, 1998
 
(2368) Guyot A., Bernal A., Hardware for computing modular multiplication algorithm, ESSCIRC '98. Proceedings of the 24th European Solid State Circuits Conference., 1998
 
(2369) Le Marrec Ph., Cayrol O., Attia M., Jerraya A. A., Hessel F., Valderrama C., Hardware, software and mechanical cosimulation for automotive applications, Proceedings. Ninth International Workshop on Rapid System Prototyping, 1998
 
(2370) Changuel A., Abid M., Jerraya A. A., Valderrama C., Hardware-software codesign methodology starting from C/VHDL models, Technique et Science Informatiques (TSI), Feb. 1998; 17(2), page: 157-80, 1998
 
(2371) Daveau J.- M., Marchioro G.F., Jerraya A. A., Hardware/software co-design of an ATM network interface card: a case study, International Conference on Hardware Software Codesign archive Proceedings of the 6th international workshop on Hardware/software codesign, 1998
 
(2372) Voros N.S., Andritsou A., Valderrama C., Mariatos V., Tsasakou S., Birbas M., Arab M.- S., Birbas A.N, Hardware/software co-design of embedded systems using multiple formalisms for application development, IFIP International Conference FORTE/PSTV'98, Formal description Techniques & Protocol Specification, Testing and Verification, Paris, France, 3-6 November 1998, 1998
 
(2373) Jerraya A. A., Marchioro G.F., Zergainoh N.-E., Hw/Sw codesign of an ATM network interface card starting from a system level specification, URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings, 1998
 
(2374) Courtois B., Török S., Rencz M., Szekely V., IDDQ testing of submicron CMOS by cooling, Seventh Asian Test Symposium (ATS'98), Singapore, 2-4 December 1998, 1998
 
(2375) Rencz M., Courtois B., Török S., Szekely V., IDDQ testing of submicron CMOS by cooling, ISRN: TIMA-RR-98/09-1--FR, 1998
 
(2376) Ostier P., Dumitrescu E., Identification of non-redundant memorizing elements in VHDL synchronous designs for formal verification tools, Fifth International Workshop on Symbolic Methods and Applications in Circuit Design (SMACD'98), Kaiserslautern, Germany, 8-9 October 1998, 1998
 
(2377) Ribas R.P., Viktorovitch P., Karam J.M., Leclercq J.L., III-V micromachined devices for mycrosystems, Microelectronics journal, vol. 29, page: , 1998
 
(2378) Karam J.M., Husak M., Courtois B., Palan B., Vinci-Dos-Santos F., Integrated microsystem for biomedical applications, 7th Annual university-wide seiminar Workshop 98, Czech Technical University, Prague, February 3-5, 1998, 1998
 
(2379) Ubar R., Borrione D., Localization of single gate design errors in combinational circuits by diagnostic information about stuck-at faults, Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'98), Szczyrk, Poland, 2-4 September 1998, 1998
 
(2380) Courtois B., Krim N., Low cost access to advanced technologies for prototyping and small volume, European Multimedia, Microprocessor Systems and Electronic Commerce (EMMSEC'98), Conference and Exhibition, Bordeaux, France, 28-30 September 1998, 1998
 
(2381) Abou-Samra S.-J., Low energy integrated circuit design in 2D and 3D SOI technologies : applied to arithmetics, These de Doctorat, 1998
 
(2382) Guyot A., Abou-Samra S.-J., Low power CMOS digital design, Proceedings of the Tenth International Conference on Microelectronics Cat. No.98EX186, 1998
 
(2383) Abou-Samra S.-J., Arweiler J., Guyot A., Low power SOI CMOS multipliers: 2D vs. 3D, ESSCIRC '98. Proceedings of the 24th European Solid State Circuits Conference., 1998
 
(2384) Perez Ribas R., Maskless front-side bulk micromachining compatible with standard GaAs IC technology, These de Doctorat, 1998
 
(2385) Cao A., Backhaus D., Karam J.M., Rodriguez J., Oudinot J., MEMS : the new challenge for the electronic design automation vendors, The International Conference on Advanced Microsystems for Automotive Applications, Berlin, Germany, 26-27 March 1998, 1998
 
(2386) Jerraya A. A., Abid M., Ben Ismail T., Changuel A., Valderrama C., Romdhani A., Marchioro G.F., Daveau J.- M., Methodology for design of embedded systems, Integrated Computer Aided Engineering, 5(1), page: 69-83, 1998
 
(2387) Leclercq J.L., Bennouri N., Karam J.M., Ribas R.P., Lescot J., Courtois B., Micromachined planar spiral inductor in standard GaAs HEMT MMIC technology, IEEE Electron Device Letters, Aug. 1998; 19(8), page: 285-7, 1998
 
(2388) Karam J.M., Micromechanical ring oscillator sensor, GB2318231, 1998
 
(2389) Karam J.M., Microsystems CAD, Ninth-Micromechanics-Europe-Workshop.-MME'98.-Proceedings, 3-5 June 1998, Ulvik, Norway, 1998
 
(2390) Cota E.F., Lubaszewski M., Courtois B., Microsystems testing: an approach and open problems, Design, Automation, and Test in Europe archive Proceedings of the conference on Design, automation and test in Europe, 1998
 
(2391) Tchoumatchenko V., Modeling, architecture and tools for fast adders synthesis, These de Doctorat, 1998
 
(2392) Lescot J., Ribas R.P., Karam J.M., Ndagijimana F., Leclercq J.L., Monolithic micromachined planar spiral transformer, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 Cat. No.98CH36260, 1998
 
(2393) Courtois B., Multidisciplinary and collaborative design for systems on silicon, FED-PDI Joint Conference on 21st Century Election Devices, Berlin, Germany, 29 June - 2 July 1998, 1998
 
(2394) Valderrama C., Coste P., Hessel F., Le Marrec Ph., Romdhani M., Jerraya A. A., Marchioro G.F., Daveau J.- M., Zergainoh N.-E., Multilanguage specification for system design and codesign, ISRN: TIMA-RR--98/12-1--FR, 1998
 
(2395) Guyot A., Montalvo L.-A., Parhi K.-K., New Svoboda-Tung division, IEEE Transactions on Computers, Sept. ; 47(9), page: 1014-20, 1998
 
(2396) Zorian Y., Nicolaidis M., On Line-Testing for VLSI, Kluwer Academic Publishers, , 1998
 
(2397) Zorian Y., Nicolaidis M., On-line testing for VLSI-a compendium of approaches, Journal of Electronic Testing: Theory and Applications, Feb.-April ; 12(1-2), page: 7-20, 1998
 
(2398) Nicolaidis M., On-line testing for VLSI: state of the art and trends, Integration, the VLSI Journal, Dec. ; 26(1-2), page: 197-209, 1998
 
(2399) Guyot A., Aberbour M., Vaucher N., Houelle A., Mehrez H., On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, March ; 6(1), page: 114-21, 1998
 
(2400) Ecoffet R., Cheynet P., Velazco R., Operation in space of artificial neural networks implemented by means of a dedicated architecture based on a transputer, Proceedings. XI Brazilian Symposium on Integrated Circuit Design, 1998
 
(2401) Abou-Samra S.-J., Guyot A., Performance/complexity space exploration : Bulk vs. SOI, 8th International Workshop Power and Timing Modeling Optimization and Simulation (PATMOS'98), Copenhagen, Denmark, October 1998, 1998
 
(2402) Abou-Samra S.-J., Guyot A., Power consumption in digital circuits, 3rd International Conference on ASIC (ASICON'98), Beijing,China, 20-23 October 1998, 1998
 
(2403) Nikolos D., Nicolaidis M., Sonza Reorda M., Proceedings on 4th IEEE International On-Line Testing Workshop, July 6-8, Capri, Italy (IOLT 1998), IEEE Computer Society, 260 pages, 1998
 
(2404) Cheynet P., Ecoffet R., Velazco R., Pulsed laser validation of recovery mechanisms of critical SEE's in an artificial neural network system, RADECS-97, 1998
 
(2405) Muller J.D., Ecoffet R., Mellinger J., Mcmorrow D., Velazco R., Cheynet P., Olmos M., Buchner S., Pulsed laser validation of recovery mechanisms of critical SEEs in an artificial neural network system, IEEE Transactions on Nuclear Science, June 1998; 45(3) pt. 3, page: 1501-7, 1998
 
(2406) Peters L., Olmos S., Ecoffet R., Cheynet P., Rubio J.-C., Cabestany J., Beck K., Velazco R., Radiation tolerance of a fuzzy controller, Engineering of Intelligent Systems, (EIS'98), Tenerife, Spain, 11-13 February 1998, 1998
 
(2407) Lubaszewski M., Courtois B., Reliable fail-safe systems, IEEE Transactions on Computers, February 1998 ; Vol. 47, page: 236-241, 1998
 
(2408) Simeu E., Residual checking method for concurrent fault detection in linear analog systems, 4th IEEE International On-Line Testing Workshop, Capri, Italy, July 6-7, 1998, 1998
 
(2409) Guyot A., Vassileva T., Tchoumatchenko V., Reuse and customisation of parallel prefix adders, International Workshop on IP Based Synthesis and System Design (IWLAS'98), Grenoble, France, 15-16 December 1998, 1998
 
(2410) Velazco R., Cheynet P., Robustness of digital intelligent control in space: from ground simulations towards on-board satellite experiments, 8th Latin American Congress on Automatic Control (CLCA'98), Viña del Mar, Chile, 9-13 November 1998, 1998
 
(2411) Asenek V., Cheynet P., Ecoffet R., Oldfield M., Rezgui S., Velazco R., Underwood C., SEU induced errors observed in microprocessor systems, IEEE Transactions on Nuclear Science, Dec. 1998; 45(6) pt. 1, page: 2876-83, 1998
 
(2412) Underwood C., Ecoffet R., Cheynet P., Asenek V., Oldfield S., Velazco R., Rezgui S., SEU induced errors observed in microprocessor systems, IEEE Nuclear and Space Radiation Effects Conference (NSREC'98), Newport Beach, USA, 20-24 July 1998, 1998
 
(2413) Rodriguez S., Velazco R., Bofill A., Alvarez M., Ecoffet R., Cheynet P., Space qualification of an architecture based on a digital signal processor for a nanosat project, 6th International Workshop on Digital Signal Processing Techniques For Space (DSP'98), Noordwijk, The Netherlands, 23-25 September 1998, 1998
 
(2414) Courtois B., Karam J.M., Ribas R.P., Study of suspended microstrip and planar spiral inductor built using GaAs compatible micromachining, Journal of Solid-State Devices and Circuits, Feb. 1998; 6(1), page: 11-16, 1998
 
(2415) Torki K., Saulnier S., Sub-micron CMOS CAD implementation of accurate timing models, 3rd International Conference on ASIC (ASICON'98), Beijing,China, 20-23 October 1998, 1998
 
(2416) Torki K., Submicronics technology: the services available from CMP, Proceedings-of-the-Tenth-International-Conference-on-Microelectronics-Cat.-No.98EX186.Monastir, TN, 1998
 
(2417) Vazquez D., Huertas J.L., Mir S., Rueda A., Switch-level fault coverage analysis for switched-capacitor systems, Proceedings. Design, Automation and Test in Europe Cat. No.98EX123, 1998
 
(2418) Velazco R., The Alfa-Huerta project, Proceedings. XI Brazilian Symposium on Integrated Circuit Design , 1998
 
(2419) Torki K., Tourki R., Abid M., Souani C., The design of MAC unit for DWT implementation, Proceedings-of-the-Tenth-International-Conference-on-Microelectronics-Cat.-No.98EX186.Monastir, TN, 1998
 
(2420) Ronge K., Krim N., The needs of small and medium sized companies in embedded systems, Advances in information technologies : the Business Challenge, J.-Y. Roger et al. (Eds.), IOS Press, , 1998
 
(2421) Lubaszewski M., Courtois B., Szekely V., Rencz M., Karam J.M., Thermal monitoring of self-checking systems, Journal of Electronic Testing: Theory and Applications, Feb.-April 1998; Volume 12, Numbers 1-2, page: 81-92, 1998
 
(2422) Rencz M., Szekely V., Courtois B., Thermal monitoring through boundary-scan , IMAPS Advanced Technology Workshop on MCM Test V, Napa Valley, California, 20-23 September 1998, 1998
 
(2423) Pahi A., Hajder Sz., Szekely V., Poppe A., Rencz M., Thermal simulation tools for microsystem elements, The First International Conference on Modeling Simulation of Microsystems, Semiconductors, Sensors and Actuators, MSM'98, Santa Clara Marriott, California, USA, April 5-8, 1998, 1998
 
(2424) Rencz M., Courtois B., Szekely V., Thermal transient testing of packages without a tester, Proceedings of 2nd Electronics Packaging Technology Conference Cat. No.98EX235, 1998
 
(2425) Rencz M., Courtois B., Szekely V., Thermal transient testing without a tester, SEMICON West 98, Technical Symposium on Semiconductor Packaging Technology, San Jose, CA, USA, 15-17 July 1998, 1998
 
(2426) Paillotin J.-F., Torki K., Courtois B., Delori H., Karam J.M., The services available from CMP, 3rd International Conference on ASIC (ASICON'98), Beijing,China, 20-23 October 1998, 1998
 
(2427) Cheynet P., Ecoffet R., Velazco R., Bofill A., THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment , IEEE European Test Workshop (ETW'98), Barcelone, Spain, 27-29 May 1998, 1998
 
(2428) Marwedel P., Newton C., Ramming F.-J., Mermet J., Borrione D., Lefaou C., Three decades of hardware description languages in Europe, Journal of Electrical Engineering and Information Science, Dec. ; 3(6), page: 700-23, 1998
 
(2429) Nacabal F., Tools for exploration of embedded programmable architectures in industrial applications, These de Doctorat, 1998
 
(2430) Nicolaidis M., Velazco R., Moss S., Koga R., Tran V.T., La Lumondiere S.D., Calin T., Clark K., Topology-related upset mechanisms in design hardened storage cells, RADECS-97, 1998
 
(2431) Nicolaidis M., Faccio F., Velazco R., Campbell M., Cosculluela J., Snoeys W., Noah E., Calin T., Giraldo A., Anelli G., Kouklinas K., Jarron P., Delmastro M., Moreira P., Marchioro G.F., Total dose and Single Event Effects (SEE) in a 0.25 µm CMOS technology, Fourth Workshop on electronics for LHC experiments, Universita La Sapienza, Roma, Italy, 21-25 September 1998, 1998
 
(2432) Courtois B., Szekely V., Rencz M., Tracing the Thermal Behavior of ICs, IEEE Design and Test of Computers, April-June 1998 ; Vol. 15, page: 14-21, 1998
 
(2433) Marchioro G.F., Ismail T.B, Daveau J.- M., Jerraya A. A., Transformational partitioning for codesign, Proceedings Computers and Digital Techniques, May 1998; 145(3), page: 181-95, 1998
 
(2434) Marchioro G.F., Transformational partitioning for the co-design of mixed hardware/software systems, These de Doctorat, 1998
 
(2435) Zergainoh N.-E., Jerraya A. A., Marchioro G.F., Daveau J.- M., Using SDL for hardware/software co-design of an ATM network interface card, 1st Workshop of the forum society on SDL and MSC, Berlin, Germany, 29 June -1 July 1998, 1998
 
(2436) Bara S., Zimmermann J., Negoi A.C., Guyot A., Virtual device : a new approach in microelectronics device education, 2nd European Workshop on Microelectronics Education (EWME'98), Noordwijkerhout, The Netherlands, 14-15 May 1998, 1998
 
(2437) Valderrama C., Virtual prototyping for the generation of mixed hardware/software architecture, These de Doctorat, 1998
 
(2438) Courtois B., Rencz M., Szekely V., 2nd International Workshop onTHERMAL INVESTIGATIONS of ICs and MICROSTRUCTURES (THERMINIC 1996), September 25-27,Budapest Hungary: Special Issue, IEEE Transactions on VLSI Systems, IEEE Computer Society, Vol. 5, N° 3, Sept., 250-343, 1997
 
(2439) Rueda A., Mir S., Huertas J.L., Liberali V., A BIST technique for sigma-delta modulators based on circuit reconfiguration, Proceedings of 1997 IEEE 3rd International Test Mixed Signal Testing Workshop, 1997
 
(2440) Nicolaidis M., Alzaher-Noufal I., Duarte R.O., A CAD framework for efficient self-checking data path design, 3rd IEEE International On-Line Testing Workshop, Aghia Pelaghia Headland, Crete, Greece, 7-9 July 1997, 1997
 
(2441) Courtois B., Access to microsystem technology: the CMP services solution, Microelectronics journal, Volume 28 1997, page: 407-417, 1997
 
(2442) Guyot A., Negoi A.C., Zimmermann J., A dedicated circuit for charged particles simulation using the Monte Carlo method, Proceedings. IEEE International Conference-on-Applications Specific Systems, Architectures and Processors. Cat. No.97TB100177. 1997:, 1997
 
(2443) Hochet B., Guyot A., Kanan R., Declercq M., A divided decoder-matrix (DDM) structure and its application to a 8 kb GaAs MESFET ROM, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age. ISCAS '97 Cat. No.97CH35987., 1997
 
(2444) Mohamed F., A fuzzy logic-based approach for the test and the diagnosis of analog circuits, These de Doctorat, 1997
 
(2445) Kamga A., Simeu E., A good choice of a path following controller for an industrial mobile robot, Proceedings of the 1997 IEEE International Conference on Control Applications Cat. No.97CH36055, 1997
 
(2446) Declercq M., Guyot A., Kanan R., Hochet B., A low-power high storage capacity structure for GaAs MESFET ROM, Proceedings. International Workshop on Memory Technology, Design and Testing Cat. No.97TB100159., 1997
 
(2447) Guillaume Ph., AMICAL extension for handling post synthesis analysis and energy estimation: averview of SYNRJ concepts, ISRN: TIMA-RR--97/05-1--FR, 1997
 
(2448) Villermaux J., Bernede P., Basrour S., Pons M., Mougin P., Daniau W., A microcatalytic support realised by LIGA technique: the devil's comb, Proceedings of International Solid State Sensors and Actuators Conference (Transducers '97)., 1997
 
(2449) Balme L., Jenni J.- F., Analyse des modes de défaillance et de leur criticité, Editions Weka, , 1997
 
(2450) Velazco R., Cheynet P., Muller J.D., Analysis and improvement of neural network robustness for on-board satellite image processing, Artificial-Neural-Networks-ICANN-'97.-, 1997
 
(2451) Abou-Samra S.-J., Guyot A., Analytical modelling of spurious transitions in adder circuits , 7th International Workshop Power and Timing Modeling Optimization and Simulation (PATMOS'97), Louvain-la-Neuve, Belgium, September 1997, 1997
 
(2452) Vestman F., Bouamama H., Borrione D., An approach to Verilog-VHDL interoperability for synchronous designs, Advances in Hardware Design and Verification. IFIP TC10 WG10.5 International Conference on Correct Hardware and Verification Methods, 1997
 
(2453) Bergher L., Lopez J., Liem Cl. B., Santana M., Gentit J.M, Cornero M., Figari X., Paulin P., Jerraya A. A., An embedded system case study: the firmware development environment for a multimedia audio processor, Proceedings of the 34th annual conference on Design automation, 1997
 
(2454) Wang J.C., Jerraya A. A., Strum M., Neto J.V.V., Teruya M.Y., A recursive high level synthesis system, ICVC '97. 5th International Conference on VLSI and CAD., 1997
 
(2455) Muller J.D., Velazco R., Buchner S., Cheynet P., Ecoffet R., Artificial neural network robustness for on-board satellite image processing : results of SEU simulations and ground tests, IEEE Nuclear and Space Radiation Effects Conference (NSREC'97), Snowmass (USA), 21-25 July 1997, 1997
 
(2456) Buchner S., Cheynet P., Velazco R., Muller J.D., Ecoffet R., Artificial neural network robustness for on-board satellite image processing: results of upset simulations and ground tests, IEEE Transactions on Nuclear Science, Dec. 1997; 44(6) pt. 1, page: 2337-44, 1997
 
(2457) Courtois B., Rencz M., Szekely V., A step forward in the transient thermal characterization of packages, Proceedings. 1997 International Symposium on Microelectronics SPIE vol.3235, 1997
 
(2458) Paret J.- M., A study and implementation of silicon microsystems design methodology and collective fabrication, These de Doctorat, 1997
 
(2459) Morawiec A., Mermet J., A survey of formal hardware verification tools developed , Asia-Pacific Conference on Hardware Description Languages (APCHDL'97), Hsin-Chu, Taiwan,18-20 August 1997, 1997
 
(2460) Renaudin M., Vivet P., Robin F., Asynchronisme et adéquation algorithme architecture, Traitement du Signal, , page: , 1997
 
(2461) Vivet P., Renaudin M., Robin F., Asynchronism in a joint algorithm-architecture perspective, Traitement du Signal, 14(6), page: 589-604, 1997
 
(2462) Renaudin M., Privat G., Robin F., Asynchronous relaxation of morphological operators: a joint algorithm-architecture perspective, International Journal of Pattern Recognition and Artificial Intelligence, 11(7): Nov., page: 1085-94, 1997
 
(2463) Calin T., Nicolaidis M., A theory of perturbation tolerant asynchronous FSMs and its application on the design of perturbation tolerant memories, European Test Workshop (ETW'97), Cagliari, Italy, 28-30 May 1997, 1997
 
(2464) Chauvet H., Leveugle R., Reveret L., Rochet R., Wending X., Automatic and optimized synthesis of dataparts with fault detection or tolerance capabilities, Proceedings. 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Cat. No.97TB100189., 1997
 
(2465) Paulin P., Nacabal F., Liabeuf C., Valderrama C., Jerraya A. A., Automatic generation of VHDL-C interfaces for distributed cosimulation, SASIMI Workshop, Osaka, Japan, 1-2 December 1997, 1997
 
(2466) Kission P., Jerraya A. A., Behavioral design allowing modularity and component reuse, Journal of Microelectronic System Integration, June 1997; 5(2), page: 67-83, 1997
 
(2467) Poppe A., Glesner M., Courtois B., Hofmann K., Drake P., Boutamine H., Rencz M., Szekely V., Karam J.M., CAD and foundries for microsystems, Annual ACM IEEE Design Automation Conference Proceedings of the 34th annual conference on Design automation, 1997
 
(2468) Courtois B., Lubaszewski M., Szekely V., Glesner M., Hofmann K., Rencz M., Karam J.M., CAD, test and manufacturing of microsystems, 1st Electronic Circuits and Systems Conference (ECS'97), Bratislava, Slovakia, 4-5 September 1997 , 1997
 
(2469) Courtois B., CAD tools and foundries to boost microsystems development, Conference on Low Dimensional Structures and Devices (LDSD'97), Lisbon, 19-21 May 1997, 1997
 
(2470) Courtois B., Karam J.M., Boutamine H., CAD tools for bridging microsystems and foundries, IEEE Design and Test of Computers, April-June 1997 (Vol. 14), page: 34-39, 1997
 
(2471) Rencz M., Courtois B., Szekely V., CAD tools for thermal testing of electronic systems, Advances in Electronic Packaging 1997. Proceedings of the Pacific Rim/ASME International Intersociety Electronic and Photonic Packaging Conference. INTERpack '97, 1997
 
(2472) Guillaume Ph., Jerraya A. A., Caractérisation de la consommation associée à la synthèse architecturale : une méthodologie, ISRN: TIMA-RR--97/01-1--FR, 1997
 
(2473) Gordon M.B., Muller J.D., El Chakik F., Velazco R., Perrenot F., Cheynet P., Cabestany J., Ecoffet R., Classical vs. neural approaches for on-board image satellite analysis, 2nd round table on Micro-Nano Tehnologies for Space, ESTEC, Noordwijk, The Netherlands, 15-17 October 1997, 1997
 
(2474) Sifflet S., Pressecq F., Karam J.M., Bianchi R.A., Courtois B., Vinci-Dos-Santos F., CMOS compatible temperature sensor using lateral bipolar transistor for very wide temperature range applications, 3rd International Workshop on Thermal Investigations of ICs and Microstructures, THERMINIC Workshop 97, Cannes, France, 21-23 September 1997, 1997
 
(2475) Jerraya A. A., Kission P., Jemai A., Combining architectural simulation and behavioral synthesis, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Oct. 1997; E80-A(10), page: 1756-66, 1997
 
(2476) Liem Cl. B., Paulin P., Jerraya A. A., Compilation Methods for the Address Calculation Units of Embedded Processor Systems, Design Automation for Embedded Systems, January 1997, Volume 2, Number 1, page: 71-77, 1997
 
(2477) Liem Cl. B., Paulin P., Compilation techniques and tools for embedded processor architectures, Hardware/Software Codesign : Principles and Practice, W. Wolf, J. Staunstrup, Kluwer Academic Publishers, , 1997
 
(2478) Wahba A., Borrione D., Connection error location and correction in combinational circuits, Proceedings. European Design and Test Conference. ED & TC 97 Cat. No.97TB100102, 1997
 
(2479) Török S., Szekely V., Rencz M., Courtois B., Cooling as a possible way to extend the usability of I/sub DDQ/ testing, Electronics Letters, 4 Dec. 1997; 33(25), page: 2117-2118, 1997
 
(2480) Jerraya A. A., Marchioro G.F., Changuel A., Valderrama C., Romdhani A., Daveau J.- M., COSMOS : a transformational co-design tools for multiprocessor architectures, Hardware/Software Co-Design: Principles and Practice, Kluwer Academic Publishers, chapitre 10, 1997
 
(2481) Wahba A., Design error diagnosis in digital circuits: the case of simple errors, These de Doctorat, 1997
 
(2482) Guyot A., Abou-Samra S.-J., Ayache F., Courtois B., Hoefflinger B., Dudek V., Designing with 3D SOI CMOS, Proceedings of the Eighth International Symposium on Silicon on Insulator Technology and Devices, 1997
 
(2483) Jerraya A. A., Kission P., Jemai A., Embedded architectural simulation within behavioral synthesis environment, Proceedings of the ASP-DAC '97, 1997
 
(2484) Goossens G., Lanneer D., Geurts W., Paulin P., Liem Cl. B., Kifli A., Van Praet J., Embedded software in real-time signal processing systems: design technologies, Proceedings of the IEEE , Vol. 85, page: , 1997
 
(2485) Drake P., Rencz M., Szekely V., Boutamine H., Karam J.M., Courtois B., Poppe A., Cao A., Oudinot J., El-Tahawi H., Engineering tool set for monolithic and hybrid microsystem design, Proceedings of the SPIE The International Society for Optical Engineering, 1997
 
(2486) Morawiec A., Mermet J., European formal verification tools for model correctness, Workshop on Libraries, Component Modelling, and Quality Assurance, 1997
 
(2487) Cheynet P., Rubio J.-C., Muller J.D., Velazco R., Evaluating neural network robustness with an architecture built around L-Neuro 2.3, 6th International Conference on Microelectronics for Neural Networks, Evolutionary & Fuzzy Systems, Dresden, Germany, 24-26 September 1997, 1997
 
(2488) Manich S., Nicolaidis M., Duarte R.O., Figueras J., Fault-secure parity prediction arithmetic operators, IEEE Design and Test of Computers, April-June ; 14(2), page: 60-71, 1997
 
(2489) Nicolaidis M., Zorian Y., Bederr H., Duarte R.O., Fault-secure shifter design: results and implementations, Proceedings. European Design and Test Conference. ED & TC 97 Cat. No.97TB100102, 1997
 
(2490) Borrione D., Dushina J., Formalisation and validation of the Std_Logic_1164 and Numeric_Std {VHDL} packages using the Nqthm theorem prover, 2nd Workshop on Libraries, Component Modeling and Quality Assurance, 1997
 
(2491) Privat G., Robin F., Renaudin M., Functionally asynchronous VLSI cellular array for morphological filtering of images, Traitement du Signal, 14(6), page: 655-64, 1997
 
(2492) Courtois B., Karam J.M., Bennouri N., Ribas R.P., GaAs MEMS design using 0.2 mu m HEMT MMIC technology, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997 Cat. No.97CH36098, 1997
 
(2493) Guyot A., Bernal A., Perez Ribas R., GaAs MESFET SRAM using a new high speed memory cell, 5th European Gallium Arsenide and related III-V compounds Applications Symposium (GAAS'97), Bologna, Italy, 3-5 September 1997, 1997
 
(2494) Karam J.M., Glesner M., Hofmann K., Courtois B., Generation of HDL-A code for nonlinear behavioral models, IEEE International Workshop on Behavioral Modeling and Simulations (BMAS'97), Washington DC, USA, 20-21 October 1997, 1997
 
(2495) Sebe N., Courtois B., Glesner M., Manolescu A., Karam J.M., Samitier J., Marco S., Hofmann K., Generation of the HDL-A-Model of a Micromembrane from Its Finite-Element-Description, 1997 European Design and Test Conference (ED&TC '97), 1997
 
(2496) Moussa I., Jerraya A. A., Kission P., Hardware reuse, 2nd Workshop on Libraries, Component Modeling & Quality Assurance, Toledo, Spain, April 1997, 1997
 
(2497) Vacher A., Hard-wired computation of a Fourier transform with a large number of samples, possibly multi-dimensional, These de Doctorat, 1997
 
(2498) Shishkov V., Vassileva T., Guyot A., Tchoumatchenko V., High performance adder's synthesis using efficient macro generator, ECCTD '97. Proceedings of the 1997 European Conference on Circuit Theory and Design., 1997
 
(2499) Rencz M., Szekely V., Courtois B., Integrating on-chip temperature sensors into DfT schemes and BIST architectures, Proceedings. 15th IEEE VLSI Test Symposium Cat. No.TB100125, 1997
 
(2500) Traore I., Romdhani A., Sahroui A.E.K., Jeffroy A., Jerraya A. A., Integration of partial specifications of avionics, Journal Européen des Systèmes Automatisés (RS-JESA) , Vol.31 N° 7/Novembre 1997, page: 1221-51, 1997
 
(2501) Rencz M., Szekely V., Courtois B., International Workshop on Thermal Investigations of ICs and Microstructures (THERMINIC 1996) September 25-27, 1996, Budapest, Hungary: Special Issue of Microelectronics Journal, Elsevier, Volume 28, Issue 3 , March, 205-365, 1997
 
(2502) Romdhani A., Le Marrec Ph., Hessel F., Marchioro G.F., Daveau J.- M., Jerraya A. A., Valderrama C., Languages for system level specification and design, Hardware/Software Co-Design: Principles and Practice, Kluwer Academic Publishers, CHAPITRE 7, 1997
 
(2503) Jerraya A. A., Ben Ismail T., Daveau J.- M., Marchioro G.F., Large protocol selection and interface generation for HW-SW codesign, IEEE Transactions on VLSI Systems, vol. 5, page: , 1997
 
(2504) Jenni J.- F., Balme L., Les plans d'expérience, Editions Weka, , 1997
 
(2505) Herve T., Simeu E., Linear and nonlinear modelling for fault detection and identification, Control of Industrial Systems. `Control for the Future of the Youth'. Proceedings volume form the IFAC Conference, 1997
 
(2506) Beleznay F., Courtois B., Napieralski A., Koval V., Szekely V., Rencz M., Main goals and obtained results of the THERMINIC Project, EUROTHERM'97, Nantes, 24-27 September 1997, 1997
 
(2507) Balme L., Jenni J.- F., Management de configuration, Editions Weka, , 1997
 
(2508) Ballandras S., Hauden D., Robert L., Basrour S., Mechanical characterization of microgrippers realized by LIGA technique, International Solid State Sensors and Actuators Conference (Transducers '97)., 1997
 
(2509) Bessot D., Velazco R., Memory cell insensitive to collisions of heavy ions, US5640341, 1997
 
(2510) Karam J.M., MEMS CAD and foundries: Where are we going?, Proceedings of the SPIE The International Society for Optical Engineering, 1997
 
(2511) Berrebi E., Methodology for the industrial application of architectural, These de Doctorat, 1997
 
(2512) Basrour S., Roulliay M., Bernede P., Daniau W., Blind P., Megtert S., Ballandras S., Microgrippers fabricated by the LIGA technique, Sensors and Actuators A : Physical, Vol.58, page: 265-272, 1997
 
(2513) Guyot A., Abou-Samra S.-J., Modeling power consumption in arithmetic operators, Microelectronic Engineering, Dec. ; 39(1-4), page: 245-53, 1997
 
(2514) Guyot A., Vaucher Ch., Abou-Samra S.-J., Houelle A., Aberbour M., Mehrez H., Modelling and synthesis of optimal adders under left-to-right input arrival, IFIP International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, France, December1997, 1997
 
(2515) Guyot A., Bernal A., Perez Ribas R., New high speed GaAs memory cell, 12th Conference on Design of Integrated Circuits and Systems (DCIS'97) , Sevilla, Spain, November 1997, 1997
 
(2516) Bernal A., Guyot A., New two single-port GaAs memory cell, ESSCIRC '97. Proceedings of the 23rd European Solid State Circuits Conference, 1997
 
(2517) Guyot A., Coissard V., OCAPI : A coprocessor for infinite precision arithmetic, International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN'97), Lyon, France, September 1997, 1997
 
(2518) Nicolaidis M., On-line testing for VLSI, Proceedings. International Test Conference 1997 IEEE Cat. No.97CH36126, 1997
 
(2519) Velazco R., Nicolaidis M., Vargas F., Terroso A.R., Performance improvement of fault-tolerant systems through chip-level current monitoring, 3rd IEEE International On-Line Testing Workshop , Aghia Pelaghia Headland, Crete, Greece, 7-9 July 1997, 1997
 
(2520) Mermet J., Nebel W., Proceedings of the NATO Advanced Sutdy Institute : Low Power Design in Deep Submicron Electronics, Il Ciocco, Italy, 20 - 30 Aug. 1996, Kluwer Academic Publishers, , 1997
 
(2521) Paschalis A., Nicolaidis M., Nikolos D., Proceedings on 3th IEEE International On-Line Testing Workshop (IOLT'97), July 7-9, 1997, Crete, Greece, IEEE Computer Society, 267 pages, 1997
 
(2522) Jerraya A. A., Ben Ismail T., Marchioro G.F., Daveau J.- M., Protocol selection and interface generation for HW-SW codesign, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 5, page: 136 - 144, 1997
 
(2523) Mcmorrow D., Buchner S., Muller J.D., Ecoffet R., Velazco R., Cheynet P., Mellinger J., Olmos S., Pulsed laser validation of recovery mechanisms of critical SEE's in an artificial neural network system, RADECS'97 (Radiation and their Effects on Devices and Systems), Cannes, France, 15-19 September 1997, 1997
 
(2524) Balme L., Jenni J.- F., Quality function deployment, Editions Weka, , 1997
 
(2525) Liem Cl. B., Jerraya A. A., Paulin P., ReCode: the design and re-design of the instruction codes for embedded instruction-set processors, 1997 European Design and Test Conference (ED&TC '97), 1997
 
(2526) Liem Cl. B., Retargetable compilers and tools for embedded processors in industrial applications, These de Doctorat, 1997
 
(2527) Liem Cl. B., Retargetable compilers for embedded core processors : methods and experiences in industrial applications, Kluwer Academic Publishers, , 1997
 
(2528) Rahmouni M., Scheduling and optimizations for high-level synthesis of control designs, These de Doctorat, 1997
 
(2529) Ziade H., Assoum A., Velazco R., Single event upsets simulations on neural networks, 2nd LAAS International Conference on Computer Simulation, Beyrouth (Liban), September 1997, 1997
 
(2530) Guyot A., Laurent B., Abou-Samra S.-J., Spurious transitions in adder circuits: analytical modelling and simulation, VLSI'97, Gramado, Brazil, 26-29 August 1997, 1997
 
(2531) Mir S., Rueda A., Peralias E., Huertas J.L., Olbrich T., SWITTEST: Automatic Switch-level Fault Simulation and Test Evaluation of Switched-Capacitor Systems, Design Automation Conference, 34th Conference on (DAC'97), 1997
 
(2532) Megtert S., Liu Z.W., Labeque A., Basrour S., Roulliay M., Kupka R., Casses V., Bernede P., Synchrotron radiation for microstructure fabrication, AIP-Conference-Proceedings.Application of Accelerators in Research and Industry. Fourteenth International Conference, 1997
 
(2533) Daveau J.- M., System level specification and communication synthesis for hardware/software co-design, These de Doctorat, 1997
 
(2534) Valderrama C., Jerraya A. A., Paulin P., Nacabal F., System-on-a-Chip Cosimulation and Compilation, IEEE Design and Test of Computers, April-June 1997 (Vol. 14), page: 16-25, 1997
 
(2535) Duarte R.O., Techniques & CAD tools for automatic generation of BIST & DFT for RAMs, These de Doctorat, 1997
 
(2536) Szekely V., Courtois B., Rencz M., Thermal testing methods to increase system reliability, Thirteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium Cat. No.97CH36031, 1997
 
(2537) Rencz M., Tarter T., Claasen A., Sabry N., Rubio A., Ortega A., Williams T., Courtois B., Thermal testing, why do we need it?, Proceedings of the IEEE VLSI Test Symposium 1997, Monterey, CA, USA, 27 April 1997 - 01 May 1997, 1997
 
(2538) Rencz M., Courtois B., Szekely V., Thermal transient testing, Microelectronics International, May 1997; (43), page: 8-10, 1997
 
(2539) Jerraya A. A., Abid M., Towards hardware-software co-design: a case study of robot arm controller, Journal of Microelectronic System Integration, Sept. 1997; 5(3), page: 167-82, 1997
 
(2540) Vinci-Dos-Santos F., Vinci-Dos-Santos F., Veychard D., Karam J.M., Courtois B., Boutamine H., Towards space microsystems : design and manufacturing methodologies for CMOS compatible MEMS, 2nd Round table on micro-nano technologies for space, ESTEC, Noordwijk, The Netherlands, 15-17 October 1997 , 1997
 
(2541) Marchioro G.F., Daveau J.- M., Jerraya A. A., Transformational partitioning for co-design of multiprocessor systems, IEEE/ACM International Conference on Computer Aided Design. Digest of Technical , 1997
 
(2542) Kission P., Guillaume Ph., Cesario W., Jerraya A. A., Unified evaluation model for interconnection schemes used in behavioral synthesis, IWLAS'97, Grenoble, France, December 1997, 1997
 
(2543) Jerraya A. A., Valderrama C., Le Marrec Ph., VCI : a VHDL-C interface generation tool for cosimulation, IEEE Second International High Level Design Validation and Test Workshop (HLDTV'97), Oakland, CA, USA, November 1997, 1997
 
(2544) Valderrama C., Daveau J.- M., Marchioro G.F., Jerraya A. A., VHDL generation from SDL specification, XIII IFIP Conference on CHDL, Toledo, Spain, 20-25 April 1997, 1997
 
(2545) Jerraya A. A., Valderrama C., Marchioro G.F., Daveau J.- M., VHDL generation from SDL specifications, Hardware Description Languages and their Applications. Specification, Modelling, Verification and Synthesis of Microelectronic Systems. IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications, 1997
 
(2546) Changuel A., Jerraya A. A., Valderrama C., Virtual prototyping for modular and flexible hardware-software systems, Design Automation for Embedded Systems, May 1997 ; Volume 2, Numbers 3-4, page: 267 - 282, 1997
 
(2547) Kodrnja M., Voltage controlled oscillator study for intermediate frequency oscillator noise analysis and simulation, These de Doctorat, 1997
 
(2548) Moussa I., Lassen P.S., A 2.5Gb/s ATM label translator implementation using high speed GaAs technology, ATM'96 Workshop, San Francisco, CA, USA, 25-27 August 1996, 1996
 
(2549) Moussa I., Torki K., Lassen P.S., A 2.5 Gb/s ATM label translator implemented by using GaAs technology, ESSCIRC-'96.-Proceedings-of-the-22nd-European-Solid-State-Circuits-Conference.Neuchatel, CH, 1996
 
(2550) Pulz L., Mir S., Lubaszewski M., ABILBO: Analog BuILt-in block observer, 1996 IEEE/ACM International Conference on Computer Aided Design. Digest of Technical Papers , 1996
 
(2551) Nicolaidis M., Manich S., Figueras J., Achieving fault secureness in parity prediction arithmetic operators: general conditions and implementations, Proceedings. European Design and Test Conference ED&TC 96 Cat. No.96TB100027, 1996
 
(2552) Jerraya A. A., Paulin P., Liem Cl. B., Address calculation for retargetable compilation and exploration of instruction-set architectures, Proceedings of the 33rd annual conference on Design automation, 1996
 
(2553) Changuel A., Jerraya A. A., Abid M., A hardware/software codesign case study: design of a robot arm controller, 1996 European Design and Test Conference (ED&TC '96), 1996
 
(2554) Guyot A., Ribas R.P., Bernal A., A low-power differential cross-coupled FET logic for GaAs asynchronous design, GAAS 96. European Gallium Arsenide and Related III V Compounds Applications Symposium and Associated CAD Workshop., 1996
 
(2555) Bernal A., Ribas R.P., Guyot A., A low-power enable/disable GaAs MESFET differential logic, 18th Annual GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. Technical Digest 1996 Cat. No.96CH35964, 1996
 
(2556) Borrione D., Wahba A., A method for automatic design error location and correction in combinational logic circuits, Journal of Electronic Testing: Theory and Applications, April ; 8(2), page: 113-27, 1996
 
(2557) Balme L., Vaucher Ch., Analog/digital testing of loaded boards without dedicated test points, Proceedings. International Test Conference 1996. Test and Design Validity IEEE Cat. No.96CH35976, 1996
 
(2558) Rahmouni M., Pedroza A., Kission P., Jerraya A. A., Pirmez L., Mesquita A., Analysis of different protocol description styles in VHDL for high-level synthesis, Proceedings EURO DAC '96. European Design Automation Conference with EURO VHDL '96 and Exhibition, 1996
 
(2559) Renaudin M., Robin F., Privat G., An asynchronous 16*16 pixel array-processor for morphological filtering of greyscale images, ESSCIRC '96. Proceedings of the 22nd European Solid State Circuits Conference, 1996
 
(2560) Guyot A., El-Hassan B., Renaudin M., A new asynchronous pipeline scheme: application to the design of a self-timed ring divider, IEEE Journal of Solid State Circuits, Volume 31, July, page: 1001 - 1013, 1996
 
(2561) Moussa I., Application of GaAs integrated circuits for high speed communication systems and high performance computing, These de Doctorat, 1996
 
(2562) Stefani R., Application of the ISO 9000 standard to service entreprises which are highly dependent on their information system, These de Doctorat, 1996
 
(2563) Rencz M., Szekely V., Karam J.M., Glesner M., Courtois B., Hofmann K., Poppe A., Applied design and analysis of microsystems, 1996 European Design and Test Conference (ED&TC '96), 1996
 
(2564) Rochet R., Leveugle R., Saucier G., ASYL-SdF: a synthesis tool for dependability in controllers, IEICE Transactions on Information and Systems, Oct. ; E79-D(10), page: 1382-8, 1996
 
(2565) Boutamine H., Renaudin M., El-Hassan B., Guyot A., Asynchronous SRT dividers: the real cost, Proceedings. European Design and Test Conference ED&TC 96 Cat. No.96TB100027, 1996
 
(2566) Bacivarov L., Balme L., Bazu M., A synergetic approach to reliability prediction, Joint International Conference on Probabilistic Safety Assessment and Management (PSAM III) and the European Safety and Reliability Conference (ESREL'96), Crete, Greece, 24-28 June 1996, Springer, London, 1996, 1996
 
(2567) Daveau J.- M., Jerraya A. A., O'Brien K., Ben Ismail T., A system-level communication synthesis approach for hardware/software systems, Microprocessors and Microsystems, Volume 20 1996, page: 149-157, 1996
 
(2568) Borrione D., Wahba A., Automatic diagnosis may replace simulation for correcting simple design errors, Proceedings EURO DAC '96. European Design Automation Conference with EURO VHDL '96 and Exhibition Cat. No.96CB36000, 1996
 
(2569) Valderrama C., Paulin P., Nacabal F., Jerraya A. A., Automatic generation of interfaces for distributed C-VHDL cosimulation of embedded systems: an industrial experience, Proceedings. Seventh IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototyping, 1996
 
(2570) Mir S., Courtois B., Lubaszewski M., Kolarik V., Automatic test generation for maximal diagnosis of linear analog circuits, Proceedings. European Design and Test Conference ED&TC 96, 1996
 
(2571) Vaucher Ch., Benali A., Balme L., Bare board test: From image processing to automatic test data generation, Proceedings of the Technical Conference IPC Printed Circuits EXPO '96, 1996
 
(2572) Ding Hong, Jerraya A. A., Kission P., Rahmouni M., Behavioral Synthesis and Component Reuse with VHDL, Kluwer Academic Publishers, , 1996
 
(2573) Courtois B., Mir S., Lubaszewski M., Built-in self-test approaches for analogue and mixed-signal integrated circuits, 38th Midwest Symposium on Circuits and Systems. Proceedings, 1996
 
(2574) Courtois B., Poppe A., Szekely V., Karam J.M., Hofmann K., Glesner M., Rencz M., CAD of MEMS: from the idea to the reality, MECHATRONICS'96, Besançon, France, 1-3 October 1996, 1996
 
(2575) Jenni J.- F., Balme L., Certification et Management de la qualité, Editions Weka, , 1996
 
(2576) Karam J.M., Bianchi R.A., Vinci-Dos-Santos F., Courtois B., CMOS compatible IR sensors array, Micromechanics Europe Conference (MME'96), Barcelona, Spain, 21-22 October 1996, 1996
 
(2577) Torki K., Paillotin J.-F., Delori H., Karam J.M., Courtois B., CMP services: basic principles and developments, 2nd International Conference on ASIC Proceedings IEEE Cat. No.96TH8140., 1996
 
(2578) Courtois B., Holjo M., Viktorovitch P., Karam J.M., Leclercq J.L., Collective fabrication of gallium-arsenide-based microsystems, Proceedings of SPIE - The International Society for Optical Engineering v 2879, 1996
 
(2579) Holjo M., Viktorovitch P., Leclercq J.L., Courtois B., Karam J.M., Collective fabrication of gallium-arsenide-based microsystems, Proceedings of the SPIE The International Society for Optical Engineering, 2879, page: 315-26, 1996
 
(2580) Herluison J.C., Jerraya A. A., Frehel J., Kission P., Vernalde S., De-Troch S., Berrebi E., Bolsens I., Combined control flow dominated and data flow dominated high-level synthesis, 33rd-Design-Automation-Conference.-Proceedings, 1996
 
(2581) Benali A., Contribution to quality assurance in bare printed wiring board testing: treatment of CAD information, using image processing techniques, for electrical test data generation, These de Doctorat, 1996
 
(2582) Dushina J., Borrione D., Jerraya A. A., Correct reuse of complex design units during high level synthesis: verification issues, 1st IEEE International High Level Design Validation and Test Workshop (HLDVT), Oakland, California, USA, 15-16 November 1996, 1996
 
(2583) Sahroui A.E.K., Jerraya A. A., Jeffroy A., Romdhani A., Co-specification for co-design in the development of avionics systems, Control Engineering Practice, Volume 4 1996, page: 871-876, 1996
 
(2584) Bianchi R.A., Vinci-Dos-Santos F., Courtois B., Karam J.M., Design and fabrication of an array of CMOS compatible IR sensors, THERMINIC Workshop, Budapest, Hungary, 25-27 September 1996, 1996
 
(2585) Szekely V., Rencz M., Benedek Zs., Courtois B., Design for thermal testability (DfTT) and a CMOS realization, Sensors and Actuators A : Physical, 15 July 1996; A55(1), page: 29-33, 1996
 
(2586) Rolland R., Jerraya A. A., Changuel A., Design of an adaptive motors controller based on fuzzy logic using behavioural synthesis, Proceedings EURO DAC '96. European Design Automation Conference with EURO VHDL '96 and Exhibition , 1996
 
(2587) Lubaszewski M., Liberali V., Mir S., Francesconi F., Design of high-performance band-pass sigma-delta modulator with concurrent error detection, Proceedings of the Third IEEE International Conference on Electronics, Circuits, and Systems. ICECS '96, 1996
 
(2588) Courtois B., Karam J.M., Developments at CMP service: from microelectronics to microsystems, Proceedings of the European Workshop Microelectronics Education, 1996
 
(2589) Nicolaidis M., Boudjit M., Parekhji R.-A., E-groups: a new technique for fast backward propagation in system-level test generation, Proceedings-of-the-Fifth-Asian-Test-Symposium-ATS-'96-Cat.-No.96TB100072. 1996:, 1996
 
(2590) Romdhani M., Embedded systems engineering using a hardware/software co-design methodology. Application on avionics, These de Doctorat, 1996
 
(2591) Nicolaidis M., Figueras J., Manich S., Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring, Proceedings. 14th IEEE VLSI Test Symposium Cat. No.96TB100043, 1996
 
(2592) Balme L., Bacivarov L., EPIQCS - An original european educational programme in quality, International Conference on Reliability of Semiconductor Devices ans Systems (RDCS'96), Kishinev, Moldova, 1996, 1996
 
(2593) Lister P., Hess K., Riesgo T., Peire J., Pype P., Krim N., Gore T., EUROMIC: EURopean OMI Centres, OMI Sixth Annual Conference on Embedded Systems (EMSYS'96), Berlin, Germany, 23-25 September 1996, 1996
 
(2594) Velazco R., Cheynet P., Bezerra F., Assoum A., Experiments on fault tolerance of artificial neural networks implemented by means of a transputer, Intelligent Systems and Soft Computing for Nuclear Science and Industry. Proceedings of the 2nd International FLINS Workshop., 1996
 
(2595) Changuel A., Jerraya A. A., Abid M., Exploration of hardware/software design space through a codesign of robot arm controller, EURO-DAC '96 European Design Automation Conference with EURO-VHDL '96, 1996
 
(2596) Vijayaraghavan V., Exploration of links between the High Level Synthesis (HLS) and the Register Transfer Level (RTL) synthesis, These de Doctorat, 1996
 
(2597) Lubaszewski M., Mir S., Courtois B., Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets, Journal of Electronic Testing: Theory and Applications, 9(1-2), page: 43-57, 1996
 
(2598) Mir S., Courtois B., Lubaszewski M., Kolarik V., Fault-based testing and diagnosis of balanced filters, Analog Integrated Circuits and Signal Processing, September, Volume 11, Number 1, page: 5-19, 1996
 
(2599) Ribas R.P., Guyot A., Vassileva T., Tchoumatchenko V., FPGA design migration: some remarks, Field Programmable Logic. Smart Applications, New Paradigms and Compilers. 6th International Workshop on Field Programmable Logic and Applications, FPL '96 Proceedings., 1996
 
(2600) Courtois B., Karam J.M., From the MEMS idea to the MEMS product: CAD and foundries, Wescon/96-Conference-Proceedings, 1996
 
(2601) Van-Den-Bossche N., Privat G., Renaudin M., Robin F., Functionally asynchronous array processor for morphological filtering of greyscale images, IEE-Proceedings-Computers-and-Digital-Techniques, 1996
 
(2602) Courtois B., Glesner M., Lambert J., Hofmann K., Karam J.M., Generation of a behavioural model of an acceleration sensor from its finite-element-description, MECHATRONICS'96, Besançon, France, 1-3 October 1996, 1996
 
(2603) Castro-Alves V., Ribeiro Antunes A., Marzouki M., Maroufi W., Global test scheduling and control in a HL-SFT environment, 1st IEEE International High Level Design Validation and Test Workshop (HLDVT), Oakland, California, USA, 15-16 November 1996, 1996
 
(2604) Kaminska B., Courtois B., Guest editorial, Journal of Electronic Testing (Historical Archives), August, Volume 9, Numbers 1-2, page: 7-8, 1996
 
(2605) Kaminska B., Courtois B., Guest Editors' Introduction: Mixed Analog and Digital Systems, IEEE Design and Test of Computers, Summer 1996 (Vol. 13), page: 8-9, 1996
 
(2606) Lefaou C., Bouamama H., Deharbe H., Borrione D., Wahba A., HDL-based integration of formal methods and CAD tools in the PREVAIL environment, Formal Methods in Computer Aided Design. First International Conference, FMCAD '96 Proceedings., 1996
 
(2607) Courtois B., Karam J.M., Bauge M., High level CAD melds microsystems with foundries, 1996 European Design and Test Conference (ED&TC '96), 1996
 
(2608) Kission P., High level synthesis involving hierarchy and the re-use of existing blocks, These de Doctorat, 1996
 
(2609) Marzouki M., Mesquita A., Ribeiro Antunes A., Castro-Alves V., Including testability in a high-level synthesis environment, 1st IEEE International High Level Design Validation and Test Workshop (HLDVT) , Oakland, California, USA, 15-16 November 1996, 1996
 
(2610) Szekely V., Rencz M., Courtois B., International Workshop on Thermal Investigations of ICs and Microstructures (THERMINIC 1995) September 25-26, 1995, Grenoble, France: Special Issue, Sensors and Actuators A: Physical, Elsevier, Issue 1 , 15 July, 1-70, 1996
 
(2611) Jerraya A. A., Aichouchi M., Kission P., Linking architectural synthesis with register transfer level design tools, Technique et Science Informatiques (TSI), 15(2), page: 179-199, 1996
 
(2612) Karam J.M., Methods and tools for the design and manufacturing of microsystems, These de Doctorat, 1996
 
(2613) Courtois B., Karam J.M., Paret J.- M., Microelectronics compatible manufacturing techniques of microsystems, MECHATRONICS'96, Besançon, France, 1-3 October 1996, 1996
 
(2614) Courtois B., Kamarinos G., Guillemot N., Microelectronics Education (1st European Workshop on Microelectronics Education, 1st EWME, Villards - de Lans, France, 5 and 6 Feb. 1996), Kluwer Academic Publishers, , 1996
 
(2615) Poppe A., Szekely V., Courtois B., Rencz M., Karam J.M., Microsystem design framework based on tool adaptations and library developments, Microlithography and Metrology in Micromachining II: Proceedings of SPIE - The International Society for Optical Engineering v 2880, 1996
 
(2616) Karam J.M., Szekely V., Poppe A., Rencz M., Courtois B., Microsystem design framework based on tool adaptations and library developments, Proceedings of the SPIE The International Society for Optical Engineering, 2880, page: 236-245, 1996
 
(2617) Courtois B., Karam J.M., Microsystem prototyping: from the idea to the foundry via a continuous design flow, EUROSENSORS X, Leuven, Belgium, 8-11 September 1996 , 1996
 
(2618) Georges D., Simeu E., Modeling and control of an eddy current brake, Control Engineering Practice, Jan. 1996; 4(1):, page: 19-26, 1996
 
(2619) Bacivarov L., Balme L., On reliability of surface mounted electronic assemblies, International Conference on Reliability of Semiconductor Devices and Systems (RDCS'96), Kishinev, Moldova, 1996, 1996
 
(2620) Marchioro G.F., Jerraya A. A., Ismail T.B, Partitioning of VLSI systems from a high-level specification, Technique et Science Informatiques (TSI), Vol.15/1996, page: 1131-65, 1996
 
(2621) Vijayaraghavan V., Pistorius R., Jerraya A. A., Kission P., Personalization of the architecture produced by High Level Synthesis for the RT Level, International Workshop on Logic and Architecture Synthesis (IWLAS '96), Grenoble, France, December 16-18, 1996, 1996
 
(2622) Pradhan D., Nicolaidis M., Proceedings on 2nd International On-Line Testing Workshop (IOLT'96), July 8-10, 1996, Biarritz - Saint-Jean-de-Luz, France, IEEE Computer Society, 265 pages, 1996
 
(2623) Kerckhoeve A., Clarençon D., Renaudin M., Gourmelon P., Catérini R., Boivin E., Ellis E., Hille B., Fatôme M., Real-time spike detection in EEG signals using the wavelet transform and a dedicated digital signal processor card, Journal of Neurosciences Methods, 70(1): Dec., page: 5-14, 1996
 
(2624) Borrione D., Research on VHDL in France, Italy and Switzerland, Spring VIUF Conference, 1996
 
(2625) Ecoffet R., Assoum A., Velazco R., Elie F., Radi M.E., Robustness against S.E.U. of an artificial neural network space application, RADECS-95, 1996
 
(2626) Wending X., Rochet R., Leveugle R., ROM-based synthesis of fault-tolerant controllers, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Cat. No.96TB100081, 1996
 
(2627) Courtois B., Second Therminic Workshop, IEEE Design and Test of Computers, Winter 1996 (Vol. 13), page: 5, 1996
 
(2628) El-Hassan B., Guyot A., Levering V., Renaudin M., Self timed division and square-root extraction, Proceedings. Ninth International Conference on VLSI Design Cat. No.96TB100010, 1996
 
(2629) Benezech D., Velazco R., Bezerra F., Assoum A., SEU and latch-up results on transputers, RADECS-95, 1996
 
(2630) Cheynet P., Ecoffet R., Olmos M., Assoum A., Velazco R., SEU experiments on an Artificial Neural Network implemented by means of digital processors, IEEE Transactions on Nuclear Science, Dec. 1996; 43(6) pt. 1, page: 2889-96, 1996
 
(2631) Velazco R., Koga R., Tran V.T., La Lumondiere S.D., Moss S., Nicolaidis M., Calin T., SEU-hardened storage cell validation using a pulsed laser, IEEE Transactions on Nuclear Science, Dec. 1996; 43(6) pt. 1, page: 2843-8, 1996
 
(2632) Courtois B., Some trends in CAD, test and fabrication of circuits and systems, Proceedings. Third International Conference on the Economics of Design, Test, and Manufacturing, 1996
 
(2633) Wending X., Leveugle R., Rochet R., Standard and ROM-based synthesis of FSMs with control flow checking capabilities, Proceedings. 14th IEEE VLSI Test Symposium Cat. No.96TB100043, 1996
 
(2634) Ding Hong, Synthèse architecturale interactive et flexible, These de Doctorat, 1996
 
(2635) Saucier G., Rochet R., Leveugle R., Synthesis for dependability of finite state machines, Technique et Science Informatiques (TSI), 15(4), page: 379-404, 1996
 
(2636) Ben Ismail T., System-level synthesis and hardware/software codesign, These de Doctorat, 1996
 
(2637) Deharbe D., Temporal logic model checking: study and application to VHDL, These de Doctorat, 1996
 
(2638) Touati M.-H., Test and diagnosis of partially boundary scan boards and MCMs, These de Doctorat, 1996
 
(2639) Kohari Z., Marta Cs., Courtois B., Szekely V., Rencz M., Test structure for thermal monitoring, ICMTS 1996. 1996 IEEE International Conference on Microelectronic Test Structures Proceedings, 1996
 
(2640) Nicolaidis M., Theory of transparent BIST for RAMs, IEEE Transactions on Computers, Oct. ; 45(10):, page: 1141-56, 1996
 
(2641) Courtois B., Szekely V., Thermal monitoring of memories, IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96), 1996
 
(2642) Karam J.M., Szekely V., Rencz M., Courtois B., Lubaszewski M., Thermal Monitoring Of Safety-Critical Integrated Systems, Fifth Asian Test Symposium (ATS'96), 1996
 
(2643) Szekely V., Courtois B., Rencz M., Thermal transient testing [IC packaging], 1996 International Symposium on Microelectronics SPIE Vol.2920., 1996
 
(2644) Courtois B., Rencz M., Szekely V., Thermal transient testing of the quality of encapsulation, MCM Test Workshop'96, Napa Valley, USA, 15-18 September 1996, 1996
 
(2645) Ziade H., Bezerra F., Velazco R., Hardy D., TILMICRO, a new SEU and latch-up tester for microprocessors: initial results on 32-bit floating point DSPs, RADECS-95, 1996
 
(2646) Cornero M., Nacabal F., Donawa C., Sutarwala S., May T., Valderrama C., Paulin P., Liem Cl. B., Trends in embedded systems technology: an industrial perspective, Hardware/Software Co-Design, Edited by M.G. Sami, G. De Micheli, Kluwer Academic Publishers, , 1996
 
(2647) Mir S., Courtois B., Lubaszewski M., Unified built-in self-test for fully differential analog circuits, Journal of Electronic Testing: Theory and Applications, 9(1-2), page: 135-51, 1996
 
(2648) Calin T., Velazco R., Nicolaidis M., Upset hardened memory design for submicron CMOS technology, IEEE Transactions on Nuclear Science, Dec. 1996; 43(6) pt. 1, page: 2874-8, 1996
 
(2649) Negoi A.C., Virtual device and its simulation processors, These de Doctorat, 1996
 
(2650) Renaudin M., Privat G., Robin F., El-Hassan B., A fine-grain asynchronous VLSI cellular array processor architecture, 1995 IEEE Symposium on Circuits and Systems Cat. No.95CH35771, 1995
 
(2651) Courtois B., Hofmann K., Poppe A., Glesner M., Szekely V., Rencz M., Karam J.M., A general CAD concept and design framework architecture for integrated microsystems, Simulation and Design of Microsystems and Microstructures, 1995
 
(2652) Boudjit M., Algorithmes de testabilité basés sur la description à deux-niveaux "Groupe-E-Concurrente" des fonctions logiques, These de Doctorat, 1995
 
(2653) Velazco R., Nicolaidis M., Calin T., Vargas F., A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results, IEEE Transactions on Nuclear Science, Dec. 1995; 42(6) pt. 1, page: 1592-8, 1995
 
(2654) Mir S., Kolarik V., Lubaszewski M., Courtois B., Analog checkers with absolute and relative tolerances, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 14, page: 607-612, 1995
 
(2655) Bederr H., Guyot A., Nicolaidis M., Analytic approach for error masking elimination in on-line multipliers, Proceedings of the 12th Symposium on Computer Arithmetic Cat. No.95CB35822, 1995
 
(2656) Zorian Y., Nicolaidis M., Vargas F., An approach for designing total-dose tolerant MCMs based on current monitoring, Proceedings. International Test Conference IEEE Cat. No.95CH35858, 1995
 
(2657) Montalvo L.-A., Guyot A., Mehrez H., Vaucher Ch., Houelle A., Application of fast layout synthesis environment to dividers evaluation, Proceedings of the 12th Symposium on Computer Arithmetic Cat. No.95CB35822., 1995
 
(2658) Simeu E., Application of NARMAX modelling to eddy current brake process, Proceedings of the 4th IEEE Conference on Control Applications Cat. No.95CH35764, 1995
 
(2659) Kebichi O., Zorian Y., Nicolaidis M., Area versus detection latency trade-offs in self-checking memory design, Proceedings. The European Design and Test Conference. ED&TC 1995 Cat. No.95TH8058, 1995
 
(2660) Jien-Chung Lo, Nicolaidis M., Daly J.-C., A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov. ; 14(11), page: 1402-7, 1995
 
(2661) Bayol C., A structural and behavioral modeling approach for the verification of VLSI components, These de Doctorat, 1995
 
(2662) Bederr H., Nicolaidis M., Hamdi B., A tool for automatic generation of self-checking data paths, Proceedings 13th IEEE VLSI Test Symposium Cat. No.95TH8068, 1995
 
(2663) Abid M., Ben Ismail T., Raghavan P.V., Valderrama C., Jerraya A. A., Changuel A., A unified model for co-simulation and co-synthesis of mixed hardware/software systems, Proceedings. The European Design and Test Conference. ED&TC , 1995
 
(2664) Lemery F., Behavioural modelling of analog and mixed circuits, These de Doctorat, 1995
 
(2665) Lubaszewski M., Mir S., Courtois B., Liberali V., Built-in self-test approaches for analogue and mixed-signal integrated circuits, 38th Midwest Symposium on Circuits and Systems. Proceedings , 1995
 
(2666) Venkataraman S., Courtois B., Hellebrand S., Rajski J., Tarnick S., Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers, IEEE Transactions on Computers, February 1995 Vol. 44, page: 223-233, 1995
 
(2667) Rencz M., Poppe A., Courtois B., Karam J.M., Szekely V., Glesner M., Hofmann K., CAD framework concept for the design of integrated microsystems, Proceedings of the SPIE The International Society for Optical Engineering, September 1995; 2642, page: 215-224, 1995
 
(2668) Karam J.M., Courtois B., Paret J.- M., Collective fabrication of microsystems compatible with CMOS through the CMP service, Materials Science and Engineering B-Solid State Materials For Advanced Technology , December 1995; Volume 35, page: 219-223, 1995
 
(2669) Houelle A., Guyot A., Mehrez H., Montalvo L.-A., Vaucher Ch., Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers, Proceedings-of-the-8th-International-Conference-on-VLSI-Design-Cat.-No.95TH802. 1995:, 1995
 
(2670) Jeffroy A., Chambert P., Romdhani A., Jerraya A. A., De-Chazelles P., Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionics, Proceedings-EURO-DAC-'95, 1995
 
(2671) Huertas J.L., Rueda A., Mir S., Lubaszewski M., Concurrent error detection in analog and mixed-signal integrated circuits, 38th Midwest Symposium on Circuits and Systems. Proceedings, 1995
 
(2672) Kaminska B., Courtois B., Conference Reports, IEEE Design and Test of Computers, Winter 1995 (Vol. 12), page: 95-97, 1995
 
(2673) Nicolaidis M., Correction d'erreurs dans une mémoire, FR2721135, 1995
 
(2674) Guyot A., Ribas R.P., DCFL- and DPTL-based approaches to self-timed GaAs circuits, ESSCIRC '95. Twenty First European Solid State Circuits Conference. Proceedings., 1995
 
(2675) Rousseau F., Launois H., Basrour S., Robert L., Roulliay M., Blind P., Bernede P., Robert D., Rocher S., Hauden D., Megtert S., Labeque A., Zewen L., Dexpert H., Comes R., Ravet M.F., Ballandras S., Daniau W., Deep etch X-ray lithography using silicon-gold masks fabricated by deep etch UV lithography and electroforming, Journal of Micromechanics and Microengineering, Vol.5, page: 203-8, 1995
 
(2676) Vassileva T., Guyot A., Tchoumatchenko V., Delay directed adder synthesis and optimization, ECCTD '95 Proceedings of the 12th European Conference on Circuit Theory and Design., 1995
 
(2677) Borrione D., Salem A., Denotational semantics of a synchronous VHDL subset, Formal Methods in System Design, Aug. ; 7(1-2), page: 53-71, 1995
 
(2678) Wahba A., Borrione D., Design error diagnosis in sequential circuits, Correct Hardware Design and Verification Methods. IFIP WG 10.5 Advanced Research Working Conference, CHARME '95. Proceedings., 1995
 
(2679) Jerraya A. A., Ismail T.B, Design models and steps for codesign, IEE Colloquium on 'Verification of Hardware Software Codesign' Digest, 1995
 
(2680) Brahic P., Leveugle R., Saucier G., Design of defect-tolerant scan chains for MCMs with an active substrate, Proceedings the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems 95TB100009, 1995
 
(2681) Skaf A., Design of redundant and on-line arithmetic processors: algorithms, architecture types and VLSI implementations, These de Doctorat, 1995
 
(2682) Nicolaidis M., Yarmolik V.-N., Memetov G.-R., Design of self-testing RAMs, Russian Microelectronics, May-June ; 24(3), page: 186-90, 1995
 
(2683) Nicolaidis M., Pham N., Digital TV: a perspective, IEE Colloquium on Developments in the Eutelsat System, 1995
 
(2684) Rochet R., Saucier G., Leveugle R., Efficiency comparison of signature monitoring schemes for FSMs, Proceedings of the ASP DAC'95/CHDL'95/VLSI'95. Asia and South Pacific Design Automation Conference. IFIP International Conference on Computer Hardware Description Languages and their Applications. IFIP Interntional Conference on Very Large Scale Integrati, 1995
 
(2685) Leveugle R., Rochet R., Saucier G., Efficient synthesis of fault-tolerant controllers, Proceedings. The European Design and Test Conference. ED&TC 1995 Cat. No.95TH8058, 1995
 
(2686) Nicolaidis M., Efficient UBIST implementation for microprocessor sequencing parts, Journal of Electronic Testing: Theory and Applications, June ; 6(3), page: 295-312, 1995
 
(2687) Jerraya A. A., De-Chazelles P., Jeffroy A., Romdhani A., Hautbois R.P., Evaluation and composition of specification languages, an industrial point of view, Proceedings of the ASP DAC'95/CHDL'95/VLSI'95. Asia and South Pacific Design Automation Conference. IFIP International Conference on Computer Hardware Description Languages and their Applications. IFIP Interntional Conference on Very Large Scale Integrati, 1995
 
(2688) Kebichi O., Nicolaidis M., Yarmolik V.-N., Exact aliasing computation for RAM BIST, IEEE International Test Conference (ITC'95), Washington, DC, USA, October 21-25, 1995
 
(2689) Nicolaidis M., Fail safe interface for appts control - has inputs for receiving two binary control signals and concurrent checker which provides error detection signal if error exists in input signals, WO9506908, 1995
 
(2690) Rahmouni M., Jerraya A. A., Formulation and evaluation of scheduling techniques for control flow graphs, Proceedings-EURO-DAC-'95, 1995
 
(2691) Courtois B., Lubaszewski M., Khaled S., Kaminska B., Frequency-based BIST for analog circuit testing, Proceedings-13th-IEEE-VLSI-Test-Symposium-, 1995
 
(2692) Jerraya A. A., Kission P., High level specification in electronic design, ISIE '95. Proceedings of the IEEE International Symposium on Industrial Electronics, 1995
 
(2693) Vargas F., Improving electronics reliability for space systems based on current monitoring, These de Doctorat, 1995
 
(2694) Liem Cl. B., Paulin P., Jerraya A. A., Cornero M., Industrial experience using rule-driven retargetable code generation for multimedia applications, Proceedings of the Eighth International Symposium on System Synthesis, 1995
 
(2695) Tchoumatchenko V., Guyot A., Vassileva T., Macromodelling of pass-transistor logic circuits, ECCTD '95 Proceedings of the 12th European Conference on Circuit Theory and Design., 1995
 
(2696) Mir S., Lubaszewski M., Courtois B., Kolarik V., Nielsen C., Mixed-signal circuits and boards for high safety applications, European Design and Test Conference (ED&TC '95), 1995
 
(2697) Sahroui A.E.K., Jeffroy A., Romdhani A., De-Chazelles P., Jerraya A. A., Modeling and rapid prototyping of avionics using STATEMATE, Proceedings. Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype, 1995
 
(2698) Renaudin M., El-Hassan B., Levering V., Guyot A., New self-timed rings and their application to division and square root extraction, ESSCIRC '95. Twenty First European Solid State Circuits Conference. Proceedings., 1995
 
(2699) Montalvo L.-A., Number systems for high performance divider, These de Doctorat, 1995
 
(2700) Courtois B., Lubaszewski M., On-line and off-line testing: from digital to analog, from circuits to boards, ESSCIRC '95. Twenty First European Solid State Circuits Conference. Proceedings, 1995
 
(2701) Ismail T.B, O'Brien K., Jerraya A. A., PARTIF: interactive system-level partitioning, VLSI Design, 3(3-4), page: 333-45, 1995
 
(2702) Jerraya A. A., Rahmouni M., PPS: a pipeline path-based scheduler, Proceedings. The European Design and Test Conference. ED&TC , 1995
 
(2703) Nicolaidis M., Pradhan D., Proceedings on 1st International On-Line Testing Workshop (IOLT'95), July 4-5, 1995, Nice, France, IEEE Computer Society, 252 pages, 1995
 
(2704) Guyot A., Vacher A., Radix-8 butterflies for folded FFT, Proceedings of the Twenty Seventh Southeastern Symposium on System Theory., 1995
 
(2705) Guyot A., Skaf A., SAGA: the first general-purpose on-line arithmetic co-processor, Proceedings of the 8th International Conference on VLSI Design Cat. No.95TH802., 1995
 
(2706) Borrione D., Deharbe H., Semantics of a verification-oriented subset of VHDL, Correct Hardware Design and Verification Methods. IFIP WG 10.5 Advanced Research Working Conference, CHARME '95. Proceedings, 1995
 
(2707) Radi M.E., Assoum A., Velazco R., Botey X., Ecoffet R., SEU fault tolerance in artificial neural networks, IEEE Transactions on Nuclear Science, Dec. 1995; 42(6) pt. 1, page: 1856-62, 1995
 
(2708) Vacher A., Guyot A., Spread and folded architectures for FFT, Proceedings of the Twenty Seventh Southeastern Symposium on System Theory., 1995
 
(2709) Armand M., Balme L., Silvy C., Supply component of the credit card type, U5449994, 1995
 
(2710) Guyot A., Montalvo L.-A., Svoboda-Tung division with no compensation, Proceedings of the 8th International Conference on VLSI Design Cat. No.95TH802., 1995
 
(2711) Ismail T.B, Daveau J.- M., Jerraya A. A., Synthesis of system-level communication by an allocation-based approach, Proceedings of the Eighth International Symposium on System Synthesis, 1995
 
(2712) Jerraya A. A., Ismail T.B, Synthesis steps and design models for codesign, Computer, Volume 28 (February 1995), page: 44-52, 1995
 
(2713) Nicolaidis M., Bederr H., Castro-Alves V., Testing complex couplings in multiport memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, March ; 3(1), page: 59-71, 1995
 
(2714) Nicolaidis M., Transparent testing of integrated circuits, US5469445, 1995
 
(2715) Calin T., Vargas F., Nicolaidis M., Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments, IEEE International Test Conference (ITC'95), Washington, DC, USA, October 21-25, 1995
 
(2716) Ding Hong, Jerraya A. A., Kission P., VHDL based design methodology for hierarchy and component re-use, Proceedings-EURO-DAC-'95, 1995
 
(2717) Jerraya A. A., Kission P., Ding Hong, Accelerating the design process by using architectural synthesis, Proceedings The Fifth International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype , 1994
 
(2718) Kolarik V., Advanced mehods for the test of analogue and mixed-signal circuits, These de Doctorat, 1994
 
(2719) Kebichi O., Nicolaidis M., Yarmolik V.-N., Aliasing-free signature analysis for RAM BIST, Proceedings. International Test Conference 1994 IEEE Cat. No.94CH3483 5., 1994
 
(2720) Jerraya A. A., Rahmouni M., O'Brien K., A loop-based scheduling algorithm for hardware description languages, Parallel Processing Letters, Volume 4(3), page: 351-364, 1994
 
(2721) Saucier G., Leveugle R., Rochet R., Alternative approaches to fault detection in FSMs, 1994 Proceedings. The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Cat. No.94TH78009, 1994
 
(2722) Ismail T.B, Jerraya A. A., O'Brien K., Abid M., An approach for hardware-software codesign, Proceedings The Fifth International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype, 1994
 
(2723) Soulas B., Bayol C., Corno F., Prinetto P., Borrione D., A process algebra interpretation of a verification oriented overlanguage of VHDL, Proceedings EURO DAC '94 with EURO VHDL '94 IEEE Cat. No.94CH35704., 1994
 
(2724) Nicolaidis M., Duarte R.O., A test methodology applied to cellular logic programmable gate arrays, Field Programmable Logic Architectures, Synthesis and Applications. 4th International Workshop on Field Programmable Logic and Applications, FPL '94. Proceedings., 1994
 
(2725) Muller J.-M., Guyot A., Bajard J.-C., Skaf A., A VLSI circuit for on-line polynomial computing: application to exponential, trigonometric and hyperbolic functions, IFIP Transactions A Computer Science and Technology, A-42, page: 93-100, 1994
 
(2726) Vacher A., Benkhebbab M., Skaf A., Rousseau T., Guyot A., A VLSI implementation of parallel fast Fourier transform, Proceedings. The European Design and Test Conference. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design Cat. No.94TH0634 6., 1994
 
(2727) Nielsen C., Kolarik V., Mir S., Lubaszewski M., Courtois B., Built-in self-test and fault diagnosis of fully differential analogue circuits, Proceedings of 1994 IEEE International Conference on Computer Aided Design (CAD-94). 6-10 Nov. 1994, 1994
 
(2728) Courtois B., CAD and testing of ICs and systems: where are we going?, Journal of Microelectronic System Integration, Sept. 1994; 2(3), page: 139-201, 1994
 
(2729) Hamdi B., CAD tools for automatic generation of self-checking data paths, These de Doctorat, 1994
 
(2730) Bessot D., Velazco R., Cellule mémoire insensible aux rayonnements, WO9422144, 1994
 
(2731) Vassileva T., Behnam B., Montalvo L.-A., Guyot A., CMOS implementation of a hybrid radix-4 divider, ESSCIRC '94. Twentieth European Solid State Circuits Conference. Proceedings., 1994
 
(2732) Guyot A., Montalvo L.-A., Combinational digit-set converters for hybrid radix-4 arithmetic, Proceedings IEEE International Conference on Computer Design: VLSI in Computers and Processors Cat. No.94CH35712., 1994
 
(2733) Bederr H., Contribution to the design for testability of iterative arithmetic and logic operators, These de Doctorat, 1994
 
(2734) Ismail T.B, Jerraya A. A., Abid M., COSMOS: a codesign approach for communicating systems, Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994
 
(2735) Bederr H., Guyot A., Nicolaidis M., Design for testability of on-line multipliers, Proceedings 12th IEEE VLSI Test Symposium Cat. No.94TH0645 2., 1994
 
(2736) Lubaszewski M., Kolarik V., Courtois B., Designing self-exercising analogue checkers, Proceedings-12th-IEEE-VLSI-Test-Symposium-, 1994
 
(2737) Guyot A., Moussa I., Skaf A., Design of a GaAs redundant divider, IFIP Transactions A Computer Science and Technology, A-42:, page: 63-72, 1994
 
(2738) Velazco R., Bessot D., Design of SEU-hardened CMOS memory cells: the HIT cell, RADECS-93, 1994
 
(2739) Bederr H., Nicolaidis M., Efficient implementations of self-checking multiply and divide arrays, Proceedings. The European Design and Test Conference. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design Cat. No.94TH0634 6., 1994
 
(2740) Nicolaidis M., Efficient UBIST for RAMs, Proceedings-12th-IEEE-VLSI-Test-Symposium-Cat.-No.94TH0645-2. 1994:, 1994
 
(2741) Guyot A., Vacher A., Error-speed compromise for FFT VLSI, Proceedings of the 26th Southeastern Symposium on System Theory Cat. No.94TH0599 1, 1994
 
(2742) Nicolaidis M., Fault secure property versus strongly code disjoint checkers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May ; 13(5), page: 651-8, 1994
 
(2743) Verguin P., Industrialization of a fault method on integrated circuits using liquid crystals, These de Doctorat, 1994
 
(2744) O'Brien K., Jerraya A. A., Ismail T.B, Interactive system-level partitioning with PARTIF, Proceedings. The European Design and Test Conference. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design , 1994
 
(2745) Aichouchi M., Linking architectural synthesis with register transfer level synthesis, These de Doctorat, 1994
 
(2746) Courtois B., MPC services available worldwide, APCCAS '94. 1994 IEEE Asia Pacific Conference on Circuits and Systems, 1994
 
(2747) Courtois B., Multi project chip service in France, Journal of the Institute of Electronics, Information and Communication Engineers, Jan. 1994; 77(1), page: 46-51, 1994
 
(2748) Vaucher Ch., Benali A., Balme L., Netlist automatic extractor: , Proceedings of the Third Asian Test Symposium Cat. No.94TH8016, 1994
 
(2749) Mullar J.-M., Guyot A., Skaf A., On-line hardware implementation for complex exponential and logarithm, ESSCIRC '94. Twentieth European Solid State Circuits Conference. Proceedings., 1994
 
(2750) Mir S., Filer N.-P., Re-engineering hardware specifications by exploiting design semantics, Proceedings of EURO-DAC European Design Automation Conference, 1994
 
(2751) Vargas F., Nicolaidis M., SEU-tolerant SRAM design based on current monitoring, Digest-of-Papers.-The-Twenty-Fourth-International-Symposium-on-Fault-Tolerant-Computing-Cat.-No.94CH3441-3. 1994:, 1994
 
(2752) Nicolaidis M., Strongly fail-safe interfaces based on concurrent check, Proceedings of IEEE 3rd Asian Test Symposium, 15-17 Nov. 1994, Nara, Japan, 1994
 
(2753) Jerraya A. A., Ming Hong, Kission P., Structured design methodology for high-level design, 31st-Design-Automation-Conference, 1994
 
(2754) Saucier G., Leveugle R., Doucet R., Chapier P., Michel T., Taking advantage of ASICs to improve dependability with very low overheads [PLC], Proceedings. The European Design and Test Conference. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design Cat. No.94TH0634 6, 1994
 
(2755) Safinia C., Leveugle R., Saucier G., Taking advantage of high level functional information to refine timing analysis and timing information, Proceedings. The European Design and Test Conference. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design Cat. No.94TH0634 6, 1994
 
(2756) Kebichi O., Techniques and CAD tools for automatic generation of BIST and DFT for RAMS , These de Doctorat, 1994
 
(2757) Leveugle R., Test of single fault tolerant controllers in VLSI circuits, IFIP Transactions A Computer Science and Technology, A-42, page: 123-32, 1994
 
(2758) Renaudin M., El-Hassan B., The design of fast asynchronous adder structures and their implementation using DCVS logic, 1994 IEEE International Symposium on Circuits and Systems Cat. No.94CH3435 5, 1994
 
(2759) Wehn N., Leveugle R., Koren Z., Koren I., Saucier G., The Hyeti defect tolerant microprocessor: a practical experiment and its cost-effectiveness analysis, IEEE Transactions on Computers, Dec. ; 43(12), page: 1398-406, 1994
 
(2760) Lubaszewski M., The unified board testing applied to the design of reliable systems, These de Doctorat, 1994
 
(2761) Voss M., Kapp K.H., Jerraya A. A., Ismail T.B, Towards a theory for hardware/software codesign, Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994
 
(2762) Castro-Alves V., Nicolaidis M., Kebichi O., Trade-offs in scan path and BIST implementations for RAMs, Journal of Electronic Testing: Theory and Applications, May-Aug. ; 5(2-3), page: 273-83, 1994
 
(2763) Kebichi O., Yarmolik V.-N., Nicolaidis M., Zero aliasing ROM BIST, Journal of Electronic Testing: Theory and Applications, Nov. ; 5(4), page: 377-88, 1994
 
(2764) Venier P., Renaudin M., Poize M., A general time domain approach for the design of perfect reconstruction modulated filter banks, ICASSP 93. 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing Cat. No.92CH3252 4, 1993
 
(2765) O'Brien K., Jerraya A. A., Park I., AMICAL: An interactive high level synthesis environment, The European Conference on Design Automation with the European Event in ASIC Design, 1993
 
(2766) O'Brien K., Park I., Jerraya A. A., AMICAL: architectural synthesis based on VHDL, IFIP Transactions A Computer Science and Technology, A-22, page: 219-34, 1993
 
(2767) Leveugle R., Saucier G., Rochet R., Analysis and comparison of fault tolerant FSM architecture based on SEC codes, Proceedings. The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Cat. No.93TH0571 0, 1993
 
(2768) Rezzouk A., Guerin R., Courtois B., Le-Roy A., A study of structural phase transitions by infrared spectroscopy of vibrational excitons: application to crystalline phenothiazine, Comptes Rendus de l'Academie des Sciences, Serie-II-Mecanique,-Physique,-Chimie-Sciences-de-la-Terre-et-de-l'Univers. 18 Feb. 1993; 316(4), page: 441-8, 1993
 
(2769) Planet P., Privat G., Renaudin M., Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms, : Proceedings.-International-Conference-on-Application-Specific-Array-Processors-Cat.-No.93TH0572-8, 1993
 
(2770) Pitot C., Saucier G., Martinez L., Rochet R., Leveugle R., A synthesis tool for fault-tolerant finite state machines, Digest of Papers FTCS 23 The Twenty Third International Symposium on Fault Tolerant Computing, 1993
 
(2771) Torki K., Nicolaidis M., Boudjit M., Automatic generation algorithms, experiments and comparisons of self-checking PLA schemes using parity codes, [1993]-Proceedings-The-European-Conference-on-Design-Automation-with-the-European-Event-in-ASIC-Design. Feb., 1993
 
(2772) Castro-Alves V., Lubaszewski M., Courtois B., Nicolaidis M., Checking signatures on boundary scan boards, Proceedings of ETC 93. Third European Test Conference Cat. No.93TH0494 5, 1993
 
(2773) Safinia C., Leveugle R., Clocking scheme selection for circuits made up of a controller and a datapath, IFIP Transactions A Computer Science and Technology, A-22, page: 293-308, 1993
 
(2774) Bouraoui R., Computation with large numbers and vlsi : application to PGCD, extended PGCD and Euclidean distance, These de Doctorat, 1993
 
(2775) Rost P., Guyot A., Moussa I., Design and comparison of GaAs and CMOS redundant divider, ESSCIRC 93. Nineteenth European Solid State Circuits Conference. Proceedings., 1993
 
(2776) Muller J.-M., Guyot A., Skaf A., Bajard J.-C., Design of a VLSI circuit for on-line evaluation of several elementary functions using their Taylor expansions, Proceedings.-International-Conference-on-Application-Specific-Array-Processors-Cat.-No.93TH0572-8. 1993:, 1993
 
(2777) Vargas F., Nicolaidis M., Courtois B., Design of built-in current sensors for concurrent checking in radiation environments, IEEE Transactions on Nuclear Science, Dec. ; 40(6) pt. 1, page: 1584-90, 1993
 
(2778) Rahmouni M., Jerraya A. A., O'Brien K., DLS: A scheduling algorithm for high-level synthesis in VH, [1993] Proceedings The European Conference on Design Automation with the European Event in ASIC Design, 1993
 
(2779) Nicolaidis M., Efficient implementations of self-checking adders and ALUs, Digest-of-Papers-FTCS-23-The-Twenty-Third-International-Symposium-on-Fault-Tolerant-Computing. Aug, 1993
 
(2780) Bayle P., Dana M., Courtois B., Electronic systems CAD, L'Onde Electrique, Nov.-Dec. 1993; 73(6), page: 25-31, 1993
 
(2781) Ben Othman M. T., Evaluation of a memory hierarchy for a symbolic machine, These de Doctorat, 1993
 
(2782) Yarmolik V.-N., Nicolaidis M., Exact aliasing computation and/or aliasing free design for RAM BIST, Records of the 1993 IEEE International Workshop on Memory Testing Cat. No.93TH0554 6, 1993
 
(2783) Nicolaidis M., Finitely self-checking circuits and their application on current sensors, Digest of Papers. Eleventh Annual 1993 IEEE VLSI Test Symposium Cat. No.93TH0537 1, 1993
 
(2784) Leveugle R., Safinia C., Generation of optimized datapaths: bit-slice versus standard cells, IFIP Transactions A Computer Science and Technology, A-22, page: 153-66, 1993
 
(2785) Nicolaidis M., Implementation techniques of self-checking arithmetic operators and data paths based on double-rail and parity codes, US5450340, 1993
 
(2786) Kission P., Jerraya A. A., Bergher L., Closse E., Industrial experimentation of high-level synthesis, Proceedings-EURO-DAC-'93, 1993
 
(2787) Saucier G., Delord X., Leveugle R., Influence of error correlations on the signature analysis aliasing, Proceedings 1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors Cat. No.93CH3335 7, 1993
 
(2788) Bayle P., Courtois B., Dana M., La CAO des systemes electroniques , Onde Electrique, vol. 73 n 6 Nov-Dec, page: 25-31, 1993
 
(2789) Jerraya A. A., Ismail T.B, O'Brien K., Linking system design tools and hardware design tools, IFIP Transactions A Computer Science and Technology, A-32, page: 345-355, 1993
 
(2790) Ben Ismail T., O'Brien K., Jerraya A. A., Linking system design tools and hardware design tools , Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL'93, Ottawa, Ontario, Canada, 26-28 April 1993 , 1993
 
(2791) Saucier G., Leveugle R., Abouzeid F., Logic synthesis for automatic layout, IFIP Transactions A Computer Science and Technology, A-22, page: 335-43, 1993
 
(2792) Kusumaputri-Hornik Y., On - line standard arithmetic operators for large precisions, These de Doctorat, 1993
 
(2793) Leveugle R., Optimized state assignment of single fault tolerant FSMs based on SEC codes, 30th Design Automation Conference. Proceedings 1993 IEEE Cat. No.93CH3262 3, 1993
 
(2794) Hamdi B., Vargas F., Nicolaidis M., Quiescent current estimation based on quality requirements, Digest of Papers. Eleventh Annual 1993 IEEE VLSI Test Symposium Cat. No.93TH0537 1, 1993
 
(2795) Courtois B., Nicolaidis M., Vargas F., Quiescent current monitoring to improve the reliability of electronic systems in space radiation environments, Proceedings 1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1993
 
(2796) Courtois B., Lubaszewski M., Reliable fail-safe systems, Proceedings-of-the-Second-Asian-Test-Symposium-, 1993
 
(2797) Benezech D., Rosier L.H., Velazco R., Estreme F., Chapuis T., Karoui S., Trigaux R., SEU and latch-up results for SPARC processors, Workshop-Record.-1993-IEEE-Radiation-Effects-Data-, 1993
 
(2798) O'Brien K., Silicon computation : from circuit to system, These de Doctorat, 1993
 
(2799) Betts A., Renaudin M., Sicard G., Bolsens I., Johnstone A., SMILE: a scalable microcontroller library element, Microprocessing and Microprogramming, 39(2-5): Dec., page: 259-62, 1993
 
(2800) Balme L., Vaucher Ch., Standard mirror boards (SMBs) concept , Proceedings of the 24th IEEE International Test Conference, Baltimore, MD, USA, 17-21 October 1993, 1993
 
(2801) Leveugle R., Saucier G., Gerbaux L., Synthesis of large controllers using ROM or PLA generators, IFIP Transactions A Computer Science and Technology, A-22, page: 47-59, 1993
 
(2802) Vaucher Ch., Test grid for tester of unpopulated printed circuits, US5450340, 1993
 
(2803) Balme L., Vaucher Ch., The standard mirror boards (SMBs) concept-An innovative improvement of traditional ATE for up to 10 mil bare board testing, Proceedings. International Test Conference 1993 Cat. No.93CH3356 3, 1993
 
(2804) Vaucher Ch., The test of high resolution bare printed circuit boards, These de Doctorat, 1993
 
(2805) Courtois B., Kolarik V., Lubaszewski M., Towards self-checking mixed-signal integrated circuits, ESSCIRC 93. Nineteenth European Solid State Circuits Conference, 1993
 
(2806) Kebichi O., Nicolaidis M., Castro-Alves V., Trade-offs in scan path and BIST implementations for RAMs, : Proceedings-of-ETC-93.-Third-European-Test-Conference-Cat.-No.93TH0494-5, 1993
 
(2807) Skaf A., Guyot A., VLSI design of on-line add/multiply algorithms, Proceedings 1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors Cat. No.93CH3335 7., 1993
 
(2808) Venier P., Renaudin M., Poize M., A fast algorithm for lapped nonorthogonal transform: application to the image Gabor transform, Proceedings of the SPIE The International Society for Optical Engineering., 1992
 
(2809) Park I., AMICAL: an assistant for the architectural synthesis and exploration of control circuits, These de Doctorat, 1992
 
(2810) Leveugle R., Roane R., Gaume F., Michel T., An application specific microprocessor with two-level built-in control flow checking capabilities, Proceedings.-Euro-ASIC-'92-Cat.-No.92TH0442-4., 1992
 
(2811) Jien-Chung Lo, Thanawastien S., Rao T.-R.-N., Nicolaidis M., An SFS Berger check prediction ALU and its application to self-checking processor designs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April ; 11(4), page: 525-40, 1992
 
(2812) Horeth S., Eveking H., Borrione D., Deharbe H., Application of a BDD-package to the verification of HDL descriptions, Correct Hardware Design Methodologies. Proceedings of the Advanced Research Workshop., 1992
 
(2813) Robach C., Aktouf C., Mazare G., Velazco R., A practical approach for the diagnosis of a MIMD network, Proceedings.-First-Asian-Test-Symposium-ATS-'92, 1992
 
(2814) Collette T., Architecture and VHDL behavioural validation of a parallel process ordedicated to computer vision, These de Doctorat, 1992
 
(2815) Nicolaidis M., Torki K., Fernandez J.-C., A self checking PLA automatic generator tool based on unordered codes encoding, EDAC, European Conference on Design Automation, Amsterdam, Netherlands, March 16, 1992, 1992
 
(2816) Jemai A., A study of a RISC processor for a parallel symbolic system, These de Doctorat, 1992
 
(2817) Kebichi O., Nicolaidis M., A tool for automatic generation of BISTed and transparent BISTed RAMs, IEEE 1992 International Conference on Computer Design: VLSI in Computers and Processors. ICCD '92 Cat. No.92CH3189 8, 1992
 
(2818) Boudjit M., Nicolaidis M., A tool for computing the output code spaces and verifying the self-checking properties in complex self-checking systems, IEICE Transactions on Information and Systems, Nov. ; E75-D(6), page: 824-34, 1992
 
(2819) Jerraya A. A., O'Brien K., Rahmouni M., A VHDL-based scheduling algorithm for control-flow dominated circuits, Sixth International Workshop on High Level Synthesis., 1992
 
(2820) Courtois B., Lestrat P., Castro-Alves V., Nicolaidis M., Built-in self-test for multi-port RAMs, 1991 IEEE International Conference on Computer-Aided Design - ICCAD-91, Santa Clara, CA, USA, November 11, 1991, 1992
 
(2821) Paillet J.-L., Milne G., Prinetto P., Eveking H., Borrione D., Claesen L., CHARME: towards formal design and verification for provably correct VLSI hardware, Correct Hardware Design Methodologies. Proceedings of the Advanced Research Workshop., 1992
 
(2822) Vaucher Ch., Circuit testing device for printed circuits - has different density test blocks linked to detachable modules arranged in lines or columns on test bed, FR9212549, 1992
 
(2823) Dassaud J.P., Guyot A., Spitz R., Copolymerization propene non-conjugated dienes: derivatization through hydroboration and epoxidation , Proceedings of the American Chemical Society Division of Polymeric Materials - Science and Engineering, Washington, DC, USA, 23-27 August 1992 , 1992
 
(2824) Sponga L., Magarshack P., Safinia C., Leveugle R., Datapath implementation: bit-slice structure versus standard cells, Proceedings.-Euro-ASIC-'92-Cat.-No.92TH0442-4., 1992
 
(2825) Martinez L., Leveugle R., Design methodology of FSMs with intrinsic fault tolerance and recovery capabilities, Proceedings.-Euro-ASIC-'92-Cat.-No.92TH0442-4., 1992
 
(2826) Daly J.-C., Nicolaidis M., Jien-Chung Lo, Design of static CMOS self-checking circuits using built-in current sensing, Digest of Papers. The 1992 IEEE Workshop on Fault Tolerant Parallel and Distributed Systems Cat. No.92TH0449 9, 1992
 
(2827) Vargas F., Russell J.D., Courtois B., E-beam testing using multiple adjacent image processing for prototype validation, Microelectronic Engineering, Volume 16 1992, page: 413-420, 1992
 
(2828) Castro-Alves V., Fault modelling and test algorithms for multi-port RAMs, These de Doctorat, 1992
 
(2829) Guyot A., Spitz R., Pasquet V., Dassaud J.P., Gomez C., General aspects of activation-deactivation processes with Ziegler-Natta olefin polymerization catalysts , Proceedings of the American Chemical Society Division of Polymeric Materials - Science and Engineering, Washington, DC, USA, 23-27 August 1992 , 1992
 
(2830) Hellebrand S., Courtois B., Rajski J., Tarnick S., Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers, Proceedings-International-Test-Conference-1992-, 1992
 
(2831) Velazco R., Karoui S., Chapuis T., Benedek Zs., Rosier L.H., Heavy ion test results for the 68020 microprocessor and the 68882 coprocesso, IEEE Transactions on Nuclear Science, June 1992, Volume: 39 , Part 1-2, page: 436-440, 1992
 
(2832) Nicolaidis M., Improving the theory of truth table verification of iterative logic arrays, Digest of Papers. 1992 IEEE VLSI Test Symposium. 10th Anniversary. Design, Test and Application: ASICs and Systems on a Chip Cat. No.92TH0437 4, 1992
 
(2833) Martinet B., Auvert G., Velazco R., Laser injection of spot defects on integrated circuits, Proceedings.-First-Asian-Test-Symposium-ATS-'92, 1992
 
(2834) Leveugle R., Abouzeid F., Saucier G., Jamier R., Logic synthesis for automatic layout, Proceedings.-Euro-ASIC-'92-Cat.-No.92TH0442-4., 1992
 
(2835) Paulin P., Jerraya A. A., Meta VHDL for higher level controller modeling and synthesis, IFIP Transactions A Computer Science and Technology, A-1, page: 215-24, 1992
 
(2836) Skaf A., Russell J.D., Conard D., Courtois B., Laurent J., Multiple adjacent image processing for automated failure location using electron beam testing, Reliability Engineering and Systems Safety, vol. 32 n 11 Nov, page: 1675-1620, 1992
 
(2837) D. Russell J., Courtois B., Skaf A., Conard D., Laurent J., Multiple adjacent image processing for automated failure location using electron beam testing [VLSI], Microelectronics and Reliability, Volume 32, Issue 11 , November 1992, page: 1615-1620, 1992
 
(2838) Kusumaputri-Hornik Y., Guyot A., OCAPI: A prototype for high precision arithmetic, IFIP Transactions A Computer Science and Technology, A-1, page: 11-18, 1992
 
(2839) Courtois B., Lubaszewski M., On the design of self-checking boundary scannable boards, Proceedings-International-Test-Conference-1992, 1992
 
(2840) Pierre L., Salem A., Borrione D., PREVAIL: a proof environment for VHDL descriptions, Correct Hardware Design Methodologies. Proceedings of the Advanced Research Workshop., 1992
 
(2841) Chapuis T., Karoui S., Velazco R., SEU testing of 32-bit microprocessors [for space application], Workshop-Record-1992-IEEE-Radiation-Effects-Data-, 1992
 
(2842) Nicolaidis M., Lubaszewski M., Castro-Alves V., Courtois B., Testing embedded single and multi-port RAMs using BIST and boundary scan, Proceedings. The European Conference on Design Automation, 1992
 
(2843) Lieberherr K.-J., Borrione D., Piloty R., Hill F., Moorby P., Three decades of HDLs. II. Conlan through Verilog, IEEE Design and Test of Computers, Sept. ; 9(3), page: 54-63, 1992
 
(2844) Nicolaidis M., Transparent BIST for RAMs, Proceedings-International-Test-Conference-1992-Cat.-No.92CH3191-4. 1992:, 1992
 
(2845) Boudjit M., Nicolaidis M., Verification of self-checking properties by means of output code space computation, Proceedings. The European Conference on Design Automation Cat. No.92TH0414 3, 1992
 
(2846) Mermet J., VHDL for Simulation, Synthesis and Formal Proofs of Hardware VHDL for Simulation, Kluwer Academic Publishers, , 1992
 
(2847) Velazco R., Caspi P., Piotrowski J., An a priori approach to the evaluation of signature analysis efficiency, IEEE Transactions on Computers, Sept. 1991; 40(9), page: 1068-71, 1991
 
(2848) Saucier G., Leveugle R., Michel T., A new approach to control flow checking without program modification, Digest of Papers. Fault Tolerant Computing: Twenty First International Symposium Cat. No.91CH2985 0., 1991
 
(2849) Marzouki M., Approches à base de connaissances pour le test des circuits VLSI : application à la validation de prototypes dans le cas d'un test sans contact, These de Doctorat, 1991
 
(2850) Fernandes A.-O., Nicolaidis M., Torki K., A self-checking PLA automatic generator tool based on unordered codes encoding, EDAC.-Proceedings-of-the-European-Conference-on-Design-Automation. 1991:, 1991
 
(2851) Boudjit M., Nicolaidis M., A tool for computation of output code spaces in complex self-checking systems, Proceedings. Pacific Rim International Symposium on Fault Tolerant Systems Cat. No.91TH0384 8, 1991
 
(2852) Lestrat P., Nicolaidis M., Courtois B., Castro-Alves V., Built-in self-test in multi-port RAMs, 1991 IEEE International Conference on Computer Aided Design. Digest of Technical Papers 91CH3026 2, 1991
 
(2853) Nicolaidis M., Castro-Alves V., Courtois B., Built-in self-test in multi-port RAMs, 1991 IEEE International Conference on Computer Aided Design. Digest of Technical, 1991
 
(2854) Magarshack P., Leveugle R., Lestrat P., Comprehensive CAD support for boundary scan implementation in ASICs, Euro-ASIC-'91-Cat.-No.91TH0367-3., 1991
 
(2855) Court T., Conception d'une famille de coprocesseurs parallèles intégrés pour le traitement d'images , These de Doctorat, 1991
 
(2856) Marzouki M., Courtois B., Laurent J., Coupling electron-beam probing with knowledge-based fault localization, Proceedings. International Test Conference 1991 IEEE, 1991
 
(2857) Leveugle R., Saucier G., Karam J.M., Hierarchical test generation based on delayed propagation, Proceedings. International Test Conference 1991 IEEE Cat. No.91CH3032 0, 1991
 
(2858) Boudjit M., Nicolaidis M., New implementations, tools, and experiments for decreasing self-checking PLAs area overhead, IEEE International Conference on Computer Design: VLSI in Computers and Processors Cat. No.91CH3040 3., 1991
 
(2859) Glesner M., Wehn N., O'Brien K., Goutis C., Catthoor F., Eijndhoven J., Philipson L., Olesen O., Courtois B., Pochmuller P., Madsen J., De Man H., Jess J., Novel ASIC architecture and synthesis methodologies for future multiplexed datapath designs, Proceedings of the 5th European Computer Conference on Advanced Computer Technology,Reliable Systems and Applications - CompEuro 91, Bologna, Italy, May 13, 1991 , 1991
 
(2860) Mark J.E., Guyot A., Espiard Ph., Revillon A., Nucleation of emulsion polymerization in the presence of small silica particles, Proceedings of the American Chemical Society, Spring Meeting, Atlanta, GA, USA, April 15, 1990, 1991
 
(2861) Guyot A., OCAPI: architecture of a VLSI coprocessor for the GCD and the extended GCD of large numbers, Proceedings. 10th IEEE Symposium on Computer Arithmetic Cat. No.91CH3015 5., 1991
 
(2862) Courtois B., Moine B., Pedrini C., Photoconductivity and fluorescence properties of divalent ytterbium ions in fluoride crystals, Journal of Luminescence, Volumes 48-49, Part 2 , January-February 1991, page: 501-504, 1991
 
(2863) Courtois B., Moine B., Pedrini C., Photoionization and luminescences in BaF/sub 2/:Eu/sup 2, Journal of Luminescence, Volume 50 -June 1991, page: 31-38, 1991
 
(2864) Martinet B., Velazco R., Physical fault injection: a suitable method for the evaluation of functional test efficiency, Proceedings. 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems, 1991
 
(2865) Jemai A., Berger Sabbatel G., Prolog on a RISC. Implementation and evaluation, Microelectronics Reliability, vol. 32 n 1-5 Aug, page: 497-504, 1991
 
(2866) Silvy C., Balme L., Rolland B., Poree E., Quality Assurance Manual for Microelectronics Industries specialized in Surface Mounted Technology : Reference Manual, , , 1991
 
(2867) Courtois B., Nicolaidis M., Self-Checking circuits: from theory to practice, Materials Science and Engineering B-Solid State Materials For Advanced Technology , , page: 83-88, 1991
 
(2868) Nicolaidis M., Shorts in self-checking circuits, Journal of Electronic Testing: Theory and Applications, Jan. ; 1(4), page: 257-73, 1991
 
(2869) Nicolaidis M., Shorts in self-checking circuits, , 1991
 
(2870) Jerraya A. A., Nicolaidis M., Torki K., Courtois B., Silicon compilation of hierarchical control sections with unified BIST testability, Microprocessors and Microsystems, June ; 15(5), page: 257-69, 1991
 
(2871) Leveugle R., Synthesis of controllers with concurrent checking: method and case studies, L'Onde Electrique, May-June ; 71(3), page: 69-75, 1991
 
(2872) Conard D., Traitement d'images en analyse de défaillances de circuits intégrés par faisceau d'électrons , These de Doctorat, 1991
 
(2873) Privat G., Renaudin M., VLSI architectural assessment of standard image coding systems, Annales des Telecommunications, 46(1-2), page: 121-41; Jan.-Feb., 1991
 
(2874) Savart D., Analyse de défaillances de circuits intégrés VLSI par testeur à faisceau d'électrons , These de Doctorat, 1990
 
(2875) Leveugle R., Saucier G., A synthesis method for concurrently checked controllers, 7th International Conference on Reliability and Maintainability. Proceedings, 1990
 
(2876) Pirson A., Conception et simulation d'architectures parallèles et distribuées pour le traitement d'images , These de Doctorat, 1990
 
(2877) Castro-Alves V., Trousson D., Guyot A., Gruere Y., Courtois B., Chaumontet G., Nicolaidis M., Description of a safe programming microprocessing unit for railway signalling, 7th International Conference on Reliability and Maintainability. Proceedings., 1990
 
(2878) Leveugle R., Saucier G., Michel T., Design of microprocessors with built-in on-line test, Digest of Papers. Fault Tolerant Computing: 20th International Symposium Cat. No.90CH2877 9., 1990
 
(2879) Nicolaidis M., Efficient UBIST implementation for microprocessor sequencing parts, Proceedings International Test Conference 1990 Cat. No.90CH2910 6., 1990
 
(2880) Chaumontet G., Etude de faisabilité d'un microcontrôleur de très haute sécurité , These de Doctorat, 1990
 
(2881) Torki K., Etude d'une stratégie d'autotest intégré pour le compilateur de silicium SYCO , These de Doctorat, 1990
 
(2882) Saucier G., Delord X., Leveugle R., Extended duplex fault tolerant system with integrated control flow checking, Defect and Fault Tolerance in VLSI Systems. Vol.2. Proceedings of the International Workshop, 1990
 
(2883) Savart D., Conard D., Courtois B., Collin J.P, Denis P., Failure analysis using E-beam, Microelectronic Engineering, Volume 12 1990, page: 305-324, 1990
 
(2884) Velazco R., Martinet B., Bellon C., Failure coverage of functional test methods: a comparative experimental evaluation, Proceedings-International-Test-Conference-1990, 1990
 
(2885) Courtois B., Pedrini C., Moine B., Fluorescence, photoconductivity and polarization properties of divalent rare earth ions in fluoride crystals, Journal of Luminescence, Volume 45 -February 1990, page: 248-250, 1990
 
(2886) Paillet J.-L., Prinetto P., Camurati P., Borrione D., Functional approaches applied to microprogrammed architectures, Interntional Journal of Computer Aided VLSI Design, 2(4), page: 339-58, 1990
 
(2887) Conard D., Courtois B., Laurent J., Marzouki M., High-level tools and methods for electron-beam debug and failure analysis of integrated circuits, Periodica Polytechnica, 34(4), page: 281-304, 1990
 
(2888) Nicolaidis M., Noraz S., High-security operation frequency-coding system, EP0385885, 1990
 
(2889) Saucier G., Delord X., Leveugle R., Improved duplex fault tolerant architecture based on integrated information compaction devices, 7th International Conference on Reliability and Maintainability. Proceedings, 1990
 
(2890) Jerraya A. A., Bonifas D., Courtois B., Bondono Ph., Hornik A., NAUTILE: a safe environment for silicon compilation, European Design Automation Conference Proceedings of the conference on European design automation, 1990
 
(2891) Leveugle R., Saucier G., Optimized synthesis of concurrently checked controllers, IEEE Transactions on Computers, April ; 39(4), page: 419-25, 1990
 
(2892) Leveugle R., Trilhe J., Reconfiguration in a microprocessor: practical results, Revue Technique Thomson CSF, Sept.; 22(3), page: 361-75, 1990
 
(2893) Courtois B., Darlay F., Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks, EDAC. Proceedings of the European Design Automation Conference., 1990
 
(2894) Velazco R., Guyot A., Ziade H., Conard D., Top down IC failure analysis using an E-beam system coupled to a functional teste, Microelectronic Engineering, May 1990; 12(1-4), page: 113-120, 1990
 
(2895) Saucier G., Leveugle R., Abouzeid F., A channelless layout for multilevel synthesis with compiled cells, Proceedings. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1989
 
(2896) Boland F., Courtois B., Melgara M., Whyte I., ADVICE project: final balance and future perspectives, ESPRIT '89. Proceedings of the 6th Annual ESPRIT Conference, 1989
 
(2897) Courtois B., Noraz S., Nicolaidis M., A generalized theory of fail-safe systems, FTCS-19-Digest of Papers. The Nineteenth Int. Symposium on Fault-Tolerant-Computing, 1989
 
(2898) Noraz S., Application des circuits intégrés autotestables à la sûreté de fonctionnement des systèmes , These de Doctorat, 1989
 
(2899) Jerraya A. A., Courtois B., Architecture experimentation with the behavioural silicon compiler SYCO, MELECON '89: Mediterranean Electrotechnical Conference Proceedings. Integrating Research, Industry and Education in Energy and Communication Engineering, 1989
 
(2900) Leveugle R., Saucier G., Poirot F., Sicard P., Duff C., Crastes-De-Paulet M., ASYL: a logic and architecture design automation system, Euro-ASIC-89, 1989
 
(2901) Saucier G., Delord X., Leveugle R., Built-in concurrent checking of ASICs, Euro-ASIC-89, 1989
 
(2902) Koga R., Velazco R., Provost-Grellier A., Chapuis T., Labrunee M., Falguere D., Comparison between Californian and cyclotron SEU tests, IEEE Transactions on Nuclear Science, Dec. 1989; 36(6) pt. 1, page: 2383-7, 1989
 
(2903) Provost-Grellier A., Velazco R., Comparisons of tests using heavy ions from californium and from cyclotron, Annales de Physique, Dec. 1989; 14colloq(2), page: 357-72, 1989
 
(2904) Leveugle R., Saucier G., Concurrent checking in dedicated controllers, Proceedings. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors , 1989
 
(2905) Jerraya A. A., Contribution à la compilation de silicium et au compilateur Syco , These de Doctorat, 1989
 
(2906) Bondono Ph., Contribution à NAUTILE: un environnement pour la compilation de silicium , These de Doctorat, 1989
 
(2907) Darlay F., Contribution au test des circuits intégrés CMOS : étude du test des pannes stuck-on et stuck-open , These de Doctorat, 1989
 
(2908) Hornik A., Contribution to definition and implementation of NAUTILE, These de Doctorat, 1989
 
(2909) Marzouki M., Courtois B., Debugging integrated circuits: AI can help, Proceedings of the 1st European Test Conference IEEE Cat. No.89CH2696 3, 1989
 
(2910) Leveugle R., Soueidan M., Design of an application specific microprocessor, Logic and Architecture Synthesis for Silicon Compilers. Proceedings of the Int. Workshop, 1989
 
(2911) Borrione D., Prinetto P., Paillet J.-L., Camurati P., Formal verification of microprogrammed architectures, CAD & CG '89 Beijing. Proceedings of International Conference on Computer Aided Design and Computer Graphics., 1989
 
(2912) Borrione D., Collavizza H., Pierre L., Paillet J.-L., Functional modelling and testing of digital circuits, Technique et Science Informatiques (TSI), 8(6), page: 523-44, 1989
 
(2913) Saucier G., Leveugle R., Highly wireable multilevel synthesis with compiled cells, Logic and Architecture Synthesis for Silicon Compilers. Proceedings of the International Workshop, 1989
 
(2914) Guyot A., Herreros Y., Muller J.-M., JANUS, an on-line multiplier/divider for manipulating large numbers, Proceedings of 9th Symposium on Computer Arithmetic, 1989
 
(2915) Pedrini C., Courtois B., Moine B., Luminescence and photoionization processes of Yb/sup 2+/ in CaF/sub 2/, SrF/sub 2/ and BaF/sub 2/, Journal de Physique, Aug. ; 50(15), page: 2105-19, 1989
 
(2916) Renaudin M., Privat G., Motion estimation VLSI architecture for image coding, Proceedings. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors Cat. No.89CH2794 6., 1989
 
(2917) Leveugle R., Saucier G., Optimized synthesis of dedicated controllers with concurrent checking capabilities, International Test Conference 1989. Proceedings. Meeting the Tests of Time , 1989
 
(2918) Balme L., Vaucher Ch., Printed circuit tester comprising stack of elastic sheets - has test point matrix card for each face of circuit sandwiched between compressed sheets conducting vertically, WO8900296, 1989
 
(2919) Courtois B., Random Pattern Testing Versus Deterministic Testing of RAMs, IEEE Transactions on Computers, May 1989 (Vol. 38), page: 637-650, 1989
 
(2920) Trilhe J., Soueidan M., Saucier G., Leveugle R., Glesner M., Wehn N., Reconfiguration in a microprocessor: practical results, ESPRIT '89. Proceedings of the 6th Annual ESPRIT Conference EUR 12512, 1989
 
(2921) Courtois B., Nicolaidis M., Self-checking logic arrays, Microprocessors and Microsystems, May; 13(4), page: 281-90, 1989
 
(2922) Nicolaidis M., Self-exercising checkers for unified built-in self-test (UBIST), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, March ; 8(3), page: 203-18, 1989
 
(2923) Nicolaidis M., Self-exercising checkers for unified built-in-test (UBIST), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, page: 203-18, 1989
 
(2924) Courtois B., Darlay F., Test and design for testability of reconvergent fan-out CMOS logic networks, International Test Conference 1989. Proceedings. Meeting the Tests of Time , 1989
 
(2925) Bekkara N., Geronimi J.P, Jamier R., Jerraya A. A., Courtois B., Mhaya N., The SYCO silicon compiler, Technique et Science Informatiques (TSI), 8(6), page: 489-507, 1989
 
(2926) Courtois B., Nicolaidis M., Noraz S., VLSI implementation for control of critical systems, Safety of Computer Control Systems 1989 SAFECOMP'89 Proceedings of the IFAC/IFIP Workshop., 1989
 
(2927) Courtois B., Nicolaidis M., Noraz S., VLSI implementation for control of critical systems, Safety of Computer Control Systems 1989 SAFECOMP'89 Proceedings of the IFAC/IFIP Workshop., 1989
 
(2928) Borrione D., Prinetto P., Zero-defect designs, why and how: formal verification vs. automated synthesis, Information Processing 89. Proceedings of the IFIP 11th World Computer Congress., 1989
 
(2929) Velazco R., Ziade H., Bellon C., Analysis of experimental results on functional testing and diagnosis of complex circuits, International Test Conference 1988 Proceedings New Frontiers in Testing Cat. No.88CH2610 4, 1988
 
(2930) Nicolaidis M., A unified built-in-test scheme: UBIST, Eighteenth International Symposium on Fault Tolerant Computing. Digest of Papers. FTCS 18 Cat. No.88CH2543 7, 1988
 
(2931) Zysman E., Control part design: application to FELIN arithmetic coprocessor, These de Doctorat, 1988
 
(2932) Privat G., Renaudin M., CORDIC-based digital signal processing hardware algorithms, Traitement du Signal, 5(6), page: 421-34, 1988
 
(2933) Jerraya A. A., Mhaya N., CPC: a control section synthesizer, Proceedings of the 8th International Custom Microelectronics Conference, 1988
 
(2934) Velasco-Medina J., Nicolaidis M., Current-based testing for analog and mixed-signal circuits, Proceedings International Conference on Computer Design VLSI in Computers and Processors, 5-7 Oct. 1998, Austin, TX, USA, 1988
 
(2935) Jansch I, Courtois B., Definition and design of strongly language disjoint checkers, IEEE Transactions on Computers, June; 37(6), page: 745-8, 1988
 
(2936) Leveugle R., Soueidan M., Design of a microprocessor with integrated on-line test for highly dependable systems, L'Onde Electrique, Nov.-Dec. ; 68(6), page: 59-66, 1988
 
(2937) Caisso J.-P., Courtois B., Fault simulation and test pattern generation at the multiple-valued switch level, International Test Conference 1988 Proceedings New Frontiers in Testing Cat. No.88CH2610 4, 1988
 
(2938) Duprat J., LAIOS : un réseau multiprocesseur orienté vers des applications d'intelligence artificielle , These de Doctorat, 1988
 
(2939) Berger Sabbatel G., Machines spécialisées et programmation en logique , These de Doctorat, 1988
 
(2940) Mhaya N.,