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70 résultats

   7 Revues internationales
  12 Conférences invitées
  35 Conférences internationales
   1 Chapitres de livre
   1 Revues nationales
   4 Autres communications
   3 Logiciels
   7 Thèses

7 Revues internationales

1 Deng E., Prenat G., Anghel L., Non-Volatile Magnetic Decider Based on Magnetic Tunnel Junctions, Electronics Letters, Ed. IEEE, Vol. , 2016
 
2 Pontié S., Maistri P., Leveugle R., Dummy operations in scalar multiplication over elliptic curves: a tradeoff between security and performance, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 23-36, DOI: 10.1016/j.micpro.2016.02.016, novembre 2016
 
3 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault models versus layout locality characteristics, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 64-73, DOI: 10.1016/j.micpro.2016.01.018, novembre 2016
 
4 Javaheri N., Morin-Allory K., Borrione D., Synthesis of Regular Expressions Revisited: from PSL SEREs to Hardware, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. to appear on paper, No. 99, pp. 1-14, DOI: 10.1109/TCAD.2016.2600241 , août 2016
 
5 Pierre L., Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements, Transactions on Design Automation of Electronic Systems (TODAES), Ed. ACM, NY, USA, Vol. 21, No. 2, pp. Article n°20, DOI: 10.1145/2811260, janvier 2016
 
6 Morin-Allory K., Javaheri N., Borrione D., Efficient and Correct by Construction Assertion-Based Synthesis, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 23, No. 12, pp. 2890-290, DOI: 10.1109/TVLSI.2014.2386212, décembre 2015
 
7 Ottavi M., Pontarelli S., Gizopoulos D., Bolchini C., Michael M.K., Anghel L., Tahoori M., Paschalis A., Reviriego P., Bringmann O., Izosimov V., Manhaeve H., Strydis C., Hamdioui S., Dependable Multicore Architectures at Nanoscale: The View From Europe , IEEE Design & Test, Ed. IEEE, Vol. 32, No. 2, pp. 17-28, DOI: 10.1109/MDAT.2014.2359572, avril 2015
 
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12 Conférences invitées

 1 Leveugle R., New approaches towards early dependability evaluation of digital integrated systems, Invited Tutorial, 11th IEEE International Design & Test Symposium (IDT'16), Hammamet, TUNISIA, 18 au 20 décembre 2016
 
 2 Maistri P., Hardware Design of Error Detection Schemes for Symmetric Ciphers, Séminaire invité, Séminaire sécurité des systèmes électroniques embarqués, Rennes, FRANCE, 2 décembre 2016
 
 3 Maistri P., Countermeasures against Implementation Attacks on Private- and Public-Key Cryptosystems, Keynote in the Opening Session, International Conference on Applications and Techniques in Information Security, Cairns, AUSTRALIA, 26 au 28 octobre 2016
 
 4 Anghel L., Portolan M., Managing Wear out and Variability Monitors: IEEE 1687 to the Rescue, Keynote talk, East West Design and test Symposium, Yerevan, ARMENIA, 13 au 16 octobre 2016
 
 5 Leveugle R., DFT vs. Security - Is it a Contradiction? How Can We Get the Best of Both Worlds?, Invited Talk, 1st IEEE International Verification and Security Workshop, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
 6 Pontié S., Prise en compte des fuites d’informations par canaux auxiliaires dans une implémentation ECC, Invited Talk, Séminaire sécurité des systèmes électroniques embarqués, Rennes, FRANCE, 27 juin 2016
 
 7 Anghel L., System Failure Prediction with On-Chip Monitors, Plenary talk, Colloque National 2016 de GDR SOC-SIP, Nantes, FRANCE, 7 au 8 mai 2016
 
 8 Portolan M., Standards: Can they co-exist for System Level Test?, Invited Talk, VLSI Test Symposium, Las Vegas, NE, UNITED STATES, 25 au 27 avril 2016
 
 9 Borrione D., Automatic Synthesis of Verification IP's from Assertions: Beyond Observers, 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16), Košice, SLOVENIA, 20 au 22 avril 2016
 
10 Anghel L., Moniteurs de fiabilité embarqués en technologie FDSOI: Implémentation et Applications, Invited Talk, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH'16), Vilard de Lans, FRANCE, 4 au 7 janvier 2016
 
11 Borrione D., Morin-Allory K., Liu M., Oddos Y., Morin-Allory K., Javaheri N., Verification and Synthesis of Digital Systems from Assertions, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'16), Villards de Lans, FRANCE, 1 janvier 2016
 
12 Anghel L., Reliability Measurements with In Situ Aging Monitors in FDSOI Technology, Invited talk (Elevator talk), International Test Conference (ITC'15), Anaheim, UNITED STATES, 6 au 8 octobre 2015
 
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35 Conférences internationales

 1 Mkhinini A., Maistri P., Leveugle R., Tourki R., Machhout M., A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption, 11th IEEE International Design & Test Symposium (IDT'16), pp. 131-136, Hammamet, TUNISIA, 18 au 20 décembre 2016
 
 2 Terras L., Teglia Y., Agoyan M., Leveugle R., Taking into account indirect jumps or calls in continuous Control-Flow Checking, 11th IEEE International Design & Test Symposium (IDT'16), pp. 125-130, Hammamet, TUNISIA, 18 au 20 décembre 2016
 
 3 Portolan M., Accessing 1687 systems using arbitrary protocols, International Test Conference (ITC'16), Fort Worth, UNITED STATES, DOI: 10.1109/TEST.2016.7805839, 15 au 17 novembre 2016
 
 4 Chabot M., Pierre L., Nabais-Moreno A., A Requirement Driven Testing Method for Multi-disciplinary System Design, ACM/IEEE International Conference on Model Driven Engineering Languages and Systems (MODELS'2016), Saint-Malo, FRANCE, 2 au 23 octobre 2016
 
 5 Plassan G., Peter H.J., Morin-Allory K., Rahim F., Sarwary S., Borrione D., Conclusively Verifying Clock-Domain Crossings in Very Large Hardware Designs, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16) , pp. 1-6, Tallinn, ESTONIA, 26 au 28 septembre 2016
 
 6 Chibani K., Portolan M., Leveugle R., Application-aware soft error sensitivity evaluation without fault injections - Application to Leon3, European Conference on Radiation and its Effects on Components and Systems (RADECS'16), Bremen, GERMANY, 19 au 23 septembre 2016
 
 7 Pontié S., Bourge A., Prost-Boucle A., Maistri P., Muller O., Leveugle R., Rousseau F., HLS-based methodology for fast iterative development applied to Elliptic Curve arithmetic, Euromicro/IEEE Conference on Digital System Design (DSD'16), pp. 511-518, Limassol, CYPRUS, DOI: 10.1109/DSD.2016.51, 31 août au 2 septembre 2016
 
 8 Alexandrescu D., Altun M., Anghel L., Bernasconi A., Ciriani V., Frontini L., Tahoori M., Synthesis and Performance Optimization of a Switching Nano-crossbar Computer, Euromicro Conference on Digital System Design (Euromicro DSD/SEAA'16), Limassol, CYPRUS, 31 août au 2 septembre 2016
 
 9 Deng E., Prenat G., Anghel L., Zhao W., Multi-context Non-volatile Content Addressable Memory Using Magnetic Tunnel Junctions, 12th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'16), Beijing, CHINA, 18 au 20 juillet 2016
 
10 Chibani K., Portolan M., Leveugle R., Evaluating Application-Aware Soft Error Effects in Digital Circuits Without Fault Injections or Probabilistic Computations, 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'16), pp. 54-59, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
11 Benhassain A., Mhira S., Cacho F., Huard V., Anghel L., In-Situ Slack Monitors : Taking up the Challenge of On-die Monitoring of Variability and Reliability, International Verification and Security Workshop, Sant Feliu de Guixols, SPAIN, 4 au 7 juillet 2016
 
12 Leveugle R., Chahed A., Maistri P., Papadimitriou A., Hély D., Beroulle V., Ammari A., On Fault Injections for Early Security Evaluation vs. Laser-based Attacks, 1st IEEE International Verification and Security Workshop, pp. 33-38, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
13 Backenstrass T., Blot M., Pontié S., Leveugle R., Protection of ECC Computations against Side-Channel Attacks for Lightweight Implementations, 1st IEEE International Verification and Security Workshop, pp. 2-7, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
14 Portolan M., Barragan M., Malloug H., Mir S., Interactive Mixed-Signal Testing Through 1687, First International Test Standards Application Workshop (TESTA'16), Amsterdam, NETHERLANDS, 26 au 27 mai 2016
 
15 Thole N., Anghel L., Fey G., A Hybrid Algorithm to Conservatively Check the Robustness of Circuits, IEEE European Test Symposium (ETS'16), Amsterdam, NETHERLANDS, 23 au 26 mai 2016
 
16 Portolan M., A Novel Test Generation and Application Flow for Functional Access to IEEE 1687 instruments, IEEE European Test Symposium (ETS'2016), Amsterdam, NETHERLANDS, DOI: 10.1109/ETS.2016.7519302, 23 au 27 mai 2016
 
17 Portolan M., Rolland R., Student-driven development of a digital tester, European Workshop on Microelectronics Education (EWME'16), pp. 1-3, Southampton, ENGLAND, DOI: 10.1109/EWME.2016.7496479, 11 mai 2016
 
18 Anghel L., Benhassain A., Sivadasan A., Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results, IEEE 34th VLSI Test Symposium (VTS'16), Las Vegas, NE, UNITED STATES, DOI: 10.1109/VTS.2016.7477316, 25 au 27 avril 2016
 
19 Benhassain A., Cacho F., Huard V., Mhira S., Anghel L., Parthasarathy C., Jain A., Sivadasan A., Robustness of Timing in-situ Monitors for AVS Management, IEEE International Reliability Physics Semiconductor (IRPS'16), Passadena, UNITED STATES, 17 au 21 avril 2017
 
20 Benhassain A., Cacho F., Huard V., Anghel L., Early failure prediction by using in-situ monitors: Implementation and application results, Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Dresden, GERMANY, 18 mars 2016
 
21 Sivadasan A., Cacho F., Benhassain A., Huard V., Anghel L., Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis, Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Dresden, GERMANY, 18 mars 2016
 
22 Ananiadis C., Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., On the development of a new countermeasure on a laser attack RTL fault model, Design, Automation and Test in Europe Conference (DATE'16), Dresden, GERMANY, 14 au 18 mars 2016
 
23 Sivadasan A., Cacho F., Benhassain A., Huard V., Anghel L., Study of workload impact on BTI HCI induced aging of digital circuits, Design Automation and Test in Europe (DATE'16), Dresden, GERMANY, 14 au 17 mars 2016
 
24 Jayet-Griffon C., Cornelie M.-A., Maistri P., Elbaz-Vincent P., Leveugle R., Polynomial multipliers for Fully Homomorphic Encryption on FPGA, International Conference on ReConFigurable Computing and FPGAs (ReConFig'15), Mayan Riviera, MEXICO, 7 au 9 décembre 2015
 
25 Benhassain A., Cacho F., Huard V., Saliva M., Anghel L., Parthasarathy C., Jain A., Giner F., Timing in-situ monitors: Implementation strategy and applications results, IEEE Custom Integrated Circuits Conference (ICICC'16), San Jose, CA, UNITED STATES, 28 au 30 septembre 2015
 
26 Chabot M., Mazet K., Pierre L., Automatic and Configurable Instrumentation of C Programs with Temporal Assertion Checkers, 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE’2015), Austin, Texas, UNITED STATES, 21 au 23 septembre 2015
 
27 Kebaili N., Morin-Allory K., Brignone J.C., Borrione D., Enabler-Based Synchronizer Model for Clock Domain Crossing static Verification, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
28 Javaheri N., Morin-Allory K., Borrione D., Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to Hardware, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
29 Pierre L., Towards a Toolchain for Assertion-Driven Test Sequence Generation, Forum on specification & Design Languages (FDL’2015), Barcelona, SPAIN, 14 au 16 septembre 2015
 
30 Papadimitriou A., Tampas M., Hély D., Beroulle V., Maistri P., Leveugle R., Validation of RTL laser fault injection model with respect to layout information, IEEE International Symposium on Hardware Oriented Security and Trust (HOST'15), pp. 78-81, McLean, VA, UNITED STATES, 5 au 7 mai 2015
 
31 Rehman Saif-Ur, Benabdenbi M., Anghel L., Application-independent testing of multilevel interconnect in mesh-based FPGAs, IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), pp. 1-6, Naples, ITALY, DOI: 10.1109/DTIS.2015.7127383, 21 au 23 avril 2015
 
32 Saliva M., Cacho F., Ndiaye C., Huard V., Angot D., Bravaix A. , Anghel L., Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology, IEEE International Reliability Physics Symposium (IRPS'15), pp. CA.4.1 - CA.4.6 , Monterrey, CA, UNITED STATES, DOI: 10.1109/IRPS.2015.7112782, 19 au 23 avril 2015
 
33 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault model versus layout locality characteristics, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
34 Pontié S., Maistri P., Leveugle R., Tuning of randomized windows against simple power analysis for scalar multiplication on elliptic curves, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
35 Saliva M., Cacho F., Huard V., Federspiel X., Angot D., Benhassain A., Bravaix A. , Anghel L., Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI, Design, Automation & Test in Europe Conference & Exhibition (DATE'15), pp. 441-446, Grenoble, FRANCE, 9 au 13 mars 2015
 
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1 Chapitres de livre

1 Beroulle V., Candelier P., De Castro S., Di Natale G., Dutertre J.M., Flottes M.-L., Hély D., Hubert G., Leveugle R., Lu F., Maistri P., Papadimitriou A., Rouzeyre B., Tavernier C., Vanhauwaert P., Laser-induced fault effects in security-dedicated circuits, VLSI-SoC: Internet of Things Foundations, L. Claesen, M.-T. Sanz-Pascual, R. Reis, A. Sarmiento-Reyes (Eds.) , Ed. Elsevier, pp. 220-240, Vol. 464, 2015
 
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1 Revues nationales

1 Fesquet L., Morin-Allory K., Robin R., Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes, J3eA – Journal sur l’enseignement des sciences et technologies de l’information et des systèmes, Ed. EDP Sciences, France, Vol. 14, No. 2009, pp. 9, DOI: 10.1051/j3ea/2015021 , août 2015
 
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4 Autres communications

1 Pierre L., Runtime Verification of Embedded Systems Requirements throughout the Design Flow, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'2015), Louvain-La-Neuve , BELGIUM, 2015
 
2 Pontié S., Attaque par analyse de la puissance consommée contre un crypto-processeur basé sur les courbes Jacobi quantiques, Journées Codage et Cryptographie 2015, Toulon, FRANCE, 2015
 
3 Bel Hadj Amor Z., Borrione D., Javaheri N., Morin-Allory K., Pierre L., Design Understanding - At What Abstraction Level is the Pain Most Intense?, Workshop on Design Automation for Understanding Hardware Designs (DUHDe Friday Workshop DATE 2015), Grenoble, FRANCE, 2015
 
4 Anghel L., Paradigm shift in the level of Quality and Reliability in semiconductors to a level smaller than 10ppb, Automotive Reliability and Test Workshop, Fort Worth, UNITED STATES, 2016
 
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3 Logiciels

1 Leveugle R., Chibani K., Portolan M., EARS (Evaluation Avancée de Robustesse de Systèmes intégrés / Early Analysis of Robustness for integrated Systems), Logiciel, 30 décembre 2016
 
2 Pierre L., Mazet K., Zian-Cherif A., OSIRIS version 1, Logiciel, 18 mars 2015
 
3 Ferro L., Pierre L., Chabot., Bel Hadj Amor Z., ISIS version 2.1.1, Logiciel, 1 mars 2015
 
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7 Thèses

1 Deng E., Design and development of low-power and reliable logic circuits based on spin-transfer torque magnetic tunnel junctions, These de Doctorat, 10 février 2017
 
2 Pontié S., Hardware security for cryptography based on elliptic curves, These de Doctorat, 21 novembre 2016
 
3 Chibani K., Robustness analysis of digital integrated systems, These de Doctorat, 10 novembre 2016
 
4 Rehman Saif-Ur, Development of test and diagnosis techniques for hierarchical mesh-based FPGAs, These de Doctorat, 6 novembre 2015
 
5 Gang Yi, Design of a Network on chip (NoC) that tolerates multiple static and dynamic faults, These de Doctorat, 5 novembre 2015
 
6 Saliva M., Dedicated circuits to aging mechanisms study in avanced CMOS technology nodes: Design and measurements, These de Doctorat, 2 octobre 2015
 
7 Javaheri N., Automatic synthesis of digital circuits from temporal specifications, These de Doctorat, 1 octobre 2015
 
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