AUGH: Autonomous and User Guided High-level synthesis


AUGH is a high-level synthesis tool designed for automatic generation of hardware accelerators for FPGA, under resource constraints. It generates a generic VHDL description from an input application written in C language.

It is free and open-source. License AGPLv3.
It is a command-line tool written for GNU/Linux systems.
It has embedded technology calibrations for Xilinx Virtex-5, Virtex-7 and Zynq.
It features highly experimental calibrations for Altera Arria V and Lattice iCE40 devices.

  • Automatic and very fast design space exploration
  • Handle strict resource constraints, given as raw number of FPGA primitives (LUTs, FFs, RAM blocks, DSP blocks…)
  • Handle a frequency constraint
  • Suited for users with low expertise in digital circuit design
  • Extensible with plugins (to declare additional FPGA technologies, boards, communication interfaces, special “black box” components, etc)

AUGH is under heavy developement.
Please be indulgent about missing features and potential bugs: we are working on them.
This project was initiated by Adrien Prost-Boucle, at the TIMA Laboratory, as works for his Ph.D.

Adrien Prost-Boucle, see this page
Olivier Muller (permanent), see this page
(in short: email is <firstname>.<lastname>


Clone the GIT repository from here: git://
and follow the instructions in the file README for compilation and installation.

For people who are not familiar with GIT repositories: you need the application git to be installed on your machine. There is an official package in every GNU/Linux distribution. Once git is installed, to get the AUGH source code, do as follows:

  1. Open a terminal
  2. Go in a directory where you want the AUGH source code to be downloaded
  3. Execute the command:

The entire AUGH source code should be present in a new directory named augh.
Follow instructions in the file README for compilation.


A tutorial application is shipped with the AUGH source code: the 2D IDCT.
Within the source tree, it is located at: tutorial/idct8x8
Follow instructions in the file README inside this directory.

More and much bigger applications will soon be provided.

Basic usage

Example of basic usage of AUGH as a command-line tool:

The first parameter -p xilinx makes AUGH load the plugin named “xilinx”. This plugin contains descriptions and calibrations for several Xilinx FPGA technologies, chips, and FPGA boards.

The second parameter -board xupv5 makes AUGH select the FPGA board named “xupv5” as synthesis target for the current application. AUGH will generate designs that correspond to the FPGA resources and that use the default board clock (100MHz) and reset button. The communication channels will be mapped, by default, on the UART port of the board.

The parameter -c makes AUGH stopafter VHDL generation. Otherwise, it would try to launch the default back-en logic synthesis, placement and routing tool suites.

The last parameter, app.c, is the cource file representing the application to synthesize on the specified target.


The user guide for AUGH is a PDF file (640kB). Last updated: March 4th, 2015.
To download it, use this link.

For help about AUGH command-line parameters, you can also launch augh –help.

AUGH also features an internal command interpreter. The user guide is very short about it. More detailed information about the available commands is in AUGH itself. To enter the command interpreter, launch augh -i. Then at the AUGH prompt, type help for a description of AUGH commands and sub- command interpreters. Please follow the above tutorial to better understand this.

Tips to write your own applications

AUGH handles a subset of ANSI C. Here are some of the limitations:

  • The top-level function must be of this form: void augh_main();
  • No arrays nor pointers in structures and unions.
  • No enumerated types.
  • No pointer arithmetic, no pointer variables.
  • Pointers can be used as function arguments but this is limited to passing address of variables, not arrays.
  • No floating-point.

Please refer to the user guide for more details.