M.Sc. in Electrical Engineering, 2018
Telecom Bretagne (IMT Atlantique)
After a one-year professional training contract at OVHcloud as last year of my M.Sc, my PhD subject was composed based on the team experience in the use of FPGAs to mitigate distributed denial-of-service (DDoS) attacks at the scale of OVHcloud’s 20Tbps network. While FPGAs provide both configurability and performance guarantees, their development flow relies on verbose and error-prone hardware descriptions with languages such as VHDL or Verilog. This flow hence struggles to provide the agility required to keep pace with attackers’ newest strategies. In order to increase both agility and confidence in the code base over iterations, my thesis researches consist in designing new paradigms for hardware description and development flow. My work is based on previous researches on Hardware Construction Languages such as Chisel –a library for describing hardware generators within Scala, an object-oriented and functional high-level language– which I leverage as the base infrastructure for introducing further abstractions and design paradigms.