The challenges that the micro/nanoelectronic system integration research is currently facing is a huge increase of the number of functions in a chip, be it processors, soft or hard IPs, interfaces with the physical world, … In this context, there are very important issues to be solved:
- what simulation strategies will allow functional validation and performance/power estimation for these new, large scale, heterogeneous systems?
- what architectural hardware support should be provided to users of these systems? Scalable but low power cache coherence, automated dynamic data placement, for large scale software support? Ad-hoc IPs for accelerating specific tasks, such as computer vision, data-analysis, artificial intelligence, and so on ? But also virtualization of the hardware resources, so that these features can be shared transparently and efficiently in actual computing environments.
- as the difficulties of HW/SW integration is unparalleled, can we provide synthesis and generation tools and methodologies to simplify and automate system integration?
To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
- Modeling and simulation of Hardware/Software Systems
- Future architectures for highly efficient general purpose computing, computer vision, data mining, IA, etc
- CAD for HW/SW systems : code generation, debug and synthesis
Visit our publications page for the recent and less recent conceptual advances that we have developed on these subjects.
Open source projects
Many of the topics we work on cannot be attacked theoretically, because of complexity and scalability issues, therefore we develop software and hardware (mainly simulation models as far as hardware is concern) to prove experimentally the interest of the approaches we define. Most if not all PhD thesis defended in the group produce practical results that we deliver as GPL’ed software (or with a license similar in spirit). Visit our repository page where the open software that we develop is available.
TIMA Lab is hosted by the Grenoble Institute of Technology, 46, avenue Félix Viallet, 38000 Grenoble, France.
The System Level Synthesis group is located Building T (two immediate turn right after the main entrance on Felix Viallet av.), 4th Floor, corridor on the left when leaving the elevator. Go straight to the closed doors, a white old school phone is there on your right, along with the list of people working here, so just pick you contact number and call.