System Level Synthesis (SLS)

Investigating Application-Specific, Multiprocessor System-on-Chips

SLS is part of the “Techniques de l’Informatique et de la Microélectronique pour l’Architecture des systèmes intégrés” (TIMA) CNRS research laboratory, located in Grenoble, France. SLS is currently led by Prof. Olivier Muller and gathers 6 permanent academic researchers.

The challenges that the micro/nanoelectronic system integration research is currently facing is a huge increase of the number of functions in a chip, be it processors, soft or hard IPs, interfaces with the physical world, etc. In this context, there are very important issues to be solved.

Microarchitecture des processeurs, RISC-V - Processor microarchitecture, RISC-V

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