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Invited Talk
Title: On Improving Real-Time Observability for In-System Post-Silicon Debug
Presenter: Nicola Nicolici (McMaster University, Canada)

Bio: Nicola Nicolici is an Associate Professor of Electrical and Computer Engineering at McMaster University. He received the Dipl. Ing. degree in Computer Engineering from the "Politehnica" University of Timisoara, Romania (1997) and a Ph.D. in Electronics and Computer Science from the University of Southampton, U.K. (2000). He is the recepient of the Best Student Paper Award at the IEEE International Test Conference (ITC) in 2000 and the Best Paper Award at the IEEE/ACM Design Automation and Test in Europe (DATE) in 2004.

Abstract: To identify design errors that escape pre-silicon verification, post-silicon debug is becoming an important step in the implementation flow of digital circuits. It is concerned with identifying design errors that escape to silicon. While commonly used in practice, it has received less research focus when compared to its complementary problem of manufacturing test, which is focused on screening for fabrication defects. We provide the background and summarize some recent research that addresses the emerging challenges


Invited Talk
Title: Calibration and Certification Instrumentation for Medical Equipment Reliability and Security
Presenter: Guillermo Avendaño ( Univ. of Valparaiso, Chile)

Bio:Guillermo Enrique Avendaño Cervantes, Chilean
Electronic Engineering University del Norte, specialization in Bioengineering, Nuclear Medicine, Cardiovascular Telemetry, respiratory function, spirometry, Extracorporeal circulation and cardioplegia
Diploma in psychophysiology.
MSc in Environmental Sciences
United Nations Technical Consultant
University professor in  6 Latin American universities
Technical Manager of 4 international companies like Siemens and General Electric
Author of 8 books, 3 book chapters and over 30 articles in various journals of specialty
Participant in 18 R&D projects and holder of  6 invention patents.

Abstract: The tutorial refers to the need for all equipment and facilities related to human health must be adequately verified in calibration and functionality, as any calibration error, indicating graphic display or measured performance parameters can become a source of serious problems for patients. Therefore there is a line of important work in Biomedical Engineering, dedicated to the creation of complementary technology to certify and eventually help calibrate Biomedical technology that has direct or indirect relationship with patients. The work shows the important iatrogenic effects and some of our developments in this kind of technology.



Keynote
Title: ICs and MEMS for energy management
Presenter: Bernard Courtois (CMP, France)

Bio: He received the Engineer degree in 1973, and next the « Docteur-Ingénieur » and « Docteur-ès-Sciences » degrees from the Institut National Polytechnique de Grenoble. He is currently the Director of CMP Service. He was also the founding Director of the Laboratory of Techniques of Informatics and Microelectronics for Computer Architecture (TIMA) where researches include CAD, architecture and testing of integrated circuits and systems. He has been general chair or program chair of many international conferences and workshops. He is Doctor Honoris Causa of the Technical University of Budapest.

Abstract: This keynote deals with how ICs and MEMS can address energy issues like the generation, the conversion, the use, the storage, of energy. Energy management is indeed a major issue for the world. Several domains are reviewed like equipment, buildings, lighting, transport, industry. Such a topic complements another important topic addressed usually for ICs and MEMS themselves, namely the design of low-power devices. A way for future ultra low power devices is also addressed. ICs and MEMS for energy management can be obtained from CMP that is briefly reviewed.

Embedded Tutorial
Title: Manufacturers to end-users tools for radiations induced reliability issues on electronic devices
Presenter: Frédéric Wrobel (IES, University of Montpellier, France)

Bio: Frederic Wrobel received his PhD in 2002 from the University of Montpellier 2 (France) in the field of nucleons induced nuclear reactions in SRAM memories. In 2008 he obtained his “Habilitation à Diriger des Recherches”. He is now associate professor at the University of Montpellier 2 where he is leader of the “Single Event Effects” themes. His current field of research is the development of soft error prediction tool and the study of natural radioactivity in devices. He is author and co-author of more than 70 works in journals and international conferences.

Abstract: Natural radiations induced failures in microelectronics has first been a real concern for space and avionic communities. Due to device integration this is now an issue for all commercial applications. The aim of this talk is to briefly present the natural radiative environment and its consequences on electronic devices. Then we will focus on soft errors induced at ground level. We will present the principles of simulation tools which are very useful to establish the transient current shapes and to evaluate the soft error rate. This kind of code can be validated thanks to accelerated tests under beam and/or accelerated test in natural environment (ie in altitude).


Invited Talk
Title: Design, Validation and Test of Robust Systems
Presenter: Subhasish Mitra (Stanford University, USA)

Bio: Subhasish Mitra is an Assistant Professor in the Department of Electrical Engineering and the Department of Computer Science of Stanford University where he leads the Stanford Robust Systems Group. His research interests include: 1. Robust system design; 2. VLSI design, CAD, validation and test; 3. Emerging nanotechnologies. Prior to joining Stanford, Prof. Mitra was a Principal Engineer at Intel Corporation. Prof. Mitra has invented design and test techniques that have seen wide-spread proliferation in the semiconductor industry. Several of his research results (some jointly with his students and collaborators) have been highlighted as "breakthroughs" by the MIT Technology Review, the Communications of the ACM and the Semiconductor Research Corporation. Prof. Mitra received numerous awards including the Presidential Early Career Award for Scientists and Engineers (the highest honor bestowed by the US government on early-career outstanding scientists and engineers), several Best Paper Awards including the IEEE Trans. CAD and IEEE/ACM Design Automation Conference, and the Intel Achievement Award, Intel’s highest corporate honor, “for the development and deployment of a breakthrough test compression technology.

Abstract: Robust system design ensures that future systems continue to meet user expectations despite rising levels of underlying disturbances. This talk discusses two essential aspects of robust system design: 1. Effective post-silicon validation, despite staggering complexity of future systems, using a new technique called Instruction Footprint Recording and Analysis (IFRA). 2. Cost-effective design of systems that overcome CMOS reliability challenges through built-in tolerance to errors in hardware during system operation. A combination of Built-In Soft Error Resilience (BISER) and circuit failure prediction, together with on-line self-test/diagnostics and software-orchestrated optimization across multiple abstraction layers, enable design of cost-effective resilient systems.

Invited Talk
Title: Variability-Aware Physical Design Techniques
Presenter: Gustavo Wilke and Ricardo Reis (UFRGS, Brazil)

Bio: Gustavo Wilke is a Postdoctoral researcher at UFRGS (Brazil). He received his Computer Engineering degree in 2005 at UFRGS and a Ph.D. in Microelectronics also from UFRGS in 2008. Gustavo worked as an Intern at Fujitsu Laboratories of America in Sunnyvale, CA for 6 months from 2004 to 2005 and for 1 year from 2006 to 2007. His research interests are automatic synthesis of high-performance clock distribution networks, CAD algorithms for physical design and reliable circuits.

Ricardo Reis received the Electrical Engineering from the Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978. In 1983, he received the Ph. D. degree from the Polytechnic Institute of Grenoble (INPG), France. He is presently Vice-President of IFIP (International Federation for Information Processing), Full Professor and the Head of the Microelectronics Graduate Program at UFRGS. His primary research interests include Physical Design Automation and Methodologies, CAD tools, Circuits Tolerant to Radiation, VLSI Design Methodologies and Microelectronics Education. He has published more than 250 hundred papers in journals and conferences proceedings (like IEEE Design & Test, ACM TODAES, IEEE JSSC, ISCAS, SBCCI, PATMOS, VLSI-SoC, DAC, DATE, ICCD, CICC, ASP-DAC, LATW). He is also author or co-author of several books. He got also some papers awards and he received an award as research of the year from the Fapergs (Science Foundation of Rio Grande do Sul), 2002. Silver Core award from IFIP. Ricardo Reis is research level 1A of the CNPq (Brazilian National Science Foundation) and head of several research projects supported by Government Agencies and Industry. Past head of the Graduate Program in Computer Science at UFRGS, where is a thesis advisor. He served as a General Chair or Program Chair of several conferences like the IFIP/IEEE VLSI-SoC, IEEE ISVLSI, IEEE LASCAS, Symposium on Integrated Circuits and Systems Design (SBCCI) and Congress of the Brazilian Microelectronics Society (SBMIcro). He is Past President of the Brazilian Computer Society and Past Vice-President of the Brazilian Microelectronics Society. He is VP of IEEE Circuits and Systems. Ricardo is member of the Editorial Board of IEEE Design&Test and chair of the Steering Committee of the IFIP/IEEE VLSI-SoC series of conferences. Ricardo Reis is a senior member of IEEE.

Abstract: Dealing with process and environmental variability became a great challenge for IC designers in the latest technology nodes. Digital circuits are designed in such a way that timing and power constraints are respected with minimum resource usage, to do that tight power and timing margins are desired. If process and environmental variability are not accounted during the design stage power and timing margins may not be sufficient to accommodate variability effect. To guaranteed robust operation physical design algorithms must account for the variability effect. This presentation gives an overview of the available technique for designing variation tolerant circuits. Techniques for robust clock distribution, routing and layout generation will be approached.


Embedded Tutorial
Title: Intelligent Ressources for Embedded Test and Control of AMS Systems
Presenter: Emmanuel Simeu (TIMA, France)

Bio: Emmanuel Simeu received the electrical engineer diploma in 1987 and Master and the Ph.D degree in Automatic Control and System Theory from the INPG (Institut National Polytechnique de Grenoble) in 1988 and 1992 respectively. From 1989 to 1992 he was researcher in CNET France Telecom research centre. He is currently associate professor in automatic control at Grenoble University and researcher in TIMA laboratory. He has been involved in nonlinear systems modelling and control. His current field of research includes heterogeneous system modelling, reliability of embedded systems systems, diagnosis and control of analogue/RF circuits.

Abstract: The conventional techniques of analogue and RF DUT test are essentially based on expensive functional test and pain to keep up with the vertiginous growth of the frequency of operation of the heterogeneous systems. This supported the emergence and the development of the alternative test approaches based on the estimation of analogue and Rf performances using low frequency measurements. We propose an approach of alternative test that use online identification of a behavioural model of the DUT. The parameters of the identified model are used as input of a regression equation to update the performances of the system in real-time. Trough analogue to digital converters (ADC), the test scheme can make use of any digital processors/memories available on the chip or package to implement the test of analogue and RF component.
The fact of being able to identify online a behavioural model and to extract the performances of the system in real time offers a feedback control possibility. The control of influential parameters such as voltage and current supply provides means to adjust the system performances according to the use demand. One challenging issue is to ensure minimal power consumption while guaranteeing a level of desired performances required by the operating condition of the system. We present a set of control loops resulting from the field of the automatic control which have been adapted in order to be used for a LNA performances control with minimal power consumption, in a space of performances which is defined by the network requirements.

Invited Talk
Title: Laser Testing for Single-Event Effects and Other Applications
Presenter: Vincent Pouget (IMS, France)

Bio: Vincent Pouget received his PhD in Applied Physics in 2000 from the University of Bordeaux, France. He’s currently a research scientist with the CNRS, the French National Center for Scientific Research, with the Nanoelectronics group at the IMS (Integration from Material to Systems) Laboratory, where he’s in charge of the ATLAS laser facility. He’s also the founder of the PULSCAN company. His main research interests include laser applications to the semiconductor industry and reliability issues in advanced technologies.

Abstract: Testing for single-event effects (SEE) aims to characterize the sensitivity of integrated circuits to perturbations induced by single particles interacting with the materials of the chip. This is a mandatory step in the system design or component qualification processes before including critical parts into systems that must guarantee high levels of reliability, safety or availability. The laser-based technique for SEE testing is a powerful in-lab approach for investigating particle induced effects at transistor, circuit, or system level, as well as for extracting useful sensitivity parameters for SEE rate prediction. This talk presents the current state-of-the-art of the laser-based technique for SEE testing. The principles of correlation between the effects of laser pulses and ionizing particles are briefly reviewed and several cases studies are presented to illustrate the current capabilities of the laser technique for SEE testing in recent technologies. Other applications of laser testing are also discussed, including fault injection for security evaluation.

Invited Talk
Title:Heterogeneous Integration: Beyond CMOS-Coping with Variability at the End of the CMOS Roadmap
Presenter: Sergio Bampi (UFRGS, Brazil)

Bio: Sergio Bampi  received the B.Sc in Electronics and  B.Sc. in Physics from the Federal Univ. of  Rio Grande do Sul (UFRGS, 1979), and the M.Sc. and Ph.D. degrees in electrical engineering from Stanford University in 1986.  He is now a professor at the Informatics Institute at UFRGS University and the Technical Director of the Microelectronics Center CEITEC at Porto Alegre, Brazil. Sergio Bampi is a Ph.D advisor and Project leader on the Microelectronics and Computer Science Programs, and his research interests are in the area of IC design and modeling, mixed signal and RF CMOS design, low power digital design, dedicated  complex architectures and ASICs for image and video processing. Sergio Bampi has co-authored more than 130 papers in these fields and in MOS devices, circuits, technology and CAD. Sergio Bampi was the President of the Research Funding agency FAPERGS in Brazil and Coordinator of the Graduate Program on Microelectronics at Federal University UFRGS.

Abstract: By 2020 it is very likely that nano-CMOS will reach the end of the scaling roadmap. Current 32nm CMOS production technology already is hampered by large variations in electrical parameters, with impacts on performance predictability, power consumption limitations and design closure for complex systems. Heterogeneous integration is the roadmap to lower cost and yet more advanced and innovative functionalities on silicon, with new and more manageable challenges. There will be no end nor a  definite demise of silicon technology at all. While there are uncertainties as to what will be the show-stoppers, there is a large number of transitional and compatible to CMOS technologies that will be more important than just 2-D scaling. This talk discusses variability among other limitations that bring the end of 2-D scaling and also proposes a likely scenario for hardware technology evolution and related challenges for integrating systems in the next 20 years. The scenario beyond the end of the roadmap is drawn, in which heterogeneous integration at the device level as well as at the system level will bring new frontiers to the ULSI era of tera-scale integration. Transitional technologies will co-exist and be built upon a basic CMOS-like technology platform.