| Research topics | Members
| Publications
| Former Researchers |
Former researchers
NB: All theses are available in pdf
format here
Researchers:
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Pr. Marc RENAUDIN |
Position: Professor at INPG (Institut National Polytechnique de Grenoble) |
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Marc
Renaudin received the Engineering and PhD degrees
in microelectronics and signal processing from the Institut
National Polytechnique de Grenoble, France,
respectively in 1987 and 1990. From 1990 till 1998, he served as an assistant
professor at Telecom Bretagne, France, a Graduate School of
Telecommunications Engineering where he was in charge of the Grenoble entity.
In 1995, he spent half a year as a visiting professor in Prof. A. Martin's
team at the Computer Science Department of the California Institute of
Technology, USA. In 1998, he joined INPG/ENSERG in Grenoble where he became a
Professor. He is currently heading the Concurrent Integrated Systems Group at
Tima Lab developing research on asynchronous system
design. He is lecturing on high performance computer architecture,
asynchronous VLSI design and hardware modelling and synthesis. He
led in collaboration with France Telecm R&D and
STMicroelectronics the Mica and Micabi projects on
the design of a CISC 8 bit asynchronous microprocessor integrated in a
contactless smart card IC using an on-chip antenna. He moreover managed the
ASPRO project, a standard-cell QDI 16-bit RISC asynchronous microprocessor.
He has numerous technical publications and has served as a reviewer for IEEE
JSSC, Trans. on VLSI, Trans. on Computers, Micro, ASYNC, ESSCIRC, VLSI. He also took part as member in the program committee
of ASYNC, ESSCIRC and DATE. His
current research interests include the design of secure chips, resistant
against timing, power and fault attacks (especially crypto processors and
coprocessors such as DES and AES). He is concurrently developing the TAST
tool suite, a CAD framework devoted to the specification, verification and
synthesis of asynchronous circuits. |
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Phone: |
E-mail: |
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Now CTO position, TIEMPO (Monbonnot,
France) |
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Dr. Alain GUYOT |
Position: Associate professor (Maître de conference)
at INPG-ENSIMAG |
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Alain Guyot
received his Master degree in Computer Science in 1971 and his Ph.D. in
Computer Science in 1975 from Grenoble University and Institut
National Polytechnique in Grenoble respectively. From 1989 to 1999 he
managed the VLSI
design group within TIMA
laboratory. For more information see: Personal home page |
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Retired
in 2005 |
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Graduated PhD's:
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Fady
ABOUZEID |
Status: Defense on November 2010 |
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PhD Title: Studies of subthreshold digital achitecture
and circuit in advanced CMOS technologies |
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Keywords:
Subthreshold, SRAM, Low power, Full custom |
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Advisors: Marc RENAUDIN, Gilles SICARD, Sylvain CLERC (STMicroelectronic) |
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Phone: |
E-mail: Hassan.Abbas@imag.fr |
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Now Ingineer position, STMicroelectronics
(Crolles, France) |
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Eslam YAHYA |
Status : Defense on December 2009 |
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PhD Title: Network on Chip Design Using
Asynchronous Logic |
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Keywords: Asynchronous Logic, Network on Chip,
NOC, Timing Analysis |
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Advisors: Marc Renaudin, Laurent Fesquet |
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Phone:
33 (0) 4-76-57-46-55 |
E-mail: Eslam.Yahya@imag.fr |
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Now Associate Professor (Cairo, Egypt) |
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Rodrigo POSSAMAI BASTOS |
Status: Defense on July 2010 (with UFRGS
university, Porto Alegre, Brazil) |
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PhD Title: Design
of Fault-Tolerant Asynchronous Circuits |
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Keywords:
Fault-Tolerant
Techniques; IC Design; Soft-Errors; SET; SEU; IC Design |
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Advisors: Ricardo REIS, Fernanda KASTENSMIDT, Marc
RENAUDIN, Gilles SICARD |
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Phone: |
E-mail: |
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Now post doc position, LIRMM Lab. (Montpellier,
France) |
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Khaled
ALSAYEG |
Status: Defense on September 2010 |
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PhD Title: Robust
clockless microcontrol |
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Keywords:
Low Power Finite State Machine, Asynchronous design |
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Advisors: Marc RENAUDIN, Gilles SICARD, Laurent FESQUET |
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Phone: |
E-mail: |
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Now ATER position, (Bordeaux, France) |
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Cedric KOCH-HOFFER |
Status: Defense on March 2009 |
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PhD Title: SystemC modelization, validation and synthesis of
asynchronous circuits |
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Keywords:
SystemC, modelization, validation, synthesis,
asynchronous circuits |
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Advisors: Marc RENAUDIN, Dominique BORIONNE (VDS group) |
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Phone: |
E-mail: |
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Now Ingineer position (Grenoble) |
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Livier
LIZARRAGA |
Status: Defense on November 2008 |
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PhD Title: Study and Development of a BIST Technique for CMOS
Imagers |
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Keywords:
CMOS Imagers; Photodiode; Test Metrics; Fault Modeling; BIST; |
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Advisors: Salvador MIR (RMS group), Gilles SICARD |
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Phone: |
E-mail: |
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Now Ingineer position (Grenoble, France) |
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Mr.
Saeed MIAN QAISAR |
Status:
Defense on May 2009 |
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PhD Title: Non-Uniform Signal Processing: Algorithms and Architectures |
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Keywords: Non-Uniform Sampling;
Asynchronous Architectures; Computational Complexity; Adaptive Rate Sampling;
Adaptive Rate Filtering; Signal to Noise Ratio; |
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Advisors: Laurent
FESQUET, Marc RENAUDIN |
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Phone:
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E-mail: |
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Now Ingineer position |
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David RIOS-ARAMBULA |
Status :
Defense on September 2008 |
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PhD Title: low power microprocessor system |
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Keywords:
low power, asynchronous, microprocessor, power estimation |
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Advisors: Marc RENAUDIN, Gilles SICARD |
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Now engineer position, Maya technologies,
(Grenoble, France) |
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Aurelien
BUHRIG |
Status :
Defense on April 2008 |
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PhD Title: Optimization
of the energy consumption in wireless sensor network nodes |
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Keywords:
energy optimization, asynchronous architectures, DVS, Scheduling |
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Advisors: Marc RENAUDIN, Laurent FESQUET |
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Now engineer position, TIEMPO (Grenoble, France) |
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Yannick
MONNET |
Status :
Defense on April 2007 |
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PhD Title: Study and modelling of secure circuits against non invasive fault
injection attacks |
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Keywords:
asynchronous circuits, circuit modeling, non invasive attack, fault injection |
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Advisors: Marc RENAUDIN, Regis LEVEUGLE (QLF group) |
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Now engineer position, TIEMPO (Grenoble, France) |
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Fraidy
BOUESSE |
Status :
Defense on December 2005 |
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PhD Title: Contribution
to secure design of integrated circuits: The asynchronous alternative |
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Keywords:
QDI Asynchronous Circuits, Hardware crypanalysis,
Side chanels attack, power analysis (SPA, DPA),
design methodology |
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Advisors: Marc RENAUDIN, Gilles SICARD |
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Now engineer position, TIEMPO (Grenoble, France) |
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Bertrand
FOLCO |
Status
: Defense on October 2007 |
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PhD Title: Contribution to Synthesis of Asynchronous Quasi
Delay Insensitive Circuits, Application to Secured Systems. |
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Keywords:
Asynchronous Circuits, QDI circuits, circuits synthesis, technology mapping,
cells library, hardware attacks, power consumption based attack, |
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Advisors: Marc RENAUDIN, Gilles SICARD |
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Now engineer position, TIEMPO (Grenoble, France) |
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Vivian BREGIER |
Status :
Defense on September 2007 |
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PhD Title: Automatic
synthesis of Asynchronous Proven Quasi Delay Insensitive Circuits |
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Keywords:
synthesis, logical optimization,
asynchronous, quasi delay insensitivity (QDI), modelization,
multi-valued decision diagram (MDD) |
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Advisor: Laurent FESQUET, Marc RENAUDIN |
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Now
engineer position, Atos Origin (Grenoble, France) |
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Estelle LABONNE |
Status :
Defense on July 2007 |
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PhD Title: Contribution To High
Dynamic Range CMOS Image Sensors Design |
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Keywords:
CMOS Imagers; High dynamic Range; Fixed Pattern Noise Calibration;
Logarithmic pixel; Adaptive Integration time; Light adaptive systems |
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Advisors: Gilles SICARD, Marc RENAUDIN |
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Now
Associate professor, Joseph Fourier University, IMEP-LAHC lab. |
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Fabien AESCHLIMANN |
Status :
Defense on February 2006 |
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PhD Title: Non
uniformly sampled signal processing : algorithm and
architecture |
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Keywords:
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Advisors: Marc Renaudin, Laurent Fesquet |
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Now
engineer position |
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Damien CAUCHETEUX |
Status :
Defense on December 2005 (with
CEA-LETI) |
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PhD Title: Architecture
study and design of mixed circuits using asynchronous logic: Application to
very low power consumption and contactless systems |
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Keywords:
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Advisors: Marc Renaudin |
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Now
engineer position |
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Joao Leonardo FRAGOSO |
Status :
Defense on November 2005 |
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PhD Title: Data
Paths Automatic Generation in QDI Asynchronous Logic |
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Keywords:
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Advisors: Marc Renaudin, Gilles Sicard |
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Post
doc with TIMA-CIS, now with CEITEC, Porto Allegre, Brasil |
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Jerome QUARTANA |
Status :
Defense on December 2004 (with
STMicroelectronics) |
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PhD Title: Design
of Asynchronous Network on Chip: application to GALS systems |
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Keywords:
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Advisors: Marc Renaudin, Laurent Fesquet |
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Now
Associate Professor with CMPG, Gardannes, France |
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Amine REZZAG |
Status :
Defense on December 2004 |
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PhD Title: Logical
synthesis of micropipeline asynchronous circuits |
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Keywords:
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Advisors: Marc Renaudin, Laurent Fesquet |
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Kamel
SLIMANI |
Status :
Defense on December 2004 |
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PhD Title: Low
power asynchronous microprocessors |
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Keywords:
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Advisors: Marc Renaudin, Gilles Sicard |
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Now
with Texas Instrument, Sophia Antipolis, France |
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Antoine SIRIANNI |
Status :
Defense on June 2004 |
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PhD Title: Mod
elisation, simulation and v erification
of asynchronous circuits in SystemC v2.0.1 standard |
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Keywords:
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Advisors: Marc Renaudin, Laurent Fesquet |
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Dhanistha
PANYASAK |
Status :
Defense on June 2004 (with
STMicroelectronics) |
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PhD Title: Electromagnetic
Emission Reduction In Integrated Circuits: The Asynchronous Alternative |
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Keywords:
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Advisors: Marc Renaudin, Gilles Sicard |
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NXP,
Crolles, France, now with EMMicroelectronic,
Marin, Switzerland |
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Emmanuel ALLIER |
Status :
Defense on November 2003 |
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PhD Title: Asynchronous
Analog to Digital Interface: a New Class of Converters Based on Time
Quantization |
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Keywords:
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Advisors: Marc Renaudin, Gilles Sicard |
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Ingineer
position, STMicroelectronics,Grenoble,France |
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Anh
Vu DINH DUC. |
Status :
Defense on March 2003 |
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PhD Title: Automatic
synthesis of QDI asynchronous circuits |
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Keywords:
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Advisors: Marc Renaudin, Laurent Fesquet |
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Now
with ITIP University, HoChiMinh Ville, Vietnam |
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Jean-Baptiste
RIGAUD |
Status :
Defense on December 2002 |
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PhD Title: Libraries
specification for the synthesis of asynchronous circuits |
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Keywords:
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Advisors: Marc Renaudin, Gilles Sicard |
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Now
Associate Professor with CMPG, Gardannes, France |
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Bruno GALILEE |
Status :
Defense on October 2002 (with France
Telecom R&D) |
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PhD Title: Algorithm-architecture
study for multimedia handset: image segmentation thanks to an asynchronous
processors array |
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Keywords:
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Advisors: Marc Renaudin,
Pierre-Yves Coulon |
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Now
with STMicroelectronics, Grenoble, France |
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Sebastien
ROUX |
Status :
Defense on January 2002 (with France
Telecom R&D) |
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PhD Title: Algorithm
and architecture for embedded multimedia system |
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Keywords:
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Advisors: Alain Guyot |
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Now
with France Telecom R&D, Grenoble, France |
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Pascal VIVET |
Status :
Defense on June 2001 (with France
Telecom R&D) |
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PhD Title: A
quasi-delay insensitive integrated circuit design methodology
: application to the study and design of a 16-bit asynchronous RISC
microprocessor |
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Keywords:
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Advisors: Marc Renaudin |
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STMicroelectronics
– Grenoble, now with CEA-LETI, Grenoble, France |
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