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8th Latin American Test
Workshop (LATW 2007), Cusco (Peru), 11-14 Mars 2007
Sensitivity to SEUs Evaluation using Probabilistic Testability Analysis at RTL
José Fernandes, Marcelino Bicho Dos Santos, Arlindo Oliveira, Joao Paulo Teixeira, Raoul Velazco
Single Event Transient Injection on an Operational Amplifier: A Case Study
John M. Espinosa-Duran, Jaime Velasco-Medina, Gloria Huertas, Raoul Velazco, José L. Huertas
Tools and Methodology Development for Pulsed Laser Fault Injection in SRAM-Based FPGAs
Vincent Pouget, Alexandre Douin, Dean Lewis, Pascal Fouillat, Gilles Foucard, Paul Peronnard, V. Maingot, J. B. Ferron, L. Anghel, R. Leveugle, R. Velazco SET Fault Injection Methods in Analog Circuits: Case Study
A. Ammari, Lorena Anghel, Régis Leveugle, Cristiano Lazzari, Ricardo Reis |
13th International Mixed Signals Testing Workshop and 3rd International GHz/Gbps Test Workshop, Povoa de Varzim (Portugal), June 18-20, 2007
Testing SET Effects in a CMOS Operational Amplifier
John M. Espinosa-Duran, Jaime Velasco-Medina, Gloria Huertas, Raoul Velazco, Jose L. Huertas
In: IFIP/CEDA VLSI-SoC2007, International Conference on Very Large Scale Integration, Atlanta, USA, October 15-17, 2007. pp. 312-315, ISBN: 978-1-4244-1710-0, DOI 0.1109/VLSISOC.2007.4402520.
Efficient Timing Closure with a Transistor Level Design Flow
C.Lazzari, C.Santos, A.Ziesemer, L.Anghel, R.Reis
DECIDE 2007, First International Workshop on Dependable Circuit Design, December 6-7, 2007, Buenos Aires, Argentina. P.69-74.
An experimental analysis of the lockstep architecture on the LEON case study
C.Meinhardt, M.Violante, R.Reis,M.Reorda
Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits
C.Lazzari, T.Assis, F.Kastensmidt,G.Wirth, L.Anghel, R.Reis
ETS 2008, 13th IEEE European Test Symposium, Verbania, Italy, May 25-28, 2008.
An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits
C.Lazzari, T.Assis, F.Kastensmidt,G.Wirth, L.Anghel, R.Reis
JETTA: Journal of Electronic Testing: Theory and Applications, Springer, ISSN 0923-8174 (Print) 1573-0727 (Online), Volume 23, Number 6, pp. 625-633, December 2007. DOI: 10.1007/s10836-007-5055-x.
A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis
C.Lazzari, R.Reis, L.Anghel
June 2007. ISBN 978-1-4020-5645-1
Radiation Effects on Embedded Systems
R.Velazco, P.Fouillat, R.reis
IN: VLSI-SOC: From Systems to Silicon. Springer, 2007, ISBN 978-0-387-73660-0. pp. 331- 344.
A Transistor Placement Technique Using Genetic Algorithm And Analytical Programming
C.Lazzari, R.Reis, L.Anghel
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