VDS Presentation

People
Current Members
Previous Members

  Research topics
RTL Assertion-based verification
ESL verification (SystemC TLM)
Verif. of communications in NoC's
Fast prototyping from assertions
Activity Report 2012

  Publications
After 2005
Before 2005

  Projects
ANR Project FME3
ANR Project SFINCS
Minalogic/AESE Project SoCKET
     (TIMA contribution)
MEDEA+ Project B-Dreams
Minalogic Project SHIVA


Research Areas


The design of first time correct Systems-on-Chip involves, among many other challenges, guaranteeing that the system will behave according to a specified set of functionalities. The VDS group is mainly concerned by the correctness of the hardware design, from its early specification levels (ESL, Electronic System Level) to the "register transfer" level (RTL). Among the current projects:

Group Leader: Laurence PIERRE
TIMA
46, avenue Félix Viallet
38031 GRENOBLE Cedex
France
Phone: (+33) 4 76 57 49 92
Fax: (+33) 4 76 57 49 81



This web site was last updated in May 2013

           Universito?= Joseph Fourier Institut National Polytechnique de Grenoble Centre National de la Recherche Scientifique